JPH01232451A - Memory device - Google Patents

Abstract

PURPOSE:To shorten the memory access cycle by allocating the continuous addresses to different memory elements and producing the access signal in a low-speed mode when a deciding means produces the same signals and in a high-speed mode with production of unequal signals respectively. CONSTITUTION:The different memory elements (two elements in the diagram) receive successively accesses in case the accesses are given to the continuous addresses (addresses n, n+1...). Thus it is possible to give an access to a 2nd memory element regardless of a precharging time (tRP) mode of a 1st memory element. While the accesses are carried out in a low-speed mode in consideration of said time tRP in case the accesses are given continuously to the same memory element. As a result, the memory access cycle is shortened for a memory device when the accesses are given to the continuous addresses.

Description

[Detailed Description of the Invention] (Summary) An object of the present invention is to shorten the memory access cycle in relation to a memory device, particularly in a memory device in which a plurality of memory elements are accessed by a memory access device to read and write data. , In a memory device in which multiple memory elements are accessed by a memory access device to read and write data, allocating consecutive addresses to different memory elements,
The above memory access device transmits the same signal when consecutively accessed addresses belong to the same memory element.
Further, a determining means generates a non-identical signal when the determining means generates the same signal, and an access signal generating section generates the access signal in a low speed mode when the determining means generates the same signal, and in a high speed mode when the determining means generates a non-identical signal. and configure it.

(Industrial Application Field) The present invention relates to a memory device, and particularly to a memory device in which a plurality of memory elements are accessed by a memory access device to read and write data.

[Conventional technology]

Dynamic RA is generally used as a memory element in memory devices.
M is sometimes used, but this dynamic RAM is
Row address strobe signal (RAS) and column address strobe signal (CAS) from memory access device
The address is determined and accessed to store and read data.

An example of such a memory device is the one shown in FIG. In the figure, reference numeral 10.11 denotes memory elements, and in this example, two memory elements are provided. Reference numeral 13 denotes an access control circuit that generates a RAS control signal. Further, 14 is a decoder that decodes the address signal and generates an enable signal for each memory, and 15 and 16 are AND gates that output the logical sum of the above RAS control signal and the above enable signal. The access control circuit 13, decoder 14, and AND gates 15 and 16 constitute an access control circuit.

[Problems to be Solved by the Invention] In a memory device having such a memory access control device, a so-called destructive read is performed in which data in one row of memory elements is lost when the data is read out.
It is necessary to write to the memory element immediately after performing the access. Such processing is performed immediately after RAS is disabled, and the time required for this processing is precharge time, and generally this precharge time is an access time of 100 ns to 150 ns.
For a n second memory element, 80 to 100 n seconds is required.

Therefore, when accessing address O and address 1 of the first memory element consecutively as shown in FIG. 6, the above precharge time (see FIG. If the period (indicated by the middle tRP) does not elapse,
The next address 1 cannot be accessed. That is, the memory access cycle time is access time+precharge time+α. Therefore, when a memory access device is required to access at a high speed, a delay circuit must be provided to ensure a precharge time, and there is a problem in that it is not possible to access at a higher speed.

Therefore, an object of the present invention is to provide a memory device that can shorten memory access cycles.

(Means for Solving the Problem) In the present invention, the means for solving the above problem is to access a plurality of memory elements i-, 1-2, etc. with a memory access device 2 to access data. In a memory device that performs reading and writing, consecutive addresses are allocated to different memory elements, and the memory access device issues the same signal when consecutively accessed addresses belong to the same memory element, and non-identical signals when the valve is open. By providing a determining means 3 that generates a signal and an access signal generating section 4 that generates an access signal in a low speed mode when the determining means 3 generates the same signal, and in a high speed mode when the determining means 3 generates a non-identical signal. be.

(Function) According to the present invention, when there is access to consecutive addresses (address n, address n+1, etc.) as shown in FIG. 2, different memory elements (two memory elements in the figure) are accessed one after another, so even during the precharge time (indicated by tRP in the figure) of the memory element (first memory element), other memory elements ( a second memory element). Furthermore, when accessing the same memory element continuously, it is accessed in a low-speed mode that takes precharge time into consideration. Therefore, when accessing consecutive addresses, the memory access cycle of the memory device can be shortened.

〔Example〕

Embodiments of a memory device according to the present invention will be described below with reference to the drawings.

FIGS. 3 and 4 show an embodiment of a memory device according to the present invention. In this embodiment, two memory devices are provided and consecutive addresses are alternately allocated to them. For example, address O is placed in the first memory element 20, address 1 is placed in the second memory element 21, address 3 is placed in the first memory element 20, etc. Even addresses are placed in the first memory element and odd addresses are placed in the first memory element 20. It is allocated to the second memory element.

In this embodiment, these memory elements 20 and 21
is accessed by a memory access device. In this embodiment, the memory access device has a configuration as shown in FIG.

In the figure, 22 is a decoder that decodes the address signal, determines which memory element the address belongs to, and generates an enable signal to the memory element to which the address belongs, and 23 is an access end signal. 24.25 is the decoder 22 described above;
The first and second flip-flops (FF) 26.27 latch the signal of 26.25 with the access timing signal of the access timing generation circuit, and 26.27 are the latches of the output signals of the respective flip-flops 24.25 and the access timing signal of the access timing generation circuit. Two AND gates that output a logical sum, 28.2
9 is the first one by the output of these AND gates 26 and 27
two RAS/CAS generation circuits that output a RAS signal and a CAS signal to the memory element 20 and the second memory element 21, and output an access end signal (END) to the access timing generation circuit 23 when the access is completed; It is. The first and second memory elements 20.21 are
An address is specified by the above RAS signal and CAS signal, and addresses and data are exchanged with the address bus 30 and data bus 31. Here, each RAS/
The CAS generation circuits 28 and 29 include determining means for generating the same signal when consecutively accessed addresses belong to the same memory element, and generating non-identical signals when the valve is open;
The access signal generating section generates an access signal in a low-speed mode when the determination means generates the same signal, and in a high-speed mode when it generates a non-identical signal. When generating a CAS signal, after accessing the memory, the next access is performed in an access cycle (low speed mode) that includes the time for precharging the memory element, and When one memory device is accessing the other memory element, the memory access is performed in the shortest possible access cycle (high-speed mode) regardless of the precharging of the other memory element. There is.

Next, the operation of the memory device according to this embodiment will be explained. FIG. 4 shows the operation of the memory device according to this embodiment. First, when address 0 is accessed, the selector 23 generates an enable signal on the first memory element 20 side (Sl), and the first flip-flop 24 latches this select signal based on the access timing, and uses the select latch. Generates a signal (SIL) (#A
). The first AND gate 26 receives this select latch signal and the above-mentioned access timing signal, and generates a memory access mode signal (Ml). Then, the first RAS/CAS generation circuit 28 receives this memory access mode signal (Ml), the above-mentioned access timing signal, and address select signal, and generates signals RASI and CASI (#B) to generate the first memory Identify the address of element 20. The memory device uses this RAS/CAS signal to read and write the memory. If there is an access to address l following this access to address 0, the second flip-flop 25 receives the access from the decoder 22 by the access timing signal (TA) generated in response to the access end signal (END). Latch the select signal (S2) and raise the memory access mode signal (M2) for the second memory element 21 (#C
), in response to this, the second RAS/CAS generation circuit 29 receives this memory access mode signal (M2), the above-mentioned access timing signal, and address select signal, and generates the RA
Signals S2 and CAS2 are generated (#D) to specify the address of the second memory element 2. The memory device uses this RAS/CAS signal to read and write the memory. Since the addresses accessed at this time are consecutive, different memory elements are accessed, and the second RAS/CAS generation circuit 29
The second memory element 2 can be accessed in a short memory access cycle in high-speed mode regardless of the precharge time of the second memory element.
Access 1.

When accessing address 7 next after address 1, the select signal from the decoder (
S2) is generated. The second flip-flop 25 latches the select signal (S2) from the decoder 22 in response to the access timing signal (TA) generated in response to the access end signal (END), and generates a memory access mode signal for the second memory element 21. (M2) continues to rise (#E), and in response, the second RAS/CAS generation circuit 29 receives this memory access mode signal (M2), the above-mentioned access timing signal, and address select signal. Generate a signal (#
F) Identifying the address of memory element 29.

The memory device uses this RAS/CAS signal to read and write the memory. At this time, RAS/CAS
The generation circuit 29 recognizes that the access is to the same memory element, and performs RA in the memory access cycle in the low-speed mode, which has a slower timing than the high-speed mode, which includes the precharge time from the previous access.
Raise S2 signal.

Therefore, according to this embodiment, when performing consecutive addresses, different memory elements can be accessed one after another in high-speed mode, and the overall access time of the memory device can be shortened.

In the above embodiment, two memory devices are used, but it goes without saying that there may be three or more memory devices.

〔Effect of the invention〕

As explained above, according to the present invention, consecutive addresses are allocated to different memory elements in a memory device,
The above memory access device transmits the same signal when consecutively accessed addresses belong to the same memory element.
Further, a determining means generates a non-identical signal when the determining means generates the same signal, and an access signal generating section generates the access signal in a low speed mode when the determining means generates the same signal, and in a high speed mode when the determining means generates a non-identical signal. Therefore, when accessing consecutive addresses, different memory elements can be accessed one after another in high-speed mode, and the access time of the memory device as a whole can be shortened. be effective

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a time chart showing the operation of the memory device according to the present invention, FIG. 3 is a block diagram showing an embodiment of the memory device according to the present invention, and FIG. 4 is a diagram showing the operation of the memory device according to the present invention. 3
FIG. 5 is a block diagram showing the conventional memory device, and FIG. 6 is a time chart showing the operation of the conventional memory device shown in FIG. 18,1. ...Memory element 4...Access signal generation section ■ 6 Figure

Claims (1)

[Claims] A plurality of memory elements (1_-_1), (1_-_2)...
・In a memory device that reads and writes data by accessing it with a memory access device (2), consecutive addresses are allocated to different memory elements, and the memory access device (2) is configured to access the same address continuously. determining means (3) which generates an identical signal when it belongs to a memory element, and a non-identical signal when it is non-identical; Access signal generator (which generates access signals in high-speed mode)
4) A memory device characterized by comprising: