KR0154717B1 - Memory management system - Google Patents

Abstract

1. Field of the Invention The invention relates to a memory management structure and a processing method thereof.

2. Technical problem to be solved by the present invention: The present invention has three state machines to support all banks and all access cycles, so that the memory management structure of the system in which the state machine of dynamic RAM shares and uses the state machine of ROM and It provides a processing method.

3. SUMMARY OF THE INVENTION The present invention relates to a system memory management structure having a plurality of banks composed of a memory array, wherein a cycle having a state of making a cycle, a path map having a state for the entire path, and a dynamic are provided. It is characterized by consisting of a ram path having a state for only ram.

4. Significant Uses of the Invention The present invention is suitably used in a system memory management structure.

Description

Memory Management Structure of System with State Transition Machine and Its Processing Method

1 is an overall block diagram according to the present invention.

2 is a state block diagram showing the access cycle of FIG.

3 is a state block diagram showing the access type of FIG.

4 is a schematic diagram of the state block diagram of FIG. 3 excluding transitions between states.

5a, 5b, 5c, 5d, 5e, and 5f are views showing respective states of FIG.

6 is a state block diagram showing the DRAM access type of FIG.

7 is an operation timing diagram showing an access timing of the dynamic RAM.

8 is an operation timing diagram showing an access timing of the read only memory or the static RAM.

9 is an operation timing diagram showing a refresh cycle.

10, 11, 12, and 13 degrees are operation timing diagrams showing a dynamic RAM write cycle.

The present invention relates to a memory management system, and more particularly, to a memory management system for generating a signal related to a memory according to a state transition.

State machines in memory management unit systems, in which several banks exist, are generally complex and have a large number of gates.

Accordingly, an object of the present invention is to provide a memory management and processing method of a system having three state machines supporting all banks and all access cycles, and a state transition circuit of a dynamic RAM sharing a state transition circuit of a ROM. Is in.

The technical idea of the present invention for achieving the above object is, in the memory management structure of a system having a plurality of banks composed of a memory array, a cycle which is a state circuit transitioned according to the number of access cycles, and transitions according to the access type And a pass path, which is a state circuit, and a ram path, which is a state circuit for accessing the dynamic RAM.

1 is an overall block diagram according to the present invention. Referring to FIG. 1, a cycle 1, which is an access cycle state machine driven according to an access cycle of an entire bank, and a passmap, which is a state machine according to a data access type, are described below. PATHMAP) 2, RAMPATH 3, a state machine that transitions according to the state of dynamic RAM, cycle / PGMHIT 4 involved in dynamic ram page mode and access cycles, and RAS precharge option. Block TrpCLk 5 and input / output signal generator 6).

FIG. 2 is a state transition diagram showing the cycle of FIG. Referring to FIG. 2, the signal pedal is a signal status of a state machine and becomes a reference value of various control signals. The signal wheel is applied to PATHMAP 2 as a state for another state machine, the ROM bank, to control the operation of the entire state machine. It is also supplied to the input / output signal generator 6 or the cycle / PGMHIT 4 as an input to control signals. The signal ancyle is a signal flag depending on how many clocks the access time of the bank to access has. As shown in FIG. 2, the state transition is performed according to a value between 0 and 7 in the first lock state. At this time, the clock is another form of the system clock (System clock mcke) made in the TrpCLK 5. In the state of TWOCT, ONECT, RESRT, etc., the wheel generates a pulse.

2 is a state machine (PATHMAP) for controlling the flow of the dynamic RAM state machine. Word, halfword, byte, and system in the configuration of an external memory are shown in FIG. Transition state as shown in Figure 4 according to access zone (Word, byte) of. In FIG. 2, lock refers to the idle state of the entire state, LAST refers to the last stage of the access cycle, and includes THREE, FOUR, FIVE, SIX and SEVEN are the intermediate stages of an access cycle. Also, RESRT, ONECT, and TWOCT are the steps to actually drive the state machine once.

3 is a state block diagram showing the path map 2 of FIG. That is, the overall state machine state diagram of PATHMAP 2, and FIG. 4 is a schematic state diagram of state transitions excluding transitions between states in the state diagram. In other words, in the actual state machine, it is possible to transition from other states W_HW0, 0.0, 0.2, 0.3, etc. without going from the idle state to the idle state, but in FIG. The states 0.1, 0.2, 0.3, and 0.0 are S_01, S_02, S_03, S_00, respectively, and the states 0, 1, 2, 3, etc. of FIG.

In FIG. 4, 0,11 (A0-A1: 00), etc., represent the state that the system is trying to access and the state of the physical memory. When the first value is 0, byte 1 is word. [Status required by CPU or other Master], the second value is two bits, 01 is a byte, 10 is a half-won, 11 is a word (memory state), and parentheses (A0 A1: 11) are addresses. 11 is the expression. In summary, when the CPU requests word access to a memory bank consisting of words in an initial idle state, the state transitions to the state W_W regardless of the address. As shown in PATHMAP 2, the flag is displayed. The value is 6. In addition, in each state, W_W (word-word) means that the master wants word access and the device is composed of words. W_WH (word-half word) means that the master wants word access. The device consists of halfwords, which means that four states operate. In addition, W_B (word-byte) means byte access, and the device is composed of bytes. In this case, four states operate. B_W (byte-word) means that the master wants byte access and the device is composed of words. In this case, only one of the four states is active, and B_HW (Byte-Halfword) means that the master wants to access the byte and the device is composed of halfwords, in which case only one of the two states is active. B_B (byte-byte) also means that the master wants to access the byte and the device consists of bytes.

5a, 5b, 5c, 5d, 5e, and 5f are views showing respective states of FIG. The I / O relationship between the internal data path and the memory device is described.

6 is a state block diagram showing the ram path of FIG. Referring to FIG. 6, the RAM path 3 in FIG. 1 is a state machine operated when the dynamic RAM bank is accessed. This state transitions to the precharge state when dynamic RAM access is initiated at the first idle, or to the precharge state even under the condition of the refresh state. At this time, each state is enabled or disabled according to the Trp option. This signal is output as a signal enTrp. The enTrp is applied to the TrpCLK 5 to skip the signal TCLK once so that all cycles are stretched. This means that if the precharge time is insufficient for one clock, it can be used as an option to set the time.

In the case of dynamic RAM, if the PGMHIT is activated in the signal PGMHIT 4 to support the page mode, the signal RAMPATH crosses the Low Address Strobe time (RAS time) in accordance with the page mode cycle. Let's run In this page mode, the signal acycle is changed, the flag of the cycle / PGMHIT 4 is changed, and the state of the cycle 1 is changed, so that the status of the pedal is different. Therefore, only the low address strobe time (RAS) is eliminated during the entire dynamic ram access timing. The basic cycle timing and the operation timing for the page mode cycle are shown in FIG. 7 is an operation timing diagram illustrating an access timing of the dynamic RAM. 8 is an operation timing diagram illustrating a read cycle of a read only memory (ROM) and a read write cycle of a static RAM. 9 is an operation timing diagram showing a refresh cycle. FIG. 10 is an operation timing diagram showing a result of simulation of a lead only memory cycle. 11 is an operation timing diagram for sending a result of a simulation of a refresh cycle. FIG. 12 is an operation timing diagram for sending a simulation result of a dynamic RAM cycle. FIG. 13 is an overall operation timing diagram according to a simulation result. Referring to FIG. 13, this timing is a case where the memory has a half word and two cycle access time when the ROM is accessed (when read). The result is a simulation of a refresh cycle with 7 cycles and a dynamic write cycle (byte access word).

As described above, the present invention allows three state machines to support all banks and all access cycles, so that the state machine of the dynamic RAM shares the state machine of the ROM.

Although the present invention described above is limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the present invention.

Claims (6)

In the memory management structure of a system having a plurality of banks composed of a memory array, a cycle for a state circuit transitioned according to the number of access cycles, a path map for a state circuit transitioned according to the access type, and access for dynamic RAM A memory management structure comprising RAMpaths, which are state circuits. 2. The memory management structure of a system as recited in claim 1, wherein said pathmap is a state machine for driving a ROM or static RAM with a state transition circuit of said entire circuit. The dynamic RAM state machine of claim 1, wherein the RAM path is operated by referring to a path map having a state of the ROM, for example, a dynamic RAM driving state transition circuit and another state transition circuit for any specific purpose. The memory structure of the system, characterized in that. The memory management structure of claim 1, wherein the bicycle has a configuration of skipping or stretching a clock of the passmap and the RAM pass according to an option of a predetermined clock. A method of managing a system memory having a plurality of banks composed of memory arrays, the method comprising: a first process of processing a memory state of a dynamic RAM with a dynamic RAM state machine which varies access cycle times of the memory array and operates the access cycle; And a second process of processing the memory state of the ROM by a ROM state machine, and the first process and the second process are not separated separately, and the memory is processed in one process. The method of claim 5, wherein the first and second processes are repeated a plurality of times to access the memory array.