KR970049586A - Memory Management Structure of System with State Transition Machine and Its Processing Method - Google Patents

Memory Management Structure of System with State Transition Machine and Its Processing Method Download PDF

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Publication number
KR970049586A
KR970049586A KR1019950047551A KR19950047551A KR970049586A KR 970049586 A KR970049586 A KR 970049586A KR 1019950047551 A KR1019950047551 A KR 1019950047551A KR 19950047551 A KR19950047551 A KR 19950047551A KR 970049586 A KR970049586 A KR 970049586A
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South Korea
Prior art keywords
state
memory
management structure
memory management
ram
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KR1019950047551A
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Korean (ko)
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KR0154717B1 (en
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서운식
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김광호
삼성전자 주식회사
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Priority to KR1019950047551A priority Critical patent/KR0154717B1/en
Publication of KR970049586A publication Critical patent/KR970049586A/en
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Publication of KR0154717B1 publication Critical patent/KR0154717B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Dram (AREA)

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야: 본 발명은 메모리 관리 구조 및 그 처리 방법에 관한 것이다.1. Field of the Invention The invention relates to a memory management structure and a processing method thereof.

2. 발명이 해결하려고 하는 기술적 과제: 본 발명은 상태 머신 3개를 가지고 모든 뱅크와 모든 엑세스 싸이클을 지원하게 하여 다이나믹 램의 상태 머신이 롬의 상태 머신을 공유하여 사용하는 시스템의 메모리 관리 구조 및 그 처리 방법을 제공한다.2. Technical problem to be solved by the present invention: The present invention has three state machines to support all banks and all access cycles, so that the memory management structure of the system in which the state machine of dynamic RAM shares and uses the state machine of ROM and It provides a processing method.

3. 발명의 해결방법의 요지: 본 발명은 메모리 어레이로 구성된 다수개의 뱅크를 가지는 시스템 메모리 관리 구조에 있어서, 싸이클을 만드는 상태를 가지는 바이싸이클과, 전체 경로를 위한 상태를 가지는 패스맵과, 다이나믹 램만을 위한 상태를 가지는 램패스로 구성됨을 특징으로 한다.3. SUMMARY OF THE INVENTION The present invention relates to a system memory management structure having a plurality of banks composed of a memory array, wherein a cycle having a state of making a cycle, a path map having a state for the entire path, and a dynamic are provided. It is characterized by consisting of a ram path having a state for only ram.

4. 발명의 중요한 용도 : 본 발명은 시스템 메모리 관리 구조에 적합하게 사용된다.4. Significant Uses of the Invention The present invention is suitably used in a system memory management structure.

Description

상태 천이 머신을 가지는 시스템의 메모리 관리 구조 및 그 처리 방법Memory Management Structure of System with State Transition Machine and Its Processing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 전체 블록도.1 is an overall block diagram according to the present invention.

제2도는 제1도의 엑세스 싸이클을 나타내는 상태블록도.2 is a state block diagram showing the access cycle of FIG.

Claims (6)

메모리 어레이로 구성된 다수개의 뱅크를 가지는 시스템의 메모리 관리 구조에 있어서, 엑세스 싸이클수에 따라 천이되는 상태 회로인 바이싸이클과, 엑세스 형태에 따라 천이되는 상태 회로인 패스맵과, 다이나믹 램의 엑세스를 위한 상태 회로인 램패스로 구성됨을 특징으로 하는 메모리 관리 구조.In the memory management structure of a system having a plurality of banks composed of a memory array, a cycle for a state circuit transitioned according to the number of access cycles, a path map for a state circuit transitioned according to the access type, and access for dynamic RAM A memory management structure comprising RAMpaths, which are state circuits. 제1항에 있어서, 상기 패스맵이 상기 전체 회로의 상태 천이회로로 롬이나 스태틱 램을 구동하는 상태 머신임을 특징으로 하는 시스템의 메모리 관리 구조.2. The memory management structure of a system as recited in claim 1, wherein said pathmap is a state machine for driving a ROM or static RAM with a state transition circuit of said entire circuit. 제1항에 있어서, 상기 램패스가 상기 롬의 상태를 가지는 패스맵을 참조하여 동작되는 예를 들면 다이나믹 램 구동상태 천이회로와 어떤 특정용도의 다른 상태 천이회로가 연동하여 동작되는 다이나믹 램 상태 머신임을 특징으로 하는 시스템의 메모리 관리 구조.2. The dynamic RAM state machine according to claim 1, wherein the RAM pass is operated by referring to a pass map having a state of the ROM, for example, a dynamic RAM driving state transition circuit and another state transition circuit for any specific purpose. The system's memory management structure. 제1항에 있어서, 상기 바이싸이클이 소정클럭의 옵션에 따라 상기 패스맵, 램 패스의 클럭을 스킵 또는 스트레치하는 구성을 가짐을 특징으로 하는 메모리 관리 구조.The memory management structure of claim 1, wherein the bicycle has a configuration of skipping or stretching a clock of the passmap and the RAM pass according to an option of a predetermined clock. 메모리 어레이로 구성된 다수개의 뱅크를 가지는 시스템 메모리 관리 방법에 있어서, 상기 메모리 어레이의 엑세스 싸이클 시간이 다양하며, 상기 엑세스 싸이클을 동작시키는 다이나믹 램 상태 머신으로 다이나믹 램의 메모리 상태를 처리하는 제1과정과, 롬 상태 머신으로 롬의 메모리 상태를 처리하는 제2과정과, 상기 제1과정과 제2과정이 따로 분리되어 있지 않고 하나의 과정으로 상기 메모리를 처리함을 특징으로 하는 시스템의 메모리 관리 방법.A method of managing a system memory having a plurality of banks composed of memory arrays, the method comprising: a first process of processing a memory state of a dynamic RAM with a dynamic RAM state machine which varies access cycle times of the memory array and operates the access cycle; And a second process of processing the memory state of the ROM with a ROM state machine, and the first process and the second process are not separated separately, and the memory is processed in one process. 제5항에 있어서, 상기 제1, 제2과정이 다수번 반복되어 상기 메모리 어레이를 엑세스함을 특징으로 하는 시스템의 메모리 관리 방법.The method of claim 5, wherein the first and second processes are repeated a plurality of times to access the memory array. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950047551A 1995-12-07 1995-12-07 Memory management system KR0154717B1 (en)

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KR1019950047551A KR0154717B1 (en) 1995-12-07 1995-12-07 Memory management system

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KR1019950047551A KR0154717B1 (en) 1995-12-07 1995-12-07 Memory management system

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KR970049586A true KR970049586A (en) 1997-07-29
KR0154717B1 KR0154717B1 (en) 1998-11-16

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US6839797B2 (en) * 2001-12-21 2005-01-04 Agere Systems, Inc. Multi-bank scheduling to improve performance on tree accesses in a DRAM based random access memory subsystem

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