JPH0863997A - Semiconductor memory circuit device - Google Patents

Abstract

PURPOSE: To shorten a test time by making forcedly a write-in acknowledge signal from an address decoder section an activation state in accordance with a test control signal and forcedly fixing data given to a bit line by an IO section an H state or an L state. CONSTITUTION: When a test control signal 3 is made H, a first write-in acknowledge signal 6 from an address decoder section 10 is made an activation state by a test pattern write-in control section 11, made a second write-in acknowledge signal 7 selecting one word from a memory 12 and acknowledging write-in, and supplied to a memory cell array 12. On the other hand, when the signal 3 is made H, a 3-state buffer circuit 23 of a test pattern generation circuit 13 is activated, a state buffer circuit 24 of an IO section 14 is made a non- activation state, input data 2 from an IO section 10 is forcedly fixed to H or L, test data 4 is supplied to a bit line 8 through the generation section 13. Thereby, write-in can be continuously performed without writing test data every one word, and a test time can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to writing test data in the memory device.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have been highly integrated, and a plurality of LSI chips have been integrated into one chip. On-chip memories such as registers and caches for general-purpose logic LSIs are now common sense. Conventionally, the bit test of these memories mainly uses a checker pattern or the like, but writing is performed by designating an address word by word.

[0003]

However, in the above method, the time required for writing the test pattern in the large-capacity memory becomes long, and there is a problem that the entire test time is increased and the manufacturing cost is suppressed. Had.

Therefore, the present invention has been made in view of the above point, and an object thereof is not to write a test pattern of a memory for each word as in the prior art, but to enable a plurality of writing simultaneously. It is to reduce the test time.

[0005]

In order to solve the above-mentioned problems, a semiconductor memory circuit device of the present invention selects a memory array section for recording data and one word of the memory array section from an address and permits writing. An address decoder section for giving a signal and data for giving to the bit line of the memory array section or for giving the data of the memory array section to the outside according to a write control signal and a read control signal I
An O section, a test pattern write control section for forcibly activating or deactivating a write enable signal output from the address decoding section according to a test control signal, and a test for data given from the IO section to a bit line of the memory array section. It is provided with a test pattern generation unit for forcibly fixing it to "H" or "L" according to a control signal.

[0006]

According to the present invention, the write enable signal output from the address decoding section can be forcibly activated in accordance with the test control signal by the above-described configuration, and at the same time, the bit line of the memory array section in the test pattern generating section is activated. Forcibly give data "H" or "according to the test control signal"
It can be fixed to L ".

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory circuit device according to an embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a circuit diagram of a semiconductor memory circuit device according to an embodiment of the present invention, and particularly shows a configuration relating to a write operation.

In FIG. 1, 1 is an address, 2 is input data, 3 is a test control signal, 4 is test data, 5 is a write control signal, 6 is a first write enable signal, and 7 is a second write enable signal. , 8 are write data.

An address decoder unit 10 selects one word in the memory array unit from an address and gives a write enable signal 7. Reference numeral 11 is a test pattern write control unit that forcibly activates or deactivates the write enable signal 6 output from the address decoding unit 10 according to the test control signal 3.

Reference numeral 12 denotes a memory array section for recording data,
Reference numeral 13 is a test pattern generation unit for forcibly fixing the data given from the IO unit to the bit line of the memory array unit 12 to "H" or "L" according to the test control signal 3. 1
Reference numeral 4 denotes an IO unit for giving data to the bit line of the memory array unit or for giving data of the memory array unit to the outside according to a write control signal 5 and a read control signal,
The read control signal is omitted in the drawing.

20, 21 are inverter circuits, 22 is an
d / or circuit, 23 and 24 are 3-state buffer circuits,
25 is an and circuit.

The operation of the semiconductor memory circuit device configured as described above in the case of a 2-bit address and 2-bit data configuration will be described below with reference to FIG.

(1) When the write control signal 5 is "H" and the test control signal 3 is "L", the input of one of the and-or circuits 22 of the test pattern write control section is "L". Therefore, the output reflects the first write enable signal output from the address decoder section, and only one specific word in the memory array section becomes writable. At this time, the output of the AND circuit 25 becomes "H" 3
Since the state buffer circuit 24 is activated and the 3-state buffer circuit 23 is deactivated, the input data 2 is reflected in the write data 8. As a result, the input data 2 is written in the specific one word of the memory array shown above.

(2) When the write control signal 5 is "H" and the test control signal 3 is "H", the input of the other and circuit of the and-or circuit 22 of the test pattern write control section is "L". Therefore, the output is the 0th bi of address 1.
Reflecting t, when the 0th bit is "L", the even-numbered word of the memory array section becomes writable, and when it is "H", the odd-numbered word of the memory array section becomes writable. At this time, the output of the and circuit 25 becomes “L”, the 3-state buffer circuit 24 is deactivated, and the 3-state buffer circuit 23 is activated, so that the test data 4 is reflected in the write data 8. As a result, the test data 4 is simultaneously written to the odd or even word of the memory array shown above. Particularly in this operation, tdata [0] = 0 of the test data 4 at the time of writing an odd number of words,
tdata [1] = 1, and tdata [0] = 1, tdata of the test data 4 when writing an even word.
By setting [1] = 0, the memory array unit 12 has 2
The checker pattern can be written in one write cycle.

[0016]

As described above, according to the present invention, a memory array section for recording data, an address decoder section for selecting one word of the memory array section from an address and a write enable signal and giving a write enable signal, and a write An IO unit for giving data to the bit line of the memory array unit or for giving data of the memory array unit to the outside according to a control signal and a read control signal, and a write enable signal issued from the address decoding unit are used as test control signals. A test pattern write control unit that is forcibly activated or inactivated according to the test pattern, and data that is given from the IO unit to the bit line of the memory array unit is forcibly "H" according to the test control signal.
Alternatively, by providing a test pattern generation unit that fixes to “L”, it was possible to realize the test pattern generation in two write cycles, although 2 ^ (number of addresses) write cycles were required to write the checker pattern in the conventional memory array. It is possible to significantly reduce the time.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory circuit device according to a first embodiment of the present invention.

[Explanation of symbols]

 1 address 2 input data 3 test control signal 4 test data 5 write control signal 6 first write enable signal 7 second write enable signal 8 write data 10 address decoder section 11 test pattern write control section 12 memory array section 13 test pattern Generation unit 14 IO unit 20, 21 Inverter circuit 22 and-or circuit 23, 24 3-state buffer circuit 25 and circuit

Claims (1)

[Claims] 1. A memory array section for recording data, an address decoder section for selecting one word of the memory array section from an address and giving a write enable signal, and the memory array according to a write control signal and a read control signal. And a test pattern for forcibly activating or deactivating a write enable signal output from the address decoding unit according to a test control signal, and an IO unit for applying data to a bit line of the memory unit or data of the memory array unit to the outside. A semiconductor memory circuit device comprising a write control unit and a test pattern generation unit for forcibly fixing data given from an IO unit to a bit line of a memory array unit to "H" or "L" according to a test control signal.