JPH0474378A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To attain high speed access by forming a control circuit and 1st and 2nd memory cell array parts into one chip. CONSTITUTION:The device is constituted in such a way that one cycle is formed by two cycles of a row address strobe signal from a CPU 10, and a period of an active level is lengthened to be longer than a period of nonactive level, and then 1st and 2nd row address strobe signals deviated from each other by one cycle of the row address strobe signal from the CPU are generated to access the 1st and 2nd memory cell array parts 2A and 2B. By this method, one cycle of the row address strobe signal from the CPU 10 is shortened, and hence the high speed access is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a dynamic type semiconductor memory device.

[Conventional technology]

Conventionally, in this type of semiconductor memory device, after the row address strobe signal RAS falls, the word line, sense amplifier, etc. are activated to perform reading and writing, and after the row address strobe signal RAS rises, the word line is activated. Although the sense amplifier is inactivated, there is a precharge period before reading and writing, which increases the cycle time for one access. Therefore, when high-speed operation is required, in order to shorten the cycle time for one access, two or more memory cell array sections are used and operated sequentially to shorten the apparent cycle time for one access. was.

FIG. 3 shows a configuration when two memory cell arrays are used, and FIG. 4 shows a timing chart of signals of each part.

The memory controller 20 uses the memory cell array 30A when accessing consecutive addresses at high speed.

30B and when accessing the same memory cell array, a standby request signal WAIT is output at a predetermined timing to the CPU 10A to request it to stand by.

The timing chart shows the row address strobe signal RASA from the CPU 1OA and the memory cell array 30.
Row address strobe signal RAS for A, 30B
IA, RAS 2A, and memory cell array 30A, 3
Only output data DTO1 and DTO2 from 0B are shown.

Since memory cell arrays 30A and 30B are accessed alternately, twice as much data is sent to data bus 40 in a single time as when only one memory cell array is used.

Row address strobe signals RAS IA and RAS 2A for each memory cell array 30A and 30B are CP
It is formed by dividing the row address strobe signal RASA from U10A by 1/2 and its inverted signal, and the low level period of the active level and the high level period of the inactive level are the same time. There is.

[Problem to be solved by the invention]

The conventional semiconductor memory device described above has a structure in which two or more memory cell arrays (30A, 30B) are operated alternately to apparently shorten the cycle time for one access.
Row address strobe signal RAS IA for 0B
, low levels of RAS 2A.

Since the high level is for the same time, the row address strobe signals RAS IA, RAS
One cycle of 2A requires twice the period of low level, which has the drawback of limiting speedup.

An object of the present invention is to provide a semiconductor memory device that can speed up access.

[Means to solve the problem]

The semiconductor memory device of the present invention inputs control signals including a row address strobe signal and write/read control signals from the CPU, and becomes active at the leading edge of the row address strobe signal to the active level in one cycle. a first control signal including a first row address strobe signal that repeats a cycle in which it becomes inactive after a predetermined time delay from the leading edge of the active level in the next cycle;
The first row address is shifted by one cycle of the row address strobe signal from the CPU with respect to the strobe signal.
a control circuit that outputs a second control signal including a second row address strobe signal that repeats a cycle of being at an active level and an inactive level similarly to the strobe signal; and writing data in accordance with the first control signal. , a first memory cell array section for reading data, and a second memory cell array section for writing and reading data in accordance with the second control signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram illustrating an example of the implementation of the present invention.

This embodiment inputs a row address strobe signal RAS from CPU10, control signals including a write/read control signal WE, and an address signal AD, and at the leading edge of the row address strobe signal RAS to an active level in one period. A first control signal (RAS 1.CNT l) including a first row address strobe signal RASI that repeats a cycle of becoming active and becoming inactive after a predetermined time delay from the leading edge of the active level of the next cycle; , and the period at which the first row address strobe signal RAS from CPUl0 is shifted by one period from the first row address strobe signal RASI to the active level and the inactive level similarly to the first row address strobe signal RAS1. The second row address that repeats
A second control signal (RAS
2. CNT2) and first and second address signals ADI
, AD2, and a first control signal (
RAS 1.

CNTI) and an address signal ADI, a first memory cell array section 2A that writes and reads data according to the address signal ADI;
It has a configuration including a second memory cell array section 2B that writes and reads data in accordance with the second control signal (RAS2.CNT2) and address signal AD2,
Control circuit 1. The memory cell array sections 2A and 2Y are formed on one chip (semiconductor chip 100).

Next, the operation of this embodiment will be explained.

FIG. 2 is a timing chart of various signals during a read operation to explain the operation of this embodiment.

First and second row address strobe signals RAS1.
In RAS2, two cycles of the row address strobe signal RAS from cPUlo form one cycle, and these are shifted from each other by one cycle of the row address strobe signal RAS.

The memory cell array sections 2A and 2B receive corresponding row address strobe signals RAS 1 and RAS 2, respectively.
Since the read operation is performed at the active level of , that is, the low level, the row address strobe signal RAS is at the active level (
low level), the memory cell array sections 2A and 2B
Data DTOI and DTO are alternately sent from data bus 4o to data bus 4o.
2 is output.

Here, the row address strobe signal RASI.

The active level (low level) period of RAS2 is a constant time ΔT longer than one period of the row address strobe signal RAS.
, and the inactive level (high level) period is shortened by that amount. By making the periods equal to the active level periods of IA and RAS2A, one period of the row address strobe signal RAS of this embodiment can be made shorter than one period of the row address strobe signal RASA of the conventional example, and accesses can be It can be made faster.

In addition, in order to operate at high speed, conventionally, even if the required memory capacity is small, two memory cell arrays 30A are required.
, 30. However, in this embodiment, since the control circuit 1 and the memory array sections 2A and 2B are integrated into one chip to form the semiconductor memory chip 100, one semiconductor memory chip 100 is required to be prepared. The advantage is that you only need to prepare.

Note that when only one of the memory cell array sections 2A and 2B is used, the standby request signal WAIT is output to the CPU 1O at a predetermined timing, as in the conventional example.

[Effects of the Invention] As explained above, in the present invention, two cycles of the row address strobe signal from the CPU form one cycle, and the period of the active level is longer than the period of the inactive level. By generating the first and second row address strobe signals that are shifted by one period of the row address strobe signal to access the first and second memory cell array sections, the row address strobe signal from the CPU is accessed. address·
Since one period of the strobe signal can be shortened,
This has the effect of speeding up access.

[Brief explanation of the drawing]

1 and 2 are respectively a block diagram of an embodiment of the present invention and a timing chart of each part signal for explaining the operation of this embodiment, and FIGS. 3 and 4 are respectively a diagram of a conventional semiconductor memory device. 2 is a block diagram showing an example and a timing chart of signals of each part for explaining the operation of this example. FIG. 1...control circuit, 2A, 2. ...Memory cell array section, 10, 10A--CPU, 20
・=-Memory control, OA. OB...Memory cell array, 0...Data bus, 00...Semiconductor memory chip.

Claims (1)

[Claims] 1. A control signal including a row address strobe signal and a write/read control signal from the CPU is input, and becomes an active level at the leading edge of the row address strobe signal to an active level in one cycle. The first cycle repeats a cycle in which the inactive level is reached after a predetermined time delay from the leading edge of the active level in the next cycle.
a first control signal comprising a row address strobe signal of C;
A second row address strobe signal including a second row address strobe signal that is shifted by one cycle of the row address strobe signal from the PU and repeats a cycle of being at an active level and an inactive level similarly to the first row address strobe signal. a control circuit that outputs a control signal; a first memory cell array unit that writes and reads data in accordance with the first control signal; and a second memory cell array unit that writes and reads data in accordance with the second control signal. 1. A semiconductor memory device comprising a memory cell array section. 2. The semiconductor memory device according to claim 1, wherein the control circuit and the first and second memory cell array sections are formed on one chip.