JPH012323A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPH012323A
JPH012323A JP62-158011A JP15801187A JPH012323A JP H012323 A JPH012323 A JP H012323A JP 15801187 A JP15801187 A JP 15801187A JP H012323 A JPH012323 A JP H012323A
Authority
JP
Japan
Prior art keywords
film
etching
insulating film
dummy
dummy film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62-158011A
Other languages
Japanese (ja)
Other versions
JPS642323A (en
Inventor
善行 酒井
Original Assignee
富士電機株式会社
Filing date
Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP15801187A priority Critical patent/JPS642323A/en
Priority claimed from JP15801187A external-priority patent/JPS642323A/en
Publication of JPH012323A publication Critical patent/JPH012323A/en
Publication of JPS642323A publication Critical patent/JPS642323A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、半導体基板上に部分的に形成された電極また
は配線上を絶縁膜が被覆してさらに、例えば第二層配線
を形成する半導体装置の製造方法に関する。
Detailed Description of the Invention (Industrial Application Field) The present invention relates to a semiconductor device in which an insulating film covers an electrode or wiring partially formed on a semiconductor substrate, and further forms, for example, a second layer wiring. The present invention relates to a method for manufacturing a device.

〔従来の技術〕[Conventional technology]

半導体基板上に部分的に存在する電極または配線をSi
J、あるいは5iJ4などからなる絶縁膜で覆うと絶縁
膜表面に段差が生ずる。この絶縁膜の上に第二層配線を
形成するとき段差部で断線が生じやすいので、それを防
ぐために表面の平坦化が必要となる。この平坦化の一つ
の方法としてvA縫縫上上ダミー膜としてレジストを被
覆して表面を平坦化したのち、ダミー膜と絶縁膜とのエ
ツチング速度がほぼ等しくなるエツチング条件を選択し
て平坦を保ったままダミー膜を除去するエッチバンク法
が知られている。
The electrodes or wiring that partially exist on the semiconductor substrate are
If it is covered with an insulating film made of J or 5iJ4, a step will be created on the surface of the insulating film. When forming the second layer wiring on this insulating film, disconnection is likely to occur at the stepped portion, so the surface needs to be flattened to prevent this. One method for flattening is to flatten the surface by coating a resist as a dummy film on the vA sewing, and then maintain flatness by selecting etching conditions that make the etching rates of the dummy film and insulating film almost equal. An etch bank method is known in which the dummy film is removed as is.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、このようなエッチバンク法を用いても、ダミー
膜が薄い場合にはダミー膜被ri後の表面が十分に平坦
でなく段差が残っている。この状態で表面のダミー膜を
エツチングしていき、絶縁膜を露出させると、絶縁膜の
表面は残ったダミー膜の表面より高くなる。さらにエツ
チングを進めても、ダミー膜と絶縁膜のエツチング速度
がほぼ等しいためその段差は解消されず、ダミー膜を全
部除去したあとの絶縁膜表面が十分平坦にならない欠点
があった。ダミー膜を厚くすればこの欠点はある程度低
減されるが、ダミー膜の材料を多量に必要とし、ダミー
膜除去のために長い処理時間を要するなどの欠点がある
However, even if such an etch bank method is used, if the dummy film is thin, the surface after the dummy film is coated is not sufficiently flat and a step remains. In this state, when the dummy film on the surface is etched to expose the insulating film, the surface of the insulating film becomes higher than the surface of the remaining dummy film. Even if the etching is further carried out, the difference in level cannot be eliminated because the etching speed of the dummy film and the insulating film are almost the same, and there is a drawback that the surface of the insulating film cannot be sufficiently flat after the dummy film is completely removed. This drawback can be reduced to some extent by making the dummy film thicker, but it requires a large amount of material for the dummy film and requires a long processing time to remove the dummy film.

本発明の目的は、ダミー膜被覆後の表面に多少の段差が
生じても、エッチング後の絶縁膜表面が平坦化するよう
にした半導体装置の製造方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which the surface of an insulating film after etching is flattened even if some steps are formed on the surface after being coated with a dummy film.

〔問題点を解決するための手段〕[Means for solving problems]

上記の目的を達成するために、本発明の方法は、半導体
基板上の表面に段差を有する絶縁膜の上をダミー膜で被
覆したのち、ダミー膜と絶!!膜のエツチング速度がほ
ぼ等しくなる条件でダミー膜が除去されるまでエツチン
グする際に、そのエツチング工程の中間において絶縁膜
が露出したのち、絶縁膜のみをエツチングする工程を挿
入するものとする。
In order to achieve the above object, the method of the present invention covers an insulating film having a step on the surface of a semiconductor substrate with a dummy film, and then separates the dummy film. ! When etching is performed until the dummy film is removed under conditions where the etching rates of the films are approximately equal, the insulating film is exposed in the middle of the etching process, and then a step of etching only the insulating film is inserted.

〔作用〕[Effect]

表面のダミー膜をエツチングしていき、絶縁膜の一部を
露出させたときに上述のように生じている絶縁膜、とダ
ミー膜の間の段差は、絶縁膜のみのエツチングをするこ
とにより解消するので平坦な表面が得られ、その後、ダ
ミー膜と絶縁膜をほぼ等しいエツチング速度でエツチン
グしてダミー膜を除去すれば、平坦な絶縁膜の表面が生
ずる。
When the dummy film on the surface is etched and a part of the insulating film is exposed, the difference in level between the insulating film and the dummy film, which occurs as described above, can be eliminated by etching only the insulating film. Therefore, a flat surface is obtained, and if the dummy film is removed by etching the dummy film and the insulating film at approximately the same etching rate, a flat surface of the insulating film is obtained.

〔実施例〕〔Example〕

第1図は本発明の一実施例のエッチバック法の工程を示
し、第1図(alにおいてシリコン基vi1には表面に
導電性の多結晶シリコン膜あるいはA7−   ’St
合金膜などにより厚さ1nの配線2が形成されている。
FIG. 1 shows the steps of an etch-back method according to an embodiment of the present invention.
A wiring 2 having a thickness of 1n is formed of an alloy film or the like.

この上に絶縁のためのSingまたはSi3N4からな
る厚さ約1−の膜3が被覆されている。この絶縁膜3の
表面には、導電膜2の存在によって生ずる段差があり、
この上を被覆する厚さ1〜2μのポジ型ホトレジスト膜
4は、絶縁膜3の高い部分には薄<、低い部分には厚く
塗布されるが、それでもなお表面に段差りが残る。次に
、第1開山)に示すように絶縁膜3の配線2の上の高い
部分31の表面が多少エツチングされる程度まで反応性
イオン5によってドライエツチングする。このドライエ
ツチングは、主エツチングガスと02の混合ガス中にプ
ラズマを発生させてホトレジスト膜4と絶&il!!3
のエツチング速度がほぼ等しい条件でエツチングするの
で、寒色縁膜31の表面とホトレジスト膜4の表面の間
に段差りが残る0次いで、この状態からホトレジスト膜
4より少し高く露出した絶縁膜31のみをエツチングし
、第1図(e)に示すようにホトレジスト膜4と絶縁膜
3の高い部分の表面の高さが等しくなるようにする。こ
の段階においては、主エツチングガスに03ガスを数%
添加した混合ガス中でプラズマを発生させてドライエツ
チングを行い、絶縁1113のみがエツチングされ、ホ
トレジスト膜4との選択比が高くなるようにエツチング
条件を決める。さらにこの状態から、最初の段階と同じ
ように主エツチングガスと0□の混合ガスを用いてホト
レジスト膜4と絶縁膜3のエツチング速度がほぼ等しい
条件でエツチングを行い、第1図(d+に示すようにホ
トレジスト膜4が除去された点でドライエツチングを停
止する。主エツチングガスは、絶縁膜がSingのとき
は、CF、。
A film 3 of about 1-thickness made of Sing or Si3N4 for insulation is coated on this. The surface of this insulating film 3 has a step caused by the presence of the conductive film 2.
The positive photoresist film 4 having a thickness of 1 to 2 μm is applied thinly to the high parts of the insulating film 3 and thickly to the low parts, but a step still remains on the surface. Next, as shown in FIG. 1), dry etching is performed using reactive ions 5 to the extent that the surface of the high portion 31 above the wiring 2 of the insulating film 3 is slightly etched. In this dry etching, plasma is generated in the mixed gas of the main etching gas and 02 to completely separate the photoresist film 4. ! 3
Since the etching is carried out under conditions where the etching speed is approximately equal, a step remains between the surface of the cold-color border film 31 and the surface of the photoresist film 4.Next, from this state, only the insulating film 31 exposed slightly higher than the photoresist film 4 is etched. Etching is performed so that the surface heights of the high portions of the photoresist film 4 and the insulating film 3 are made equal as shown in FIG. 1(e). At this stage, a few percent of 03 gas is added to the main etching gas.
Dry etching is performed by generating plasma in the added mixed gas, and etching conditions are determined so that only the insulation 1113 is etched and the etching selectivity with respect to the photoresist film 4 is high. Further, from this state, as in the first stage, etching was performed using the main etching gas and a mixed gas of 0 □ under conditions where the etching speed of the photoresist film 4 and the insulating film 3 were almost equal. The dry etching is stopped at the point where the photoresist film 4 is removed.The main etching gas is CF when the insulating film is Sing.

CHF3.5iJaのときはCFオ、SF4.NF2を
用いる。エツチング段階の切換えおよび終点の決定は、
エツチング中にプラズマ発生のモニタリングを行い、被
エツチング材料の変化に伴う発光強度の変化を検出する
ことによって行う0以上のようなエツチング法によれば
、平坦化用ダミー膜4の段差を途中の絶縁膜3のエツチ
ングで緩和することができるので、ダミー膜4の表面に
多少の段差があっても絶縁膜の平坦な表面を得ることが
できる。なお上記の実施例では、ダミー膜4としてホト
レジストを用いているが、他の材料を用いても同様に実
施できる。
When CHF3.5iJa, CF O, SF4. Use NF2. Switching the etching stage and determining the end point
According to the above etching method, which is performed by monitoring plasma generation during etching and detecting changes in emission intensity due to changes in the material to be etched, the steps of the planarizing dummy film 4 are insulated in the middle. Since this can be alleviated by etching the film 3, a flat surface of the insulating film can be obtained even if there is some level difference on the surface of the dummy film 4. In the above embodiment, photoresist is used as the dummy film 4, but other materials may be used as well.

〔発明の効果〕 本発明によれば、平坦化用ダミー膜の表面にあった段差
を途中の露出絶縁膜のエツチングにより緩和することが
できるので、ダミー膜があまり平坦化されていなくても
、平坦化された表面を有する絶縁膜を得ることができる
。従って、ダミー膜を薄くすることができるので処理時
間が短縮し、半導体装置の!!造工数の低減に有効であ
る。
[Effects of the Invention] According to the present invention, the level difference on the surface of the dummy film for planarization can be alleviated by etching the exposed insulating film in the middle, so even if the dummy film is not very planarized, An insulating film having a flattened surface can be obtained. Therefore, since the dummy film can be made thinner, processing time can be shortened and semiconductor devices can be improved. ! Effective in reducing manufacturing man-hours.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例におけるエッチバツク法の
工程を順次示す断面図である。 1:シリコン基板、2:配線、3:絶縁膜、4:ポジレ
ジスト膜、5:反応性イオン。 1.・ぐ゛。 s1図
FIG. 1 is a cross-sectional view sequentially showing steps of an etchback method in an embodiment of the present invention. 1: Silicon substrate, 2: Wiring, 3: Insulating film, 4: Positive resist film, 5: Reactive ions. 1.・Guh. s1 diagram

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板上の表面に段差を有する絶縁膜の上に
ダミー膜を被覆したのち、ダミー膜と絶縁膜のエッチン
グ速度がほぼ等しくなる条件でダミー膜が除去されるま
でエッチングする際に、該エッチング工程の中間におい
て絶縁膜を露出したのち絶縁膜のみをエッチングする工
程を挿入することを特徴とする半導体装置の製造方法。
(1) After covering an insulating film with a step on the surface of a semiconductor substrate with a dummy film, etching is performed until the dummy film is removed under conditions such that the etching rates of the dummy film and the insulating film are approximately equal. A method for manufacturing a semiconductor device, comprising inserting a step in the middle of the etching step in which the insulating film is exposed and then only the insulating film is etched.
JP15801187A 1987-06-25 1987-06-25 Manufacture of semiconductor device Pending JPS642323A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15801187A JPS642323A (en) 1987-06-25 1987-06-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15801187A JPS642323A (en) 1987-06-25 1987-06-25 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPH012323A true JPH012323A (en) 1989-01-06
JPS642323A JPS642323A (en) 1989-01-06

Family

ID=15662313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15801187A Pending JPS642323A (en) 1987-06-25 1987-06-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS642323A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2527555Y2 (en) * 1990-05-18 1997-03-05 日産自動車株式会社 Air bypass device for internal combustion engine with supercharger

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