JPH01231093A - Video signal generating circuit for crt display device - Google Patents

Abstract

PURPOSE:To erase a retrace line without increasing the number of parts and producing any data delay and to improve the speed of processing by making a load timing signal effective by using a display-enable signal. CONSTITUTION:By making a load timing signal LOAD effective by using a display-enable signal DSPE, parallel video data to be displayed is loaded on a parallel-serial converting circuit 11 which converts the parallel video data into serial video data VIDEO. The serial video data VIDEO is outputted from the circuit 11. When no parallel video data is inputted to the parallel-serial converting circuit 11, serial data of a non-displaying level are outputted and retrace line erasion is performed. Therefore, a retrace line can be erased without increasing the number of parts and producing any data delay and, as a result, the processing speed can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a video signal generation circuit for a CRT display device, and particularly to a blanking control circuit.

(Prior Art) FIG. 2 is a block diagram showing an example of a conventional CRT display device. 21 is a video clock generating section, 22 is a display control signal generating section, and 23 is a video memory section.

24 is a video conversion section, and 25 is a CRT display section.

The video clock generator 21 supplies a video clock CLK to the display control signal generator 22 and the video converter 24.

The display control signal generation section 22 supplies a memory control signal MC to the video memory section 23, and a display enable signal DSPE and a load timing signal LOAD to the video conversion section 24.

Furthermore, a horizontal synchronizing signal HD and a vertical synchronizing signal VD are supplied to the CRT display section 25. The display enable signal DSPE is in an enabled state when it is at a high level;
This is determined sufficiently before the load timing signal LOAD.

The video memory section 23 outputs n-bit parallel video data VD1=VDn to the video conversion section 24.

The video conversion unit 24 converts the parallel video data VDI
~ Input VDn and convert it to serial data VIDEO,
Furthermore, blanking is performed and the signal is output to the CRT display unit 25 as a video signal.

Next, a configuration example and timing chart of a conventional video signal generation circuit in the above-mentioned CRT display device are shown in FIGS. 3 to 6, and its operation will be explained.

FIG. 3 is a configuration diagram showing the first conventional example, in which 31 is a synchronization circuit that manually inputs a display enable signal DSPE, a load timing signal LOAD, and a video clock CLK, and converts the display enable signal DSPE into serial conversion data (SD, (to be described later) is output. A shift register 32 inputs parallel video data VD1 to VDn, a load timing signal LOAD, and a video clock CLK, and outputs serial conversion data SD. 33 is an AND gate,
The serial conversion data SD and the output signal A of the synchronization circuit 31 are input, and the serial conversion data SD when the signal A is at a high level is output as the signal B. 34 is a flip-flop which inputs the output signal B of the AND gate 33 and the video clock CLK, and outputs serial data VIDEO in which the signal B is synchronized with the video clock CLK.
Output.

Next, the operation of the first conventional example will be explained based on the timing chart of FIG. 4, taking the case of n-4 as an example. Note that symbols 1 to 4 of the parallel video data vDl to VD4 in Figure 1 each indicate 4-bit parallel data, and symbols 1-1 to 4-1 of the serial conversion data SD indicate each of the parallel video data VDI to VD4. This indicates that 4-bit parallel data is serially converted, and the symbols for other serial data are the same.

The shift register 32 receives a load timing signal LOAD input with a width of one video clock every four video clocks.
When CLK is at high level, at the rising edge of video clock CLK,
Parallel video data VDI to VD4 inputted at the same timing as the load timing signal LOAD is loaded, serially converted, and serially converted data SD synchronized with the video clock CLK is output.

When the load timing signal LOAD is at a high level, the synchronization circuit 31 latches the display enable signal DSPE and outputs the signal A at the rising edge of the video clock CLK. That is, the display enable signal DSPE
is made to match the timing of the serial conversion data SD. In the example of Fig. 4, 1 Display enable signal D
SPE is for displaying parallel video data VD1-VD4 indicated by symbols 1 and 2.

The AND gate 33 performs a logical product of the output signal A of the synchronous circuit 1 and the serial conversion data SD, and when the signal A is at a low level, outputs a signal B at a non-display level, that is, a low level, thereby blanking the line. I do. That is, symbol 1-1~
Only serial conversion data indicated by symbol 2-4 is output.

The flip-flop 34 outputs the output signal A from the synchronization circuit 31 due to the phase difference between the output signal A and the serial conversion data SD.
When the pulse width of the output signal of the ND gate 33 becomes less than one video clock width, the former signal B is corrected to one video clock width and output as serial data VIDEO.

The higher the frequency of the video clock CLK, the more necessary it becomes.

FIG. 5 is a block diagram showing a second conventional example, in which 41 is a shift register and 42 is an AND gate circuit consisting of n AND gates.

The n-bit parallel data of the parallel video data VDI to VDn is inputted to an AND gate circuit 42, each inputted to one input terminal of the AND gate, and the display enable signal D inputted to the other input terminal.
A logical product with SPE is performed to perform blanking, and the result is manually input to the shift register 41. The shift register 41 is
It inputs the output signal C1-C port of the D gate circuit 42, the load timing signal LOAD, and the video clock CLK, and outputs the serial data VIDEO.

Next, we will explain the operation of the second conventional example using the case of n-4 as an example.
The explanation will be based on the timing chart shown in the figure. Note that symbols 1 to 4 of parallel video data VDI to VD4 in Figure 1 each indicate 4-bit parallel data, and symbols 1-1 to 2-4 of serial data VIDEO indicate parallel data indicated by symbols 1 and 2. Video data VDI~VD
4 is serially converted in order.

Parallel video data VDI-VD4 indicated by symbols 1 to 4 are manually input to the AND gate circuit 42 in order.
The display enable signal DSPE is the parallel video data VDI to VD4 indicated by the symbol 1 and the symbol 2.
can be displayed, parallel video data VDI-VD4 indicated by symbols 1 and 2 are output as output signals Ct to C4 of the AND gate circuit 42, and blanking is performed.

The shift register 41 transfers the parallel data of the output signals 01 to C4 of the AND gate circuit 42 to the video clock C when the load timing signal LOAD, which is input with a width of one video clock every four video clocks, is at a high level.
Load at the rising edge of LK, perform serial conversion, and output serial data VIDE0.

(Problem to be Solved by the Invention) However, in the first conventional example, it is necessary to synchronize the display enable signal DSPE with the serial conversion data SD by the synchronization circuit 31 in units of one video clock cycle, When increasing the frequency and speed, it becomes difficult to achieve synchronization due to signal delays caused by elements in the circuit and signal delays caused by wiring.

Also.

In the second conventional example, there is no need for synchronization control in units of one video clock cycle as in the first conventional example.

n AND gates are required to logically AND the parallel video data VD1 to VDn and the display enable signal DSPE, and in addition, in a color CRT display device, parallel video data VD1 for three colors of red, green, and blue are required.
~VDn is required, so 3×n AND gates are required. As n becomes larger, the speed can be increased, but on the contrary, the number of parts increases. Also, there is an A in the front stage of the shift register.
There is a problem in that data delay occurs due to the inclusion of the ND gate.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a video signal generation circuit for a CRT display device, which can eliminate retrace lines without increasing the number of parts and without causing data delay, thereby increasing the speed. It's about doing.

(Means for Solving the Problems) In order to achieve the above object, the present invention converts input parallel video data into serial video data in response to a load timing signal and outputs the serial video data. A video signal generation circuit for a CRT display device is composed of a parallel-to-serial conversion circuit that outputs serial video data at a non-display level when the data is not displayed, and a circuit that makes the load timing signal valid using a display enable signal.

(Operation) According to the present invention, by enabling the load timing signal with the display enable signal.

Parallel video data to be displayed is loaded into the parallel-to-serial conversion circuit, and the parallel-to-serial conversion circuit converts the parallel video data into serial and video data and outputs the same, and when the parallel video data is not input to the parallel-to-serial conversion circuit. Serial data at non-display level is output and blanking is performed.

(Embodiment) The first is a configuration diagram showing an embodiment of the video signal generation circuit of the CRT display device of the present invention, in which 11 is a shift register, 12
is an AND gate.

Shift register 11 stores parallel video data VD1 to VD
D4, the output signal of the AND gate 12, and the video clock CLK are input, and serial data VIDEO is output. That is, the shift register 11 constitutes a parallel-serial conversion circuit that converts parallel video data into serial and video data. The shift register 11 also has a serial data input terminal Sl, which is grounded and receives a low level signal. That is, the video data at the non-display level is manually created. The AND gate 12 inputs the load timing signal LOAD and the display enable signal DSPE, and outputs a signal obtained by logically multiplying the load timing signal LOAD and the display enable signal DSPE. That is, the AND gate 12 receives the load timing signal L.
A circuit is configured to enable OAD using a display enable signal DSPE.

Next, the operation of one embodiment of the present invention will be explained based on the timing chart of FIG. 7, taking the case of n-4 as an example. Sho 1
In the figure, symbols 1 to 4 of parallel video data VDI to VD4 each indicate 4-bit parallel data, and symbols 1-1 to 2-4 of serial data VIDEO indicate parallel video data indicated by symbols 1 and 2. data VDI
- Indicates that VD4 was serially converted. Further, the display enable signal DSPE enables parallel video data VDI to VD4 indicated by symbols 1 and 2 to be displayed.

1 video clock width is input every 4 video clocks and 6
01 timing 13 LOAD and display enable signal DSI) C are ANDed by AND gate 2 and output as a signal.

In other words, the parallel video data VD1~ which can be displayed in 5
Only the load timing signal LOAD for loading VD4 into the shift register 11 is output. In the shift register 11, at the rising edge of the video clock CLIC when the signal RI is at the no level, the 1-bit video data VDI to VD4 is loaded, serially converted, and outputted as serial data VIDEO. Also, shift register]
When the parallel video data VDl to VD4 are no longer input to the input terminal 1, serial manual data, that is, video data at a non-display level is outputted to perform blanking.

(Effects of the Invention) As described above, according to the present invention, input parallel video data is converted into serial video data in response to a load timing signal and outputted, and when the parallel video data is not input, Since the video signal generation circuit of the CRT display device is constructed from a parallel-to-serial conversion circuit that outputs serial video data at a non-display level and a circuit that makes the load timing signal H-effect using a display enable signal, the number of components increases by one. In addition, blanking lines can be eliminated without causing data delay, and speeding up can be achieved.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram showing an embodiment of the present invention, Figure 2 is a CR
FIG. 3 is a configuration diagram showing an example of a T display device. FIG. 3 is a configuration diagram showing a first conventional example. FIG. 4 is a timing chart of the first conventional example. FIG. 5 is a configuration diagram showing a second conventional example. , FIG. 6 is a timing chart of the second conventional example, and FIG. 7 is a timing chart of an embodiment of the present invention. 11...Shift register, 12...AND gate. 21...Video clock generation section, 22...Display control signal generation section, 23...Video memory section, 24...Video conversion section, 25...CRT display section 131...Synchronization circuit. 32...Shift register, 33...AND gate,
34...Flip-flop, 41...Shift register. Gate, 42...AND gate.

Claims (1)

[Scope of Claims] A parallel camera that receives a load timing signal, converts input parallel video data into serial video data, and outputs the serial video data, and outputs serial video data at a non-display level when the parallel video data is not input. C comprising a serial conversion circuit and a circuit for validating the load timing signal by a display enable signal.
Video signal generation circuit for RT display device.