JPH04310998A - Display controller - Google Patents

Abstract

PURPOSE:To provide the display controller which facilitates the generation of a non-display signal by latching no parallel display data in a parallel-serial conversion part in a non-display state, and outputting non-display data to the serial output of the parallel-serial conversion part unless a latch signal is supplied after data latched in the parallel-serial conversion part are all outputted. CONSTITUTION:Parallel display data are latched in the shift register of the parallel-serial conversion part 1 and the parallel display data latched in the shift register are converted into serial data in synchronism with a CLOCK signal and then outputted. When an LOAD signal outputted at intervals of specific pulses of the CLOCK signal is not outputted, the parallel display data are inhibited from being inputted to the shift register and non-display data are shifted in the parallel-serial conversion part 1 in synchronism with the CLOCK signal. The latch signal is not outputted when a BLANK signal is outputted (at non-display time).

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device that converts parallel display data into serial data and outputs the serial data.

0002

2. Description of the Related Art FIG. 5 is a diagram showing a conventional example of a display control device that converts parallel display data into serial data and displays it. Here, the case where the display device 55 is a raster scan type CRT display is shown. In the case of the raster scan method, the scanning beam scans from left to right and displays one pixel at a time, and when it reaches the right edge of the screen, it returns to the left edge of the screen without displaying anything, and repeats this process, starting from the top one line at a time. Displayed below. FIG. 6 schematically shows this situation. In FIG. 6, solid lines indicate beam scanning while displaying, and dotted lines indicate beam scanning without display.

FIG. 9 is a timing chart of the synchronization signal output from the timing generator section 52 of this conventional display control device. The timing of beam scanning in the horizontal direction in Fig. 6 is determined by the horizontal synchronization signal (HSYNC).
When the scanning position of the beam reaches the bottom of the screen, it scans back to the top of the screen without displaying,
This is repeated. The scanning timing in the vertical direction is determined based on the vertical synchronization signal (VSYNC). Furthermore, in the non-display state indicated by the dotted line in FIG. 6, the BLANK signal is active.

FIGS. 7 and 8 each show a parallel/serial converter 51 (FIG. 8) that latches parallel display data of 8 pixels and converts it into a serial signal, and a corresponding timing generator 52 circuit ( Figure 7) shows the configuration. Further, FIG. 10 shows the parallel/serial converter 51
2 is a timing chart for explaining the operation of FIG.

The timing generator section 52 is shown in FIG.
As is clear from the figure, a pulse is generated once every eight clocks based on the reference clock (CLOCK) of the parallel-to-serial converter 51, and is output to the parallel-to-serial converter 51 as a LOAD signal. Three flip-flops 71 to 73 in FIG. 7 constitute a 3-bit binary counter. Synchronous signal generation circuit 7
4 generates a synchronization signal required by the display device 55.

In the parallel/serial converter 51 shown in FIG. 8, when the serial output 81 is at a low level, the display device 5
It is assumed that the data displayed in 5 is not displayed, and that it is not displayed when the parallel input data 82 is at a low level. Now, the timing generator section 52
When the LOAD signal becomes high level, the CLOCK
The signal causes each bit of parallel input 82 to be latched into a respective flip-flop. At this time, B.L.A.
If the NK signal is at a low level, the contents of D0 latched in the flip-flop 90 are output to the serial output 81. Also, when the LOAD signal becomes low level,
Each bit data latched in flip-flops 83 to 90 is shifted by the CLOCK signal, and the BLAN
If the K signal is low level, D1 is output to the serial output 81.
, D2, D3, . . . each bit is output in this order. however,
When the BLANK signal becomes high level, the LOAD signal,
Regardless of the CLOCK signal, the serial output 81 becomes low level, and the display state of the display device 55 becomes a non-display state.

[0007]

In recent years, as display devices have become higher in resolution, the CLOCK signal has become a high-frequency clock signal. The BLANK signal mentioned above is
Since this signal must be synchronized with this CLOCK signal, there is a problem in that when the CLOCK signal becomes a high frequency, it is difficult to synchronize the BLANK signal with this clock signal.

The present invention has been made in view of the above-mentioned conventional example, and is designed to prevent parallel display data from being latched to the parallel-to-serial converter when in a non-display state, and to prevent the data latched by the parallel-to-serial converter from being latched. It is an object of the present invention to provide a display control device that facilitates generation of a non-display signal by outputting non-display data to the serial output if no latch signal is supplied after all outputs.

[0009]

[Means for Solving the Problems] In order to achieve the above object, a display control device of the present invention has the following configuration. That is, the display control device converts display data into serial data and displays the data, and includes a latch unit that latches parallel display data, and converts the parallel display data latched by the latch unit into serial data in synchronization with a clock signal. parallel-to-serial conversion means for converting and outputting the signal; latch signal output means for outputting a latch signal to the latch means every predetermined pulse of the clock signal; and latch signal output means for outputting the latch signal to the latch means when the latch signal is not output. means for prohibiting input of display data and shifting non-display data into the parallel-to-serial conversion means in synchronization with the clock signal; and prohibition means for prohibiting output of the latch signal when non-displaying is performed. .

0010

In the above structure, parallel display data is latched by the latch means, and in synchronization with a clock signal, the parallel display data latched by the latch means is converted into serial data and output. When the latch signal that is output every predetermined pulse of the clock signal is not output, input of parallel display data to the latch means is prohibited, and non-display data is shifted into the parallel-serial conversion means in synchronization with the clock signal. do. This latch signal is also prohibited from being output when not displayed.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a schematic configuration of the display control circuit of this embodiment. In the figure, reference numeral 1 denotes a parallel-to-serial conversion section, which inputs parallel display data from the video RAM section 4 and converts the clock signal ( It outputs a serial signal 32 synchronized with CLOCK). 2 is a timing generator unit that generates timing signals for each part; 3 is a video signal generator unit that generates a signal for the display device 5 from the serial output of the parallel-to-serial converter 1 and the synchronization signal of the timing generator unit 2; 4; 5 is a video RAM unit storing display data, and 5 is a display device.

Similar to the conventional example described above, the display data 31 includes a parallel/serial converter 1 for inputting 8-bit data composed of 8 pixels and converting it into a known signal, and a timing generator 2 corresponding thereto. The circuit configurations are shown in FIGS. 2 and 3, respectively. Further, FIG. 4 is a timing chart for explaining the operation of the parallel-to-serial converter 1.

As shown in FIG. 2, the timing generator section 2 uses the clock signal (CLOCK) as the reference for the parallel-to-serial converter section 1, as in the conventional example.
The flip-flops 21 to 23 generate a pulse once every eight clocks, and output it to the parallel-to-serial converter 1 as a LOAD signal. This LOAD signal is not output when the BLANK signal from the synchronization signal generation circuit 24 is at a high level, that is, when the display is in a non-display state. The state in which the output of the LOAD signal is inhibited by the BLANK signal is shown by the dotted line in FIG. The portion of the LOAD signal indicated by the broken line is the portion that is output in the conventional example. Note that, similarly to the conventional example described above, in FIG. 3, when the serial output 32 is at a low level, no display data is displayed on the display device 5, and the parallel input data 3
It is assumed that the display is hidden when 1 is at low level.

In FIG. 3, when the LOAD signal becomes low level, the parallel display data 31 latched in the flip-flops 33 to 40 is shifted, and the contents of D0 latched in the flip-flop 40 are output to the serial output 32. be done. At this time, a low level is latched in the flip-flop 33 that latches the value of D7, and each bit is outputted to the serial output 32 in the order of D1, D2, D3, . . . D7. After that, if the LOAD signal does not go high, all outputs shifted thereafter will go low.

On the other hand, when the BLANK signal is at a low level, the LOAD signal from the timing generator section 2 is output once for every eight CLOCK signals, so the parallel-to-serial converter section 1 The display data continues to be sent to the video signal generator 3. Also, B.L.A.
When the NK signal is at a high level, the LOAD signal from the timing generator section 2 remains at a low level, so the parallel/serial converter section 1 synchronizes the data (8 bits) latched by the last LOAD signal with the CLOCK signal. After outputting, it continues to output low level until the next LOAD signal comes. Therefore, the display device 5 is in a non-display state while the individual output 32 is at a low level.

As explained above, when the parallel/serial converter 1 latches the parallel data of 8 pixels and converts it into serial data, the BLANK signal is generated at the CLOC.
It is only necessary to synchronize with 8 pulses of the K signal at one timing, and if 16 pixels can be latched, CLOCK
Since it is only necessary to synchronize with 16 pulses of the signal at one timing, there is more margin in the output timing of the BLANK signal.

In the above explanation, in order to simplify the explanation,
The explanation has been made for the case where the display device 5 has a monochrome level, that is, there are only two states for a certain display pixel: display state or non-display state, but if the display device 5 is a color display, the parallel-serial converter 1 For this purpose, a plurality of shift registers as shown in FIG. 3 may be prepared. For example, 8
In the case of color, one display pixel can be represented by one bit of RGB, so three shift registers are required. Furthermore, in the case of a display device in which each 8 bits of RGB represent one display pixel, 24 shift registers are required.

As explained above, according to this embodiment, B
The LANK signal can be used by masking the LOAD signal obtained by dividing the CLOCK signal, so the BLANK signal can be used as a CLOCK signal.
This has the effect that it is easier to generate a non-display signal than in the conventional example, which requires tuning to the K signal.

[0020]

As explained above, according to the present invention, parallel display data is not latched in the shift register for parallel-to-serial conversion when in the non-display state, and the parallel display data is not latched in the parallel-to-serial conversion section. If the latch signal is not supplied after outputting all the data,
By outputting the non-display data to the serial output, there is an effect that the non-display data can be easily generated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a display control circuit according to an embodiment.

FIG. 2 is a block diagram showing the configuration of a timing generator section of this embodiment.

FIG. 3 is a circuit diagram showing a circuit configuration of a parallel-to-serial conversion section of this embodiment.

FIG. 4 is an operation timing diagram of the parallel-to-serial converter of this embodiment.

FIG. 5 is a block diagram showing the configuration of a conventional display control circuit.

FIG. 6 is an explanatory diagram of beam scanning in a general raster scan type CRT.

FIG. 7 is a block diagram showing the configuration of a conventional timing generator section.

FIG. 8 is a circuit diagram showing a circuit configuration of a conventional parallel-to-serial converter.

FIG. 9 is a timing diagram of synchronization signals of the display device.

FIG. 10 is a timing diagram of the operation of a conventional parallel-to-serial converter.

[Explanation of symbols]

1 Parallel/serial converter 2 Timing generator section 3 Video signal generation section 4 Video RAM section 5 Display device 31 Display data 32 Serial output

Claims (1)

[Claims] 1. A display control device that converts display data into serial data and displays the data, the device comprising: latch means for latching parallel display data; and a latch means for latching parallel display data latched by the latch means in synchronization with a clock signal. parallel-to-serial conversion means for converting into serial data and outputting it; latch signal output means for outputting a latch signal to the latch means every predetermined pulse of the clock signal;
means for prohibiting input of the display data to the latch means when the latch signal is not output, and shifting non-display data into the parallel-to-serial conversion means in synchronization with the clock signal; , and prohibition means for prohibiting output of the latch signal.