JPH04298786A - Display controller - Google Patents

Abstract

PURPOSE:To provide a display controller which can easily change the correspondence relation of the display data and the display state of a display device where the display data is inputted and displayed. CONSTITUTION:The display data 30 is reversed in accordance with a reverse mode signal 41, and the display data 30 which is reversed in such a way or not reversed is converted into an output video signal 42 to the display device 5. At such a time, a BLANK level signal 40 designating a signal level which is not displayed on the device 5 is inputted, and the level of the output video signal 42 in the non-display state of the device 5 is decided in accordance with the signal level.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for outputting image data to a display device for display.

0002

[Prior art] Converting display data to serial data,
An example of the configuration of a conventional display control device that displays this is shown in FIG. In FIG. 6, the display device 65 is a raster scan type CRT display. In the case of a raster scan type CRT, the beam scans from left to right and displays one pixel at a time, and when the beam scanning position reaches the right end, it moves to the left end without displaying image data on the screen. This is repeated for each scanning line, and each line is displayed from top to bottom. FIG. 7 is a diagram schematically showing the state of this beam scanning. In Figure 7,
A solid line indicates beam scanning while displaying, and a dotted line indicates beam scanning without displaying.

FIG. 10 shows the timing generator section 6.
2 is a timing chart of a synchronizing signal for display outputted from 2. The horizontal scanning timing in FIG. 7 is based on the horizontal synchronization signal HSYNC, and when the beam scanning position reaches the bottom of the screen, the beam position is returned to the top of the screen without displaying. Repeat for each display screen. This vertical scanning timing is based on the vertical synchronization signal VSYNC. Also, Figure 7
When the display indicated by the dotted line shown in is not displayed,
The BLANK signal is active.

FIGS. 8 and 9 each show the parallel/serial converter 6 when the display data that can be latched is 8 pixels.
1 (FIG. 9) and the corresponding timing generator section 62 (FIG. 8). Also, Figure 1
1 is a timing chart for explaining the operation of the parallel-to-serial converter 61 shown in FIG.

The timing generator section 62 is shown in FIG.
As shown in FIG. 2, based on the clock signal from the clock generation circuit 80 that serves as a reference for the parallel-to-serial converter 61, one pulse signal is output every eight clocks, and the LOAD
It is output to the parallel/serial converter 61 as a signal. Three flip-flops 82 to 84 in FIG. 8 constitute a 3-bit binary counter, and a synchronization signal generating circuit 81 outputs a synchronization signal required by the display device 65.

In the parallel-to-serial converter shown in FIG. 9, it is assumed that when the serial output 91 is at a low level, there is no display, and the parallel input data 92 is all at a low level and is not displayed. When the LOAD signal from the timing generator section 62 becomes high level, C
The parallel input (8 bits) is latched into each flip-flop by the LOCK signal, and if the BLANK signal is at low level, the contents of D0 are output to the serial output. Then, when the LOAD signal becomes low level,
The latched parallel data is shifted by the CLOCK signal, and if the BLANK signal is at a low level, each 1-bit data is output to the serial output 91 in the order of D1, D2, D3, . . . . However, when the BLANK signal becomes high level, the serial output 91 becomes low level regardless of the states of the LOAD signal and the CLOCK signal, resulting in a non-display state.

[0007]

[Problems to be Solved by the Invention] Currently, there are diversifying requirements for display control devices, such as the need to be able to connect to multiple display devices. It is necessary to For example, the correspondence between the stored display data information and the display state, that is, in the case of a monochrome display device, how the display data "0" and "1" correspond to the display state and non-display state, or the display device The correspondence between the level of the video signal and the display state, that is, the low level and high level of the video signal,
There is a problem in how to correspond to the display state and non-display state. If the display control device can handle any of these cases, there will be no need to change its specifications or change it in accordance with the connected display device, and it will be easy to use it for other display devices. However, the conventional example described above has a drawback that the display data "0" corresponds to the non-display state, or when the level of the video signal output to the display device is low level, it permanently corresponds to the non-display state.

The present invention has been made in view of the above conventional example, and an object of the present invention is to provide a display control device that can easily change the correspondence between display data and the display state of a display device that inputs and displays the display data. shall be.

[0009]

[Means for Solving the Problems] In order to achieve the above object, a display control device of the present invention has the following configuration. That is, the display control device outputs image data to a display device for display, and includes an inverting means for inverting the image data in response to an inversion instruction signal, and outputting the image data that has passed through the inverting device to the display device. converting means for converting into a video signal; and signal level determining means for determining the signal level of the output video signal in a non-display state of the display device in response to an instruction signal that indicates a signal level that is not displayed on the display device. Equipped with

0010

[Operation] With the above structure, image data can be inverted in response to the inversion instruction signal, and the thus inverted or non-inverted image data can be converted into an output video signal to a display device. During this conversion, an instruction signal indicating a signal level that is not displayed on the display device is input, and the signal level of the output video signal in the non-display state of the display device is determined in accordance with the signal level.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a schematic configuration of the display control circuit of this embodiment. In FIG.
is input in parallel, converted into a serial signal, and output to the video signal generator 3. The parallel-to-serial converter 1 receives B output from a CPU (not shown), for example.
A LANK level signal 40 and a reverse mode signal 41 are input. This BLANK level signal 40 is
It defines the signal level of the video signal 42 when not displayed on the display device 5, and the reverse mode signal 41
is a signal for instructing whether to invert the display data 30 from the video RAM 4. 2 is a timing generator unit that generates timing signals for each part; 3 is a timing generator unit that inputs the serial output of the parallel-to-serial converter unit 1 and a synchronization signal from the timing generator unit 2, and generates a video signal 42 to be output to the display device 5; 4 is a video RAM section storing display data 30 in image data format; 5 is a display device such as a CRT.

Similar to the conventional example described above, FIG. 2 shows the circuit configurations of the parallel/serial converter 1 and the corresponding timing generator 2 when the display data 30 to be latched is 8 pixels (8 bits). and shown in Figure 3. Further, FIG. 4 is a timing chart for explaining the operation of the parallel-to-serial converter 1.

In FIG. 2, the timing generator section 2 operates once every eight clocks based on the clock signal that is the reference for the parallel-to-serial converter section 1 and is output from the clock generating circuit 21, as in the conventional example. pulse signal (L
OAD signal) and outputs the parallel signal as the LOAD signal.
It is output to the serial converter 1. This LOAD signal is not output when the BLANK signal output from the synchronization signal generation circuit 22 is at a high level, that is, when the display is in a non-display state.

The broken line portion of the LOAD signal in FIG. 4 shows the state in which the output of the LOAD signal is prohibited by the BLANK signal, and is the portion that was output in the conventional example shown in FIG. First, the same condition as in the conventional example described above, that is, the case where the video signal 42 is not displayed when it is at a low level and the display data 30 is not displayed when it is at a low level will be described.

In this case, in FIG. 3, the BLANK level signal 40 is set to low level, and the reverse mode signal 41 is set to low level. Here, when the LOAD signal becomes high level, the display data 30 is transferred as it is to each flip-flop 32 to 32 by the CLOCK signal.
39 and the serial output 31 is first D0.
The contents of are output. When the LOAD signal goes low in this state, the parallel data latched by the CLOCK signal is shifted by the flip-flops 32-39. Then, the BLANK level signal 40, that is, the low level, is latched in the flip-flop 32 that latches the value of D7. In this way, D1, D2, D3,..., are output to the serial output 31 in synchronization with the CLOCK signal.
The serial outputs 31 are output in the order of D7, and unless the LOAD signal becomes high level thereafter, all subsequent serial outputs 31 remain at low level.

As mentioned above, when the BLANK signal is at a low level, the L from the timing generator section 2
Since the OAD signal is output as a pulse signal once every eight clocks of the CLOCK signal, the parallel-to-serial converter 1 continues to output the display data 30 to the video signal generator 3 as is. Therefore, in this case, if the value of the display data 30 is "0", the level of the video signal 42 becomes low level and the display device 5 remains in the non-display state, and even if the value of the display data 30 is "1" If the screen is displayed, it will be displayed.

Furthermore, when the BLANK signal is at a high level, the LOAD signal from the timing generator section 2 remains at a low level, so the parallel/serial converter section 1 converts the data latched by the last LOAD signal into CLOC.
After outputting in synchronization with the K signal, the low level corresponding to the BLANK level signal 40 continues to be output until the next LOAD signal arrives, so the display device 5 maintains the non-display state.

Next, consider a case where the correspondence between the video signal 42 and the display state is the same, but the display data 30 and the display state are different, that is, the case where the display is not displayed when the display data 30 is "1".

In this case, in the parallel-to-serial converter 1 of FIG. 3, the reverse mode signal 41 is set to a high level while the BLANK level signal 40 remains at a low level. As a result, the display data 30 from the video RAM 4 is inverted and latched into the flip-flops 32 to 39, so that when the BLANK signal is at a low level, it is "1".
"The video signal 42 corresponding to the display data 30 becomes low level and becomes non-display. Also, when the BLANK signal is high level, the low level signal specified by this BLANK level continues to be output as video output, so the display The device 5 will remain in the non-display state.

Further, consider the case where the display is not displayed when the video signal 42 is at a high level, and the display is not displayed when the display data 30 is "1".

In this case, in FIG. 3, the BLANK level signal 40 is at a high level, and the reverse mode signal 4
When level 1 is set to low level, video RAM 4
The display data 30 is directly transferred to the flip-flop 32.
~39 is latched. As a result, when the BLANK signal is at low level, the video signal 42 corresponding to display data "1" becomes high level and becomes non-display. Also, BL
When the ANK signal is at high level, the high level signal specified by the BLANK level signal 40 continues to be output, so that the display device 5 maintains the non-display state.

[0023] The correspondence relationship between the video signal and the display state, the correspondence relationship between the display data and the display state, and the BL
FIG. 5 shows the relationship between the ANK signal level and the reverse mode signal level. In addition, in the figure, “low”
indicates that the signal is low level, and "high" indicates that the signal is high level.

[0024] In order to simplify the explanation, the above-mentioned embodiment has been described assuming that the display device 5 is monochrome, that is, there are only two states for a certain display pixel: a display state or a non-display state. The invention is not limited to this,
For example, if the display device 5 is a color display, a plurality of shift registers shown in FIG. 3 may be provided in the parallel/serial converter 1, for example, for each of RGB. For example, in the case of color image data of eight colors, one pixel can be represented by one bit of each of RGB, so three shift registers are required. Furthermore, in the case of a display device in which each 8 bits of RGB represent one display pixel, 24
shift registers are required.

The present invention may be applied to a system made up of a plurality of devices, or to a device made up of one device. It goes without saying that the present invention can also be applied to cases where the present invention is achieved by supplying a program to a system or device.

As explained above, according to this embodiment, a signal specifying the inversion of display data and a signal specifying the level in the non-display state are input to the parallel-to-serial converter 1. Various settings can be made for the correspondence between the display data information and the display state of the display device, and the correspondence between the level of the video signal to the display device and the display state of the display device.

[0027]

As described above, according to the present invention, the correspondence between display data and the display state of the display device that inputs and displays the display data can be easily changed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a display control circuit according to an embodiment.

FIG. 2 is a circuit diagram of a timing generator section of this embodiment.

FIG. 3 is a circuit diagram of a parallel-to-serial conversion section of this embodiment.

FIG. 4 is a timing diagram of the operation of the display control circuit of this embodiment.

FIG. 5 is a diagram for explaining the relationship between the level of the BLANK signal and the level of the reverse mode signal of the display control circuit of the present embodiment.

FIG. 6 is a block diagram showing a schematic configuration of a conventional display control circuit.

FIG. 7 is a diagram for explaining scanning of a general raster scan type CRT.

FIG. 8 is a circuit diagram of a conventional timing generator section.

FIG. 9 is a circuit diagram of a conventional parallel-to-serial converter.

FIG. 10 is a timing diagram of a synchronization signal output from a conventional timing generator section.

FIG. 11 is an operation timing diagram of a conventional display control circuit.

[Explanation of symbols]

1 Parallel/serial converter 2 Timing generator section 3 Video signal generation section 4 Video RAM section 5 Display device 21 Clock generation circuit 22 Synchronous signal generation circuit 32-39 Flip-flop

Claims (2)

[Claims] 1. A display control device that outputs and displays image data on a display device, the device comprising: inverting means for inverting the image data in response to an inversion instruction signal; converting means for converting the output video signal into an output video signal; and a signal level determination for determining the signal level of the output video signal in a non-display state of the display device in response to an instruction signal that indicates a signal level that is not displayed on the display device. A display control device comprising: means. 2. The converting means includes a shift register for converting the image data from parallel to serial signals, and shifts the signal level of the instruction signal to the shift register when a BLANK signal to the display device is enabled. 2. The display control device according to claim 1, wherein the display control device generates a video signal by inputting a video signal.