JPH0122938B2 - - Google Patents

Info

Publication number
JPH0122938B2
JPH0122938B2 JP56027491A JP2749181A JPH0122938B2 JP H0122938 B2 JPH0122938 B2 JP H0122938B2 JP 56027491 A JP56027491 A JP 56027491A JP 2749181 A JP2749181 A JP 2749181A JP H0122938 B2 JPH0122938 B2 JP H0122938B2
Authority
JP
Japan
Prior art keywords
channel
section
input
command
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56027491A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57141737A (en
Inventor
Masahito Hihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2749181A priority Critical patent/JPS57141737A/ja
Publication of JPS57141737A publication Critical patent/JPS57141737A/ja
Publication of JPH0122938B2 publication Critical patent/JPH0122938B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP2749181A 1981-02-26 1981-02-26 Channel controlling system Granted JPS57141737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2749181A JPS57141737A (en) 1981-02-26 1981-02-26 Channel controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2749181A JPS57141737A (en) 1981-02-26 1981-02-26 Channel controlling system

Publications (2)

Publication Number Publication Date
JPS57141737A JPS57141737A (en) 1982-09-02
JPH0122938B2 true JPH0122938B2 (enrdf_load_html_response) 1989-04-28

Family

ID=12222597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2749181A Granted JPS57141737A (en) 1981-02-26 1981-02-26 Channel controlling system

Country Status (1)

Country Link
JP (1) JPS57141737A (enrdf_load_html_response)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943771B2 (ja) * 1977-04-22 1984-10-24 日本電気株式会社 入出力制御方式

Also Published As

Publication number Publication date
JPS57141737A (en) 1982-09-02

Similar Documents

Publication Publication Date Title
EP0464615B1 (en) Microcomputer equipped with DMA controller
US4974143A (en) Information processing apparatus wherein address path is used for continuous data transfer
JPH0332818B2 (enrdf_load_html_response)
EP0220990A2 (en) Buffer storage control system
JPS5851327A (ja) 入出力制御システム
JPH0221619B2 (enrdf_load_html_response)
JPH0122938B2 (enrdf_load_html_response)
JP2533886B2 (ja) デ―タ転送方式
JPS6048563A (ja) チャネル制御方式
JPS6240736B2 (enrdf_load_html_response)
JPH0425581B2 (enrdf_load_html_response)
JP2594611B2 (ja) Ｄｍａ転送制御装置
JPH10133997A (ja) Ｄｍａ制御装置
JP2552025B2 (ja) データ転送方式
JPS59144955A (ja) 情報処理装置
JPH0424733B2 (enrdf_load_html_response)
JPS63137350A (ja) チヤネルプログラム実行制御方式
JPS63132362A (ja) コマンド動作制御方式
JPS6174045A (ja) マルチプロセツサシステムにおけるチヤネル制御方式
JPH05233482A (ja) データ転送システム
JPH0347536B2 (enrdf_load_html_response)
JPH071494B2 (ja) チャネルコマンド語チェイン装置
JPS60103473A (ja) デ−タ転送制御方式
JPH1027153A (ja) バス転送装置
JPS6027056B2 (ja) チエイニング・チエック方式