JPH0122936B2 - - Google Patents

Info

Publication number
JPH0122936B2
JPH0122936B2 JP57143924A JP14392482A JPH0122936B2 JP H0122936 B2 JPH0122936 B2 JP H0122936B2 JP 57143924 A JP57143924 A JP 57143924A JP 14392482 A JP14392482 A JP 14392482A JP H0122936 B2 JPH0122936 B2 JP H0122936B2
Authority
JP
Japan
Prior art keywords
signal
cpu
flag
register
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57143924A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5933568A (ja
Inventor
Toshiaki Suzuki
Takashi Sakao
Katsuhiko Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57143924A priority Critical patent/JPS5933568A/ja
Publication of JPS5933568A publication Critical patent/JPS5933568A/ja
Publication of JPH0122936B2 publication Critical patent/JPH0122936B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP57143924A 1982-08-18 1982-08-18 マイクロコンピユ−タ Granted JPS5933568A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57143924A JPS5933568A (ja) 1982-08-18 1982-08-18 マイクロコンピユ−タ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57143924A JPS5933568A (ja) 1982-08-18 1982-08-18 マイクロコンピユ−タ

Publications (2)

Publication Number Publication Date
JPS5933568A JPS5933568A (ja) 1984-02-23
JPH0122936B2 true JPH0122936B2 (enExample) 1989-04-28

Family

ID=15350259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57143924A Granted JPS5933568A (ja) 1982-08-18 1982-08-18 マイクロコンピユ−タ

Country Status (1)

Country Link
JP (1) JPS5933568A (enExample)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56157541A (en) * 1980-05-06 1981-12-04 Kinki Keisokki Kk Pseudo and multi central processor
JPS57109635A (en) * 1980-11-13 1982-07-08 Goodrich Co B F Preparation of molding composition

Also Published As

Publication number Publication date
JPS5933568A (ja) 1984-02-23

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