JPH01229340A - System for detecting execution address - Google Patents

System for detecting execution address

Info

Publication number
JPH01229340A
JPH01229340A JP63056747A JP5674788A JPH01229340A JP H01229340 A JPH01229340 A JP H01229340A JP 63056747 A JP63056747 A JP 63056747A JP 5674788 A JP5674788 A JP 5674788A JP H01229340 A JPH01229340 A JP H01229340A
Authority
JP
Japan
Prior art keywords
comparison
address
execution
signal
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63056747A
Other languages
Japanese (ja)
Inventor
Norihiko Sumiya
炭屋　紀彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Solution Innovators Ltd
Original Assignee
NEC Solution Innovators Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Solution Innovators Ltd filed Critical NEC Solution Innovators Ltd
Priority to JP63056747A priority Critical patent/JPH01229340A/en
Publication of JPH01229340A publication Critical patent/JPH01229340A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To analyze respective problems related to the execution order of programs by designating the appearance order of plural execution addresses so as to detect them. CONSTITUTION:A comparison address memory 1 holds comparison addresses which can be compared with the execution addresses in a comparison order. A comparison address memory pointer 2 designates one of the comparison addresses which are read from the memory 1. On the other hand, a comparison coincident detection part 3 compares an execution address signal (a) which changes in the execution of the program and a comparison address signal read from the memory 1. When they coincide, a coincident signal (b) is outputted. As a result, a pointer 2 receives the signal (b), adds by one in a coincident number update circuit and shifts the instruction of the comparison address which is read from the memory 1 to one address next. Said processings are repeated. On the other hand, a coincident time number counting part 4 counts the number of coincident times when the signals (b) are outputted, and a designation condition setting part 5 sets and holds the number of the designated times of the signals (b) as a designated condition. A designated condition detection part 6 outputs a condition coincident signal (c) when the number of the times of the counting part 4 and the number of times (i) coincide, and transmits the signal (c) to a debugging information control part.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は実行アドレス検出方式に関し、特に情報処理装
置におけるプログラムの実行アドレス検出方式に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an execution address detection method, and particularly to an execution address detection method for a program in an information processing apparatus.

〔従来の技術〕[Conventional technology]

従来の実行アドレス検出方式は、一つの比較アドレスを
設定し、これと実行アドレスとを比較して一致したとき
の比較一致信号を条件一致信号として出力している。In the conventional execution address detection method, one comparison address is set, and the comparison address is compared with the execution address, and when they match, a comparison match signal is output as a condition match signal.

また、従来の実行アドレス検出方式には、Ｎヒツトの実
行アドレスの下位Ｍ　（ＭＡＮ＞ビット分使用せず、上
位Ｎ−Ｍビットだけを比較範囲として、比較アドレスの
Ｎ−Ｍビットに比較して一致したときの比較一致信号を
東件一致信号として出力する方式がある。In addition, in the conventional execution address detection method, the lower M (MAN> bits) of N execution addresses are not used, and only the upper N-M bits are used as a comparison range, and compared with the N-M bits of the comparison address. There is a method of outputting a comparison match signal when a match occurs as a Tokyo case match signal.

この場合には、実行アドレスが、近接する２Ｍ個のアド
レス範囲に入るこ”とにより、条ｎ−一致信号を出力す
ることになる。In this case, when the execution address falls within the range of 2M adjacent addresses, the article n-match signal is output.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の実行アドレス検出方式は、一つの比較ア
ドレスもしくは比較アドレス範囲を一致条件としており
、幾つかの実行アドレスの出現順序を一致条件として、
−度に指定することができないので、プログラムの実行
順序に関係する諸間厘を解析することが困難であるとい
う欠点がある。The conventional execution address detection method described above uses one comparison address or comparison address range as a matching condition, and uses the order of appearance of several execution addresses as a matching condition.
- Since it is not possible to specify the order of execution of a program, it is difficult to analyze various errors related to the order of execution of a program.

本発明の目的は、複数個の実行アドレスの出現順序を指
定して検出することにより、プログラムの実行順序に関
係する諸問題を解析することができる実行アドレス検出
方式を提供することにある。An object of the present invention is to provide an execution address detection method that can analyze various problems related to the execution order of a program by specifying and detecting the order in which a plurality of execution addresses appear.

１課題を解決するための手段］ 本発明の実行アドレス検出方式は、記憶装置に記憶され
たプログラムの実行アドレスにある命令を順次取出して
実行する情報処理装置にあって、（Ａ）実行アドレスに
比較する複数個の比較アドレスを保持する比較アドレス
メモリ、 （Ｂ）前記比較アドレスメモリから読出す比較アドレス
を指示するとともに、比較一致信号により読出す比較ア
ドレスの指示を順次移動する比較アドレスメモリポイン
タ、 （Ｃ）プログラムの実行アドレスと前記比較アドレスメ
モリから読出された比較アドレスとを比較し、一致した
ときに前記比較一致信号を出力する比較一致検出部、 （Ｄ）前記比較一致信号が出力された一致回数を計数す
る一致回数計数部、 （Ｅ）前記比較一致信号の指定回数を含む指定条件を設
定して保持する指定条件設定部、（Ｆ）面記一致回数計
数部で計数している一致回数と前記指定条件設定部に保
持する指定回数との一致を含む前記指定条件設定部の指
定条件が満足されたときに、染件一致信号を出力する指
定条件検出部、 を備えて構成されている。1. Means for Solving the Problem] The execution address detection method of the present invention is provided in an information processing device that sequentially retrieves and executes instructions at the execution address of a program stored in a storage device. a comparison address memory that holds a plurality of comparison addresses to be compared; (B) a comparison address memory pointer that indicates a comparison address to be read from the comparison address memory and sequentially moves the instruction of the comparison address to be read by a comparison match signal; (C) a comparison match detection unit that compares the program execution address and the comparison address read from the comparison address memory and outputs the comparison match signal when they match; (D) the comparison match signal is outputted; A match counting section that counts the number of matches, (E) a specified condition setting section that sets and holds the specified conditions including the specified number of times of the comparison match signal, and (F) a match counted by the inscription match number counting section. a specified condition detection unit that outputs a dye match signal when specified conditions of the specified condition setting unit, including a match between the number of times and a specified number of times held in the specified condition setting unit, are satisfied; There is.

［実施例〕 次に本発明の実施例について図面を参照して説明する。[Example〕 Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の実行アドレス検出方式の一実施例を示
すブロック図である。FIG. 1 is a block diagram showing an embodiment of the execution address detection method of the present invention.

第１図において、記憶装置に記憶されたプログラムの実
行アドレスにある命令を順次取出して実行する情報処理
装置にあって、比較アドレスメモリ１は、１ワードが１
６ビツトの２５６ワードで構成され、実行アドレスに比
較することができる２５６個までの比較アドレスを比較
する順序に保持している。In FIG. 1, in an information processing device that sequentially retrieves and executes instructions at execution addresses of a program stored in a storage device, a comparison address memory 1 has a memory in which each word is one word.
It is composed of 256 words of 6 bits and holds up to 256 comparison addresses that can be compared with the execution address in the order of comparison.

また、比□較アドレスメモリポインタ２は、２５６個ま
での一つを指示できる８ビツトで構成され、比較アドレ
スメモリ１から読出す比較アドレスの一つを指示してい
る。The comparison address memory pointer 2 is composed of 8 bits that can point to one of up to 256 points, and points to one of the comparison addresses to be read from the comparison address memory 1.

一方、比較一致検出部３は、プログラムの実行により変
化している実行アドレス信号ａと、比較アドレスメモリ
から読出された比較アドレスの信号とを比較し、一致し
たときに比較一致信号すを出力する。On the other hand, the comparison match detection unit 3 compares the execution address signal a that is changing due to the execution of the program with the signal of the comparison address read from the comparison address memory, and outputs a comparison match signal S when they match. .

この結果、比較アドレスメモリポインタ２は、比較一致
信号すを受けて、アドレスメモリポインタ更新回路で１
を加算することにより、比較アドレスメモリ１から読出
す比較アドレスの指示を１アドレス次に移動する。As a result, in response to the comparison match signal, the comparison address memory pointer 2 is changed to 1 by the address memory pointer update circuit.
By adding , the instruction of the comparison address to be read from the comparison address memory 1 is moved one address to the next.

以上の動作は、繰返して行われる。The above operations are performed repeatedly.

一方、一致回数計数部４は、８ビツトで構成され、初期
値として０が設定されており、比較一致信号すを受ける
ごとに、一致回数更新回路で１を加算することにより、
比較一致信号すが出力された一致回数を計数している。On the other hand, the match count counting section 4 is made up of 8 bits, and is set to 0 as an initial value, and each time it receives a comparison match signal, the match count update circuit adds 1.
The number of times the comparison match signal is outputted is counted.

他方、指定条件設定部５は、８ビツトで構成され、比較
一致信号すの指定回数ｉを指定条件として設定して保持
している。On the other hand, the specified condition setting section 5 is composed of 8 bits, and sets and holds the specified number of times i of the comparison match signal as a specified condition.

そこで、指定条件検出部６は、一致回数計数部４で計数
している一致回数と指定条件設定部５に保持している指
定回数ｉとが一致したときに、条件一致信号Ｃを出力し
、この染件一致信号Ｃをデバッグ情報制御部へ送出する
。Therefore, the specified condition detecting section 6 outputs a condition matching signal C when the number of matches counted by the matching number counter 4 matches the specified number i held in the specified condition setting section 5, This stain matching signal C is sent to the debug information control section.

以上述べたように、本実施例の実行アドレス検出方式は
、複数個の実行アドレスの出現順序を指定して検出する
ことができるので、プログラムの実行順序に関係する諸
問題を解析するために有効である。As described above, the execution address detection method of this embodiment can specify and detect the order in which multiple execution addresses appear, so it is effective for analyzing various problems related to the program execution order. It is.

し発明の効果〕 以上説明したように、本発明の実行アドレス検出方式は
、複数個の実行アドレスの出現順序を指定して検出する
ことにより、プログラムの実行順序に関係する諸問題を
解析することができるという効果を有している。[Effects of the Invention] As explained above, the execution address detection method of the present invention can analyze various problems related to the execution order of a program by specifying and detecting the order in which a plurality of execution addresses appear. It has the effect of being able to.

このため、本発明の実行アドレス検出方式は、ソフトウ
ェアやファームウェアのデバッグ手段として、極めて有
効であるという効果を有している。Therefore, the execution address detection method of the present invention is extremely effective as a means for debugging software and firmware.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実行アドレス検出方式の一実施例を示
すブロック図である。 １・・・・・比較アドレスメモリ、２・・・・・比較ア
ドレスメモリポインタ、３・・・・・・比較一致検出部
、４・・・・・一致回数計数部、５・・・・・・指定条
件設定部、６・・・・・・指定条件検出部、ａ・・・・
・・実行アドレス信号、ｂ・・・・・・比較一致信号、
Ｃ・・・・・・条件一致信号。FIG. 1 is a block diagram showing an embodiment of the execution address detection method of the present invention. 1... Comparison address memory, 2... Comparison address memory pointer, 3... Comparison match detection section, 4... Match count counting section, 5...・Specified condition setting section, 6...Specified condition detection section, a...
...Execution address signal, b...Comparison match signal,
C...Condition match signal.

Claims (1)

【特許請求の範囲】 　記憶装置に記憶されたプログラムの実行アドレスにあ
る命令を順次取出して実行する情報処理装置にあって、 （Ａ）実行アドレスに比較する複数個の比較アドレスを
保持する比較アドレスメモリ、 （Ｂ）前記比較アドレスメモリから読出す比較アドレス
を指示するとともに、比較一致信号により読出す比較ア
ドレスの指示を順次移動する比較アドレスメモリポイン
タ、 （Ｃ）プログラムの実行アドレスと前記比較アドレスメ
モリから読出された比較アドレスとを比較し、一致した
ときに前記比較一致信号を出力する比較一致検出部、 （Ｄ）前記比較一致信号が出力された一致回数を計数す
る一致回数計数部、 （Ｅ）前記比較一致信号の指定回数を含む指定条件を設
定して保持する指定条件設定部、（Ｆ）前記一致回数計
数部で計数している一致回数と前記指定条件設定部に保
持する指定回数との一致を含む前記指定条件設定部の指
定条件が満足されたときに、条件一致信号を出力する指
定条件検出部、 を備えることを特徴とする実行アドレス検出方式。[Scope of Claims] An information processing device that sequentially retrieves and executes instructions at an execution address of a program stored in a storage device, comprising: (A) a comparison address that holds a plurality of comparison addresses to be compared with an execution address; (B) a comparison address memory pointer that indicates a comparison address to be read from the comparison address memory and sequentially moves the instruction of the comparison address to be read by a comparison match signal; (C) a program execution address and the comparison address memory; (D) a match count counter that counts the number of times the comparison match signal has been output; (E) ) a specified condition setting unit that sets and holds specified conditions including the specified number of times of the comparison match signal; (F) the number of matches counted by the number of matches counting unit and the specified number of times held in the specified condition setting unit; An execution address detection method comprising: a specified condition detection section that outputs a condition match signal when a specified condition of the specified condition setting section including a match is satisfied.
JP63056747A 1988-03-09 1988-03-09 System for detecting execution address Pending JPH01229340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63056747A JPH01229340A (en) 1988-03-09 1988-03-09 System for detecting execution address

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63056747A JPH01229340A (en) 1988-03-09 1988-03-09 System for detecting execution address

Publications (1)

Publication Number Publication Date
JPH01229340A true JPH01229340A (en) 1989-09-13

Family

ID=13036118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63056747A Pending JPH01229340A (en) 1988-03-09 1988-03-09 System for detecting execution address

Country Status (1)

Country Link
JP (1) JPH01229340A (en)

Similar Documents

Publication Publication Date Title
JPH01229340A (en) System for detecting execution address
JPH01211129A (en) Information processor
JPH028942A (en) Method for measuring frequency of occurrence of instruction
JPH04147350A (en) Microprogram step appearance frequency counting method
JPS61141046A (en) System for controlling debug interruption
JPH05158731A (en) Debugger
JPH04255037A (en) Program control circuit
JPH03105433A (en) Measurement device for micro instruction appearing frequency
JPH04104335A (en) Memory stop trapper
JPS6292036A (en) Information processor
JPS6270947A (en) Control system for debug interruption
JPH0353370A (en) Parallel processor for information processor
JPS626341A (en) Information processor
JPS63124145A (en) Information processor
JPH02100145A (en) Computer system for microprogram control system
JPH01316826A (en) Register file address circuit
JPH0362233A (en) Address match timing tracing mechanism
JPH01185738A (en) Address trace circuit
JPS61131051A (en) Traced data storing system
JPS62129775A (en) Simultaneously counting circuit of position ct apparatus
JPS6419439A (en) Central processing unit
JPH04232537A (en) Trace system
JPS63124144A (en) Information processor
JPH01304559A (en) Input/output function test system
JPH03240138A (en) Microprocessor