JPS6224334A - Stack circuit - Google Patents

Stack circuit

Info

Publication number
JPS6224334A
JPS6224334A JP60163353A JP16335385A JPS6224334A JP S6224334 A JPS6224334 A JP S6224334A JP 60163353 A JP60163353 A JP 60163353A JP 16335385 A JP16335385 A JP 16335385A JP S6224334 A JPS6224334 A JP S6224334A
Authority
JP
Japan
Prior art keywords
program
stack
flag
contents
program counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60163353A
Other languages
Japanese (ja)
Inventor
Tomoko Matsuki
松木　智子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60163353A priority Critical patent/JPS6224334A/en
Publication of JPS6224334A publication Critical patent/JPS6224334A/en
Pending legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To omit process where a debug row is inserted to a program and to simplify debugging by designating a check flag when a program is started and holding the contents of a program counter in a stack when the designated flag changes. CONSTITUTION:In an arithmetic logic operation processing mode, the contents of a program counter 1 are held in a stack 2 every time the flag designated when a program is started changes to '1' from '0' in a flag group 4 showing the state of the process carried out by an arithmetic logic operator 3. Thus if an overflow flag, for example, is designated when the program is started, it is possible to detect a specific step of the program where an overflow is produced from the value of the counter 1 held in the stack 2 after the processing is through with the program. In such a way, the debug can be simplified by omitting a process where a debug row is inserted to the program.

Description

【発明の詳細な説明】 し産業上の利用分野〕 本発明のスタック回路関し、特に算術論理演算器の処理
によるフラグ群の変化時のプログラムカウンタの内容を
保持するスタックを有するスタック回路に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a stack circuit, and more particularly to a stack circuit having a stack that holds the contents of a program counter when a group of flags changes due to processing by an arithmetic logic unit.

〔従来の技術〕[Conventional technology]

信号処理等においてプログラｌ、のどこでオーバーフロ
ー等が起こるかは、しばしば重要なことがある。従来、
オーバーフロー等かプログラムのと、二で起こるかを発
見する手段としては、プログラム内にデバ・・ｌグ処理
用のステップを多数設けることにより実現される。即ち
、算術論理演算処理ステ・ソブのあとに、処理結果をデ
ィスプレーーやプリンタ等の出力装置に出力するステッ
プを設けるなどして処理データをチェックすることによ
り、オーバーフロー等が起こった場合にそれかプログラ
ムのどこで起こったかを発見することができる。In signal processing and the like, it is often important where an overflow occurs in a program. Conventionally,
As a means of discovering whether an overflow or the like occurs in a program, it is realized by providing a large number of steps for debugging processing within the program. In other words, by checking the processed data by providing a step after the arithmetic and logical operation processing step to output the processing result to an output device such as a display or printer, it is possible to detect if an overflow occurs. You can discover where it happened in your program.

〔発明が解決しようとする問題点１ 上述した従来例に示すように、処理データのオーバーフ
ロー等がプログラムのどこで起こるかを発見する際には
、処理データをチェックするために１０グラム内に多数
のデバッグ行を挿入するという煩雑な処理が必要である
ので、プログラムサイズが大きくなり、またディスプレ
ーや１リンタ等の出力装置に出力するために処理に時間
がかかるという欠点がある。[Problem to be Solved by the Invention 1] As shown in the conventional example described above, when discovering where in a program an overflow of processing data occurs, it is necessary to Since the complicated process of inserting debug lines is necessary, the program size becomes large, and the process takes a long time to output to an output device such as a display or a printer.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のスタック回路は、プログラムカウンタと、該プ
ログラムカウンタの内容を保持するスタックと、算術論
理演算器と、該算術論理演算器による処理状態を示すフ
ラグ群と、該フラグ群の内容の変化により前記プログラ
ムカウンタの内容を前記スタッフに保持するように制御
を行う制御回路とを備えている。The stack circuit of the present invention includes a program counter, a stack that holds the contents of the program counter, an arithmetic and logic unit, a group of flags indicating the processing status of the arithmetic and logic unit, and a stack circuit that stores the contents of the program counter. and a control circuit that performs control so that the contents of the program counter are held in the stuff.

〔実施例〕〔Example〕

次に１本発明について図面を用いて説明する。 Next, one aspect of the present invention will be explained with reference to the drawings.

第１図は本発明のスタック回路の一実施例を示すブロッ
ク図である。FIG. 1 is a block diagram showing an embodiment of the stack circuit of the present invention.

第１図において、スタック回路はプログラムカウンタ１
と、指定フラグが°゛ｌ゛に変わった時点のプログラム
カウンタ１の内容を保持するスタック２と、算術論理演
算器３と、算術論理演算器３による処理状態を示すフラ
グ群４と、フラグ群４の中から指定されたフラグが′１
′′に変わっな時点のプログラムカウンタ１の内容をス
タック２に保持するように制御する制御回路５とからな
る、本実施例によれば、前述のプログラム内にデバ・ソ
ゲ行を挿入する処理が全く必要なくなる。即ち、第１図
に示すスタック回路では、算術論理演算処理を行う場合
、算術論理演算器３による処理状態を示すフラグ群４の
中でプログラムを起動する際に指定したフラグが“０゛
から“°１°゛に変わるごとに、その時点のプログラム
カウンタ１の内容をスタック２に保持する。従って、例
えば１０グラムを起動する際にオーバーフローフラグを
指定すれば、このプログラムの処理が終わった後、スタ
・・Ｉり２に保持されたプログラムカウンタ１の値から
１０グラムのどのステップでオーバーフローが起こった
かを発見することができる。In Figure 1, the stack circuit is program counter 1.
, a stack 2 that holds the contents of the program counter 1 at the time when the designated flag changes to °゛l゛, an arithmetic and logic unit 3, a flag group 4 that indicates the processing status by the arithmetic and logic unit 3, and a flag group. The flag specified from 4 is '1
According to this embodiment, the process of inserting the deba-soge line into the program described above is It won't be needed at all. That is, in the stack circuit shown in FIG. 1, when performing arithmetic and logic operation processing, the flag specified when starting the program among the flag group 4 indicating the processing state by the arithmetic and logic unit 3 changes from "0" to "". Every time the program counter changes by 1°, the contents of the program counter 1 at that time are held in the stack 2. Therefore, for example, if you specify the overflow flag when starting 10g, after this program has finished processing, at which step in 10g will the overflow occur from the value of program counter 1 held in star 2? You can discover what happened.

Claims (1)

【特許請求の範囲】[Claims] 情報処理装置のスタック回路において、プログラムカウ
ンタと、該プログロムカウンタの内容を保持するスタッ
クと、算術論理演算器と、該算術論理演算器による処理
状態を示すフラグ群と、該フラグ群の内容の変化により
前記プログラムカウンタの内容を前記スタックに保持す
るよう制御を行う制御回路とを備えることを特徴とする
スタック回路。In a stack circuit of an information processing device, a program counter, a stack that holds the contents of the program counter, an arithmetic logic unit, a flag group indicating a processing state by the arithmetic logic unit, and a change in the contents of the flag group. and a control circuit that performs control to hold the contents of the program counter in the stack.
JP60163353A 1985-07-23 1985-07-23 Stack circuit Pending JPS6224334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60163353A JPS6224334A (en) 1985-07-23 1985-07-23 Stack circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60163353A JPS6224334A (en) 1985-07-23 1985-07-23 Stack circuit

Publications (1)

Publication Number Publication Date
JPS6224334A true JPS6224334A (en) 1987-02-02

Family

ID=15772271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60163353A Pending JPS6224334A (en) 1985-07-23 1985-07-23 Stack circuit

Country Status (1)

Country Link
JP (1) JPS6224334A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06510976A (en) * 1992-01-27 1994-12-08 ベロイト・テクノロジーズ・インコーポレイテッド Articulated rider roll device and method
US11792911B2 (en) 2021-06-17 2023-10-17 International Business Machines Corporation Flexible cold plate for contacting varied and variable chip heights

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06510976A (en) * 1992-01-27 1994-12-08 ベロイト・テクノロジーズ・インコーポレイテッド Articulated rider roll device and method
US11792911B2 (en) 2021-06-17 2023-10-17 International Business Machines Corporation Flexible cold plate for contacting varied and variable chip heights

Similar Documents

Publication Publication Date Title
US5717851A (en) Breakpoint detection circuit in a data processor and method therefor
JPS6224334A (en) Stack circuit
US5872961A (en) Microcomputer allowing external monitoring of internal resources
US20150363351A1 (en) Data transfer device and data transfer method
JPH03105503A (en) Programmable controller
JPS58181158A (en) Storage device of state history
JPS6160146A (en) Check system of microprogram
JP2002163224A (en) Information processing system and interface processing method
JPS62254237A (en) Inter-printer type branch instruction executing system
JPS6153579A (en) Tester for function of logical circuit
JPH08202415A (en) Program update detecting method for programming device
SU1387000A1 (en) Device for generating instruction flag
JPS61275941A (en) Trace control system
KR20030042240A (en) Method of processing alarm at the interactive program in a mmi system
JPH10320242A (en) Method for inspecting application task
JPS59220849A (en) Image comparison control system
JPH0346852A (en) Protocol setting system
JPH05100913A (en) Error factor searching system
JPH04248633A (en) Test system
JPS635441A (en) Hang-up condition detecting system
JPH02249040A (en) Information history storage circuit
JPS63124145A (en) Information processor
JPH04336631A (en) Error message output system
JPH01144135A (en) System for observing program executing process
JPH01229340A (en) System for detecting execution address