JPH01228167A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce parasitic resistance and to prevent performance characteristics abnormalities by a method wherein the outer section of a part, which is in contact with an aluminum electrode, of a high concentration diffusion region, formed on a semiconductor substrate is subjected to etching for the formation of a step-like abruptness near the contact. CONSTITUTION:The surface of a P-type semiconductor substrate 1 is subjected to etching, except for regions for contact with aluminum electrodes 7, 8 respectively for N<+>-type source and drain regions 3, 4, and except for their outer circumferences, for the production of step-like abruptnesses 3a, 4a surrounding the N<+>-type regions 3, 4, respectively. Stepped oxide films 5 are next provided along the abruptnesses 3a, 4a, for the suppression of aluminum atom contaminated regions from being formed within an N<+>-type region 2. This design protects electrode sections from possible characteristics abnormalities inserting polycrystalline silicon between the aluminum electrodes 7, 8, which reduces J-FET parasitic resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a structure for preventing characteristic abnormalities at electrode formation sites.

[Conventional technology]

Conventionally, transistors used for high frequency amplification or high frequency oscillation have adopted fine pattern structures to increase the integration density in order to increase the gain bandwidth product.

Figure 3 shows a conventional N-channel junction type FE for high frequency amplification.
1 is a vertical cross-sectional view of a T (J-FET), in which an N-type region 2 is formed in a P-type semiconductor substrate l as a P-type source region, and a P-type gate region 6 is further formed approximately in the center thereof. Also,
An N' type source region 3 and an N' type drain region 4 are formed at positions sandwiching this P type gate region 6, respectively, and a source N' type polysilicon layer 9. Aluminum source electrode 7. via drain N-type polysilicon layer 10. An aluminum drain electrode 8 is electrically connected. Note that 5 is an oxide film.

Here, as an example, the width W of the P-type gate tJ region 6.

is 1 to 1.5 μm, the contact dimension Wc of the N"" type source region 3 and the N4 type drain region 4 is 1 to 2 μm, N
The overlap size between each diffusion region of the "type source region 3 and N+ type drain region 4 and the oxide film 5 is 0.2 to 0.2".
It is about 5 μm.

Here, the reason why polysilicon layers 9 and 10 are provided on the source electrode and the drain electrode, respectively, is as follows.

That is, as shown in FIG.
(or the aluminum drain electrode 8), a 350-460"b alloy treatment is performed to improve ohmic properties. At this time, the overlap dimension is 0.
．． Since the thickness is as narrow as 2 to 0.5 μm, aluminum tends to advance to the interface between the N-type region 2 and the oxide film 5, and an aluminum atom penetration region X may be formed in the N-type region 2. When this aluminum atom penetration region X is formed in the N-type region 2, abnormalities in characteristics such as withstand voltage deterioration are likely to occur.

For this reason, in the past, polysilicon 19.10 was interposed between each N-type region of the source and drain and the aluminum electrode, and the size of the N-type region between the N-type region and the N-type region was made long. This suppresses the entry of aluminum atoms.

[Problem to be solved by the invention]

In the conventional configuration described above, the polysilicon layers 9 and 10 interposed between the aluminum electrode and the N-type region have irregular crystal alignment compared to single-crystal silicon, so the resistance is low even with the same impurity concentration. The parasitic resistance of the J-FET increases, the resistance between the source and drain increases, the gain bandwidth product decreases, and the J-FE for high frequency amplification increases.
There is a problem that the characteristics as T are impaired.

An object of the present invention is to prevent such deterioration of characteristics and provide a semiconductor device with improved gain-bandwidth product.

[Means to solve the problem]

The semiconductor device of the present invention has an electrode structure in which an aluminum electrode is formed in contact with a high concentration diffusion region formed on a semiconductor substrate. A stepped portion is formed around the contact portion.

[Effect]

In the above configuration, although the aluminum electrode is in direct contact with the highly active diffusion region, the dimension between the aluminum electrode and the semiconductor substrate side in the high concentration diffusion region is lengthened by the stepped portion, and the dimension between the aluminum electrode and the semiconductor substrate side in the high concentration diffusion region is lengthened. Suppresses the entry of aluminum atoms into.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention.

An N-type region 2 is formed in a P-type semiconductor substrate 1 as a P-type gate region, and a P-type gate region 6 is formed approximately in the middle of the N-type region 2. These P-type gate regions 2.6 are electrically connected to the same potential by a diffusion layer or an aluminum electrode (not shown). In the N-type region 2, an N'' source region 3 and an N'' drain region are formed with a P-type HM region 6 in between, and an aluminum source electrode 7 and an aluminum source electrode 7 are formed in each region through a window formed in the oxide film 5. The aluminum drain electrode 8 is formed by ohmic contact.

Here, the P-type semiconductor substrate 1 has an N source region 3.
and an aluminum electrode 7. and N-type drain region 4, respectively.
The other surface is etched to a depth d, leaving the area for contact with 8 and its outer part, and as a result, each N
Stair-like step portions 3a and 4a are formed around the ゛-shaped area 4. The oxide film 5 also has these step portions 3a, 4a.
It is shaped like a staircase.

Therefore, due to the step portions 3a and 4a, in each N-type region 4, the dimension from the aluminum electrode 7.8 to the N-type region 2 is the same as that of each N-type region.

4 and the etching depth d, and the formation of an aluminum atom intrusion region in the N-type region 2 is suppressed. As a result, it is possible to suppress the occurrence of characteristic abnormalities in the electrode part without interposing polysilicon between the N+ type region aluminum electrode and the J-
It is possible to obtain a semiconductor device with high characteristics in which the parasitic resistance of the FET is reduced and the gain bandwidth product is improved.

Note that in order to increase the length from the aluminum electrode 7.8 to the N-type region 2, the etching depth d must be as large as possible and the overlap dimension of the N-type region must be increased. is preferred.

FIG. 2 is a longitudinal sectional view of a second embodiment of the present invention, which is an example in which the present invention is applied to a high frequency bipolar transistor. P-type collector region 11. N-type base region 12.
The P+ type emitter region 13 constitutes a PNPI- transistor, and the base electrode 14. The emitter electrode 15 is made of metal such as aluminum.

Here, the P1 type emitter region 13 is left and the other parts are etched to form a step 13a around the P1 emitter region 13, and this step 13a connects the aluminum emitter electrode 15 to the N type base region 12. The dimensions are set long enough to reach the desired size.

In this configuration, N is adjacent to the P emitter region 13.
It is possible to prevent aluminum atoms from penetrating into the mold base region 12 without intervening polysilicon, thereby reducing parasitic resistance and constructing a bipolar transistor with high characteristics.

〔Effect of the invention〕

As explained above, in the present invention, the outside of the portion of the high-concentration diffusion region formed on the semiconductor substrate that comes into contact with the aluminum electrode is etched, and a stepped portion is formed around this contact portion. Although the aluminum electrode is in direct contact with the highly active diffusion region, the step-like step increases the dimension between the aluminum electrode and the semiconductor substrate side in the high concentration diffusion 9M region, allowing aluminum atoms to reach the semiconductor substrate side. This has the effect of suppressing the intrusion of particles, reducing parasitic resistance, and preventing the occurrence of characteristic abnormalities.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view of a first embodiment in which the present invention is applied to a J-FET for high frequency amplification, FIG. 2 is a vertical cross-sectional view of a second embodiment in which the present invention is applied to a bipolar transistor, and FIG. FIG. 4 is a vertical cross-sectional view of a conventional J-FET for high frequency amplification, and is a vertical cross-sectional view for explaining a problem when a polysilicon layer is not provided. 1...P-type gate jiff region (P-type semiconductor substrate), 2
...N-type region, 3...N゛゛source region, 3a...
- Step part, 4...N'' type drain region 4a... Step part, 5... Oxide film, 6... P type gate region, 7...
Aluminum source electrode, 8... Aluminum drain electrode, 9... Source N" type polysilicon layer, 10.
...Drain N-type polysilicon layer, 11...P-type collector region, 12...N-type base region, 13...P
゛゛Emitter region, 13a... step portion, 14... base electrode, 15... emitter electrode. Figure 3 Figure 4

Claims (1)

[Claims] 1. In a semiconductor device having an electrode structure in which an aluminum electrode is formed in contact with a high concentration diffusion region formed on a semiconductor substrate, the outside of the portion of the high concentration diffusion region that is in contact with the aluminum electrode is etched, and the area around this contact portion is etched. A semiconductor device characterized in that a stepped portion is formed in the semiconductor device.