JPH01228144A - Circuit for setting trimming code - Google Patents

Abstract

PURPOSE:To enable a trimming code to be selected at a low voltage and with a single power supply by a method wherein a thin film resistor is connected between an earth potential and the source of an N-channel MOS transistor and the drain and the gate of the N-channel MOS transistor are respectively connected to the highest potentials. CONSTITUTION:One end of a thin film resistor is connected to the lowest potential Vss, the other end of the resistor is connected to a source of an N-channel MOS transistor 1 and a drain and a gate of the transistor 1 are respectively connected to the highest potentials Vcc. Moreover, the nodal point between one end of the thin film resistor and the source of the transistor 1 is connected to an input of a complementary inverter constituted of an N-channel MOS transistor 2 and a P-channel MOS transistor 1 having a threshold voltage of the absolute value larger than that of the threshold voltage of the transistor 1. A trimming code is set by the output of the inverter 1. Thereby, a selection of the trimming code becomes possible in a low voltage and by a single power supply.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for trimming a semiconductor integrated circuit device, and more particularly to a circuit for setting a code for trimming.

[Conventional technology]

In semiconductor integrated circuit devices, the catalog standards are very strict for setting reference voltage values and circuit currents, especially for analog circuits, so trimming circuits are required to bring the voltage and current values within the catalog standards. In need of.

Conventionally, a circuit as shown in FIG. 3, for example, has been used to set the trimming code. However, Fig. 3 shows the highest potential V. . This is a case where three trimming code setting circuits are configured between =+5V and the lowest potential -VSS=-5V.

Next, the operation of this circuit will be explained. The explanation will be given by taking up one consisting of a P-channel MOS transistor MP9 and a thin film resistor R8. First, P channel MO
The S-type transistor MP9 is also mirror-connected to the P-channel MOS transistor MP7, and attempts to flow a constant current.

At this time, when the resistor R8 is not disconnected, the resistance of the resistor R8 is smaller than the ON resistance of the transistor MP9, so that the node (2) falls below the logical threshold voltage of the inverter 8. Therefore, inverter 8 outputs a high level. Next, if the resistor R8 is disconnected, the potential at the node (2) is raised to a level higher than the logical threshold voltage of the inverter 8 by the transistor MP9. Therefore, inverter 8
outputs a low level.

In other words, the trimming code can be set depending on whether or not the resistors R7 to R9 are disconnected.

For example, in this circuit as shown in FIG. 4, if resistor R8 is disconnected but resistors R7 and R9 are not disconnected, inverter 8 will output a low level, inverter 7, inverter 9
outputs a high level output and the trimming code is set.

Note that cutting of a thin film resistor such as polysilicon is normally carried out in a wafer inspection process using a tester or the like, in which a pad made of wiring material such as aluminum is taken out from the node of the thin film resistor and a P-channel MOS transistor. That is, the pad connected to the thin film resistor to be cut and -VSS
A voltage of about 10 V is applied between the two, and a current is passed through the thin film resistor to fuse it.

[Problem to be solved by the invention]

In this way, the trimming code is set. In the circuit shown in FIG. 3, the above-mentioned V, cc=+
5 V, LS with Vss = 5 V (7) power supply
It can be used in I, but it cannot be used in LSI with vo0=+5V single power supply. To explain the reason for this, in the case of a 5V single power supply, it is necessary to form a trimming code setting circuit between VCC and the ground potential (hereinafter referred to as GND), as shown in FIG.

As mentioned above, cutting a thin film resistor requires applying a voltage of about IOV, but vo. Since it is dangerous to apply a voltage higher than the absolute maximum rating of the LSI (usually 7V), a voltage higher than 7V cannot be applied. Therefore, V is applied to the drain of the P-channel MOS transistor. . This P-channel MO
The substrate potential of the S-type transistor is ■. . Therefore, the Pn junction between the P+ type diffusion layer of the drain and the n type substrate is in the forward direction, making it impossible to apply IOV. In other words, it becomes impossible to cut the thin film resistor.

[Means to solve the problem]

In the present invention, in a trimming circuit that sets a desired code depending on whether or not to cut a thin film resistor such as polysilicon, one end of the thin film resistor is connected to the lowest potential, and the other end is connected to the n-channel MOS transistor 1. The drain and gate of the N-channel MOS transistor 1 are connected to the highest potential, and the node between one end of the thin film resistor and the source of the N-channel MOS transistor 1 is connected to the N-channel MOS transistor 2 and the N-channel MOS transistor 1. It is connected to the input of a complementary inverter 1 composed of a P-channel MOS transistor l having a threshold voltage larger in absolute value than the threshold voltage of the channel MOS transistor 1, and the output of the complementary inverter 1 The trimming hood is set.

This makes it possible to select a trimming code using a low voltage power supply such as a single +5V power supply.

〔Example〕

Next, the present invention will be explained using figures.

FIG. 1 is a circuit diagram of an embodiment of the present invention. However, this figure shows a case where three trimming code setting circuits are provided. As shown in the figure, n-channel transistors are used in areas where P-channel transistors were conventionally used. In other words, a thin film resistor is connected between the ground potential and the source of the N-channel MOS transistor, and the drain and gate of the N-channel MOS transistor are
is connected to. The circuit operation is the same as the conventional example. For example, considering one trimming code setting circuit composed of an N-channel MOS transistor MN2, a resistor R2, and an inverter 2, first, if the resistor R2 is not disconnected, the ON resistance of the N-channel MOS transistor MN2 is is set to be larger than the resistor R2, so the node (2) becomes less than the logical threshold voltage of the inverter 2, and the inverter 2 outputs a high level.

Next, when resistor R2 is disconnected, the potential at node 2 is
V by transistor MN2. . -(threshold voltage of MN2). Here, the logical threshold voltage of inverter 2 is V. . - (threshold voltage of MN2) or less, inverter 2 outputs a low level. In other words,
The trimming code can be set depending on whether or not the resistors R1 to R3 are cut off.

Here, the same cutting as described above is performed by applying a voltage of about IOV between the pads taken out from the nodes (2), (2), and (3) and GND, but since MNI to MN3 are n-channel MOS transistors, the contact point (2) Even if IOV is applied to ~■, the sources of transistors MNI to MN3 are not forward biased. Also, since 5■ is applied to VCC, the sources of transistors MNI to MN3,
There is only a potential difference of 5V between the drains, and a voltage of less than 7V, which is the absolute maximum voltage, is applied.

Therefore, the circuit of the present invention can be used without any problems even in an LSI with a +5V single power supply.

Here, consider again the case where the resistor R2 is disconnected in the trimming code setting circuit configured by the transistor MN2, the resistor R2, and the inverter 2. As mentioned above, in this case, the potential of node ■ is Vcc
(threshold voltage of MN2), but if the absolute value of the threshold voltage of P-channel MOS transistor MP2 constituting inverter 2 is
In other words, (threshold voltage of MN2)>(threshold voltage I of 1MP2)...
...Consider the case (1).

In this case, the potential of node ■, that is, the input of inverter 2, is vcc (threshold voltage of MN2), so that (threshold voltage of MN2) is applied between the gate and source of transistor MP2. Ru.

Here, because of the relationship expressed by equation (1), a voltage higher than the threshold voltage of transistor MP2 is applied between the gate and source of transistor MP2, and transistor MP2
2 means it is ON.

Therefore, the inverter 2 will continue to pass through current. This is a problem because it increases the power consumption of the LSI.

In the circuit of this embodiment, by setting the absolute value of the threshold voltage of the transistor MP2 to be larger than the threshold voltage of the transistor MN2, the transistor MP2 is turned on.
This is to prevent this through current.

FIG. 2 is a circuit diagram of another embodiment of the invention.

In one embodiment shown in FIG. 1, as described,
When the thin film resistor is disconnected, the potential at the node between the source of the n-channel MOS transistor and the thin film resistor becomes VCC (
(threshold voltage of an n-channel MOS transistor), and the smaller this threshold voltage is, the more margin there is for the logical threshold of the next stage inverter.

That is, by using an n-channel transistor with a small threshold value, a more reliable trimming code setting circuit can be obtained.

Here, the P-type substrate that forms a normal complementary MOSLSI has a substrate concentration of about 10"[cm-"], and an n-channel M in which this substrate is used as it is for the channel part.
If you use an OS type transistor, you can easily set the threshold value to
An n-channel MOS transistor of 0.2 V or less can be easily realized.

Here, if transistors with a threshold value of 0.2V or less are used as the N-channel MOS transistors MNOI to MNO3 in FIG. This prevents a through current from flowing through the inverter, making it easier to set the threshold voltage of the P-channel MOS transistor.

〔Effect of the invention〕

As described above, the trimming code setting circuit according to the present invention can be used not only in ±5V power supply type LSIs but also in +5V single power supply type LSIs, and has the effect of not increasing unnecessary power consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention, and FIGS. 3 and 4 are:
FIG. 5 is a circuit diagram showing a conventional example, and FIG. 5 is a circuit diagram for explaining the problem to be solved by the present invention. MNI to MN9... N-channel MOS transistor, MNOI to MNO3... N-channel MOS transistor with a threshold voltage of 0.2 V or less, MP1 to MP14...P Channel MOS type transistor, R1-R12...Thin film resistor such as polysilicon. Agent Patent Attorney Oto Uchihara Figure 1 Figure 2 Figure 3 Figure 4

Claims (2)

[Claims] (1) In a trimming circuit that sets a desired code depending on whether or not to cut a thin film resistor, one end of the thin film resistor is connected to the lowest potential, and the other end is connected to a first MOS of one conductivity type.
MOS type transistor, the drain and gate of the first MOS type transistor are connected to the highest potential, and the node between one end of the thin film resistor and the source of the first MOS type transistor is connected to the one conductivity type transistor. and a third MOS transistor of another conductivity type having a threshold voltage larger in absolute value than the threshold voltage of the first MOS transistor. A circuit for setting a trimming code, characterized in that the circuit is connected to an input of the complementary inverter 1 and sets a trimming code by the output of the complementary inverter 1. (2) The trimming code setting circuit according to claim 1, wherein an N-channel MOS transistor having a threshold value of 0.2 V or less is used as the first MOS transistor.