JPH01225222A - Power-on reset circuit - Google Patents

Abstract

PURPOSE:To send a reset pulse when an exact time passes after a power source is inputted by successively shifting the '0' of a negative power source to be impressed to a first step. CONSTITUTION:Since a positive power source 3 is impressed to the BAF inputs of respective steps 111-11n and 161-16n in a basic circuit just after the power source is inputted, the both outputs of the final steps 11n and 16n are logic '1' and the output of an EXOR circuit 18 is '0'. When a clock signal executes an N-times of changes, the '0' due to a negative power source 19 in the first step 161 is successively shifted and appears as the output of the final step 16n. Thus, the both inputs of the EXOR circuit 18 goes to be decident and the reset pulse is sent from this EXOR circuit 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power-on reset circuit that generates a reset pulse in response to power-on.

[Conventional technology]

Reset circuits are used in various electronic circuits for the purpose of setting the initial state when the power is turned on, and conventionally, the configuration shown in the circuit diagram in Figure 2 has generally been adopted. .

That is, a power supply 3 is applied to a series circuit of a resistor element 1 and a capacitor 2, and the voltage becomes zero when the power is turned on.
The terminal voltage of the capacitor 2, which increases according to a time constant, is inverted by the inverter 4, and a reset pulse RP is obtained from the output of the inverter 4 until the terminal voltage of the capacitor 2 increases.

[Problem to be solved by the invention]

However, in the configuration shown in Fig. 2, when integrating the circuit,
A large space is required to form the capacitor 2, which results in an increase in the chip area of the integrated circuit, resulting in a drawback that it is generally difficult to integrate the circuit.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention is configured by the following means.

That is, a basic circuit in which power is applied to the drain of a MOS transistor (hereinafter referred to as MO8TR) via a resistive element and the input of a battery circuit (hereinafter referred to as BAF) is connected to this drain is connected to N (N=2.3.4). ...) stepped,
BAF output and MOS T H in each basic circuit with
a first cascade circuit in which the sources of the first cascade circuit are sequentially connected, a second cascade circuit having the same configuration as the first cascade circuit, and a BAF in the final stage of these first and second cascade circuits.
Exclusive OR (hereinafter referred to as EXOR) using each output as input
a positive power supply applied to the source of MO8TR in the first stage of the first cascade circuit, a negative power supply applied to the source of MO8TH in the first stage of the second cascade circuit, and two of the first and second cascade circuits. ×I-1 (I=1.2.3...)
The first clock signal applied to the gate of each MO8TR in the stage and the 2x I (
The second clock signal changes complementary to the first clock signal applied to the gate of each MO8TH in the I=1.2.3...) stage.

[Effect]

Therefore, a shift register is configured by each of the first and second cascaded circuits, and the final stage outputs of both are the same immediately after power is turned on, and the output of the EXOR circuit is the logical value rOJ.
On the other hand, in response to the application of each clock signal, the "0" of the negative power supply applied to the first stage of the second cascade circuit is sequentially shifted and sent to the final stage output, and at this time, the EXO
The two forces in the R circuit do not match, and a reset pulse with a logic value of "1" is sent out.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to the circuit diagram of FIG. 1 showing an embodiment.

In the figure, as the basic circuit 111 is shown as a representative, an N-channel MO8TR 12 is used, and the positive power supply 3 is applied to the drain thereof via the resistive element 13.
Connect the input of BAFl 4 to this drain, and connect these basic circuits 111 to 11rl to N (N=2.3.4
...) Stage provision, B in each basic circuit 111 to 11H
Connect the output of AF' and the source of MO8TR in sequence,
A first cascade circuit 15 is configured.

In addition, a basic circuit 16 similar to the basic circuits 111 to 11rl
, ~ten, a second cascade circuit 17 having the same configuration as the cascade circuit 15 is provided, and the final stage 11n of both circuits 15.17
, 16n is given to the input of the EXOR circuit 18, while the positive power supply 3 is applied to the source of MO8TH in the first stage 111 of the cascade circuit 15.
7 Shodan 16. A negative power supply 19 is applied to the source of MO8TH in .

In this 1, 2xl-1 (I
=1.2.3...) stage 11it181+11s+16
6. The first clock signal CLK is applied to the gates of the MO8TRs in odd-numbered stages such as 11s and 16s, and the 2×I (■=1.2.3
...) Stage 11ss18st114*16*+11st
A second clock signal CLK that changes complementary to the clock signal CLK is applied to the gates of HO8TH in even-numbered stages such as 16a, and thereby both cascade circuits 15
．． 17 to operate as a shift register.

Therefore, immediately after turning on the power, each stage 111 to 11n11
Since the positive power supply 3 is applied to the BAF inputs of 61 to 16n, both outputs of the final stage 11n and 116H have the logical value "
1'' and the output of the EXOR circuit 18 is 0. However, when the clock signals CLK and CLK each change N times, the output of the first stage 16. "0" from the negative power supply 19 is sequentially shifted according to the on/off of each MO8TR, and appears as the output of the final stage 16n, while the first stage 1
Since “1” is given to 11 by the positive power supply 3,
Even if this is similarly shifted and appears at the final stage 11n, this output will maintain "1".
Since the two inputs of the OR circuit 18 do not match, the reset pulse RP of rlJ is sent out from the circuit 18.

Therefore, the time from power-on to sending out the reset pulse RP becomes accurate, and it can be configured without using a capacitor, making it easy to reduce the chip area when integrated circuits are fabricated.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, MO
A basic circuit in which power is applied to the drain of 8TR via a resistance element and the input of BAF is connected to the drain is
providing a step, thereby configuring a first cascade circuit, and
A second cascade circuit having the same configuration is provided, an EXOR circuit is provided which takes the final stage outputs of both circuits as input, and a positive power supply and a negative power supply are applied to each first stage of both cascade circuits to establish a complementary relationship. The first and second clock signals having
By shifting each logical value from the positive power supply and negative power supply of each initial stage to the first stage, the purpose can be achieved without using a capacitor, and integrated circuits can be easily integrated. Significant effects on development can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional example. 3@@11@positive power supply, 111~11n, 161~16n
...Basic circuit, 12.--MOS transistor, 13.Fist/life resistance element, 14.Buffer circuit,
15.17...cascade circuit, 18 fist...exclusive OR circuit, 19...negative power supply, CLK, CLK...
Clock signal, RP...reset pulse.

Claims (1)

[Claims] N (N=2, 3, 4...) stages of basic circuits are provided in which power is applied to the drain of the MOS transistor via a resistive element, and the input of a buffer circuit is connected to the drain, and in each of the basic circuits, The output of the buffer circuit and M
a first cascade circuit in which the sources of the OS transistors are sequentially connected; a second cascade circuit having the same configuration as the first cascade circuit; and a buffer circuit in the final stage of the first and second cascade circuits. a positive power supply applied to the source of the MOS transistor in the first stage of the first cascade circuit, and a positive power supply applied to the source of the MOS transistor in the first stage of the second cascade circuit; 2×I of the negative power supply and the first and second cascade circuits.
The first clock signal applied to the gate of each MOS transistor in the -1 (I=1, 2, 3...) stage and the 2×I (I=1, 2,
3...) A power-on reset circuit comprising a second clock signal that changes complementary to the first clock signal applied to the gate of each MOS transistor in the stages.