JPH01223577A - Ct picture re-constituting device - Google Patents

Abstract

PURPOSE:To drastically shorten a processing time by respectively sharing, executing and controlling the writing, reading and adding processing of picture data for respective addresses corresponding to a difference picture element for approximately same time to a storage device and an adding device. CONSTITUTION:Into a picture memory 8, a picture data after the picture data of the same address fetched to be newly added are added and processed to the picture data before adding corresponding to an address n-1 read from a picture memory 9 are written and processed. Simultaneously, picture data corresponding to an address n+1 are read and processed from a picture memory 9. Simultaneously, an adder 13 adds and processes the picture data corresponding to an address (n). Namely, the plural different processings are executed approximately in the same time. When these processings of one procession are completed, the picture data for a picture element are read from the memory 8, the picture data fetched newly are added to this and written to the memory 9. The processing is repeated at a prescribe number of times, executed concerning all picture data and the processing is completed.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to a CT system that reconstructs both CT images based on back projection image data collected from, for example, an X-ray CT scanner.
The present invention relates to a T-image reconstruction device.

(Prior art) The configuration of the main parts of a conventional CT image reconstruction device is shown in Figure 4 (a).
).

In FIG. 3A, the main parts of the CT image reconstruction apparatus include an image memory 1 that stores back projection data for each pixel taken in through a data register 3 in correspondence with addresses, and this image memory 1. The image data processing apparatus includes an adder 2 that adds the read image data and the captured image data when the image data stored in the image data is read out.

In the conventional CT image reconstruction apparatus having such a configuration, as shown in FIG. The addition process by the adder 2 and the writing process 7 to the image memory 1 for 62 images were processed in series.

Here, for convenience of explanation, the readout process 5, the addition process 6. Assuming that the time required for each writing process 7 is tl, the processing time for any one pixel n requires a total time of 3i1.

(Problem to be Solved by the Invention) In other words, in the conventional CT image reconstruction device having the above-mentioned configuration, the above-mentioned three processes are performed for each pixel, and one process is completed, and then the next process is performed. However, despite the desire to improve the processing speed, it has not been possible to solve the problem.

On the other hand, the above problem can be solved by using devices that can process each image memory, adder 2, control section (not shown), etc. at high speed, but each element that can process at high speed is expensive, and the cost is low. The drawback was that it led to soaring prices.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a CT image regrooving device that is low in cost and can shorten the time required for reconstructing image data.

[Structure of the invention] (Means for solving the problem) The structure of the present invention for achieving the above object is based on the above-mentioned C.
In the T-image reconstruction device, a control means for controlling the execution of writing, reading, and adding the image data to each address corresponding to a different pixel by having the storage means and the adding means each share the writing, reading, and addition processing for each address corresponding to a different pixel within substantially the same time. It is assumed that

(Function) The function of the present invention having the above configuration is to write in a complementary manner,
A process of reading out both edge data recorded at an address corresponding to a specific pixel of a readable storage means, and a process of adding new image data to image data corresponding to another pixel different from this pixel. and the process of recording image data of a pixel different from the above two pixels in the storage means are performed within approximately the same time.

Therefore, the processing time can be significantly shortened compared to the case where processing similar to the conventional method is performed.

(Example) Hereinafter, a CT image reconstruction apparatus of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a CT image reconstruction apparatus as an example.

The CT image reconstruction device shown in the same figure uses image data (
A data register 12 for temporarily storing the image data (hereinafter simply referred to as image data); a data register 18 for temporarily storing the image data read from the image storage memory 9; A adder 13 that adds the image data and the image data sent out from the data register 12, a data register 14 that temporarily stores the added image data, and a data register 14 that adds the image data sent out from the data register 14. For example, RA
An image storage memory 8 consisting of M, etc. is connected and arranged.

On the other hand, on the image storage memory 9 side, there is a data register 17 for temporarily storing the image data read out from the image storage memory 8, and on the subsequent stage side, there is a data register 17 for storing image data sent from the data register 17 and the data register 17. 12; a data register 15 that temporarily stores the added image data; and an image storage memory 9 that stores the image data sent from the data register 15. are connected and arranged. Note that in this embodiment, the adder 13 and the adder 16
The addition means cumulatively adds the image data sequentially taken in corresponding to the pixel to the image data of each pixel read out from the image storage memories 8 and 9.

The image storage memory 82 and the image storage memory 9 include an address register 20.21 for temporarily storing back projection address data (hereinafter simply referred to as address data) corresponding to each pixel, and this address register 20.21. 21
An address selector 10 that selects an address for each pixel based on address data sent from the address selector 10. il is connected.

The address selector 10.11, image storage memory 82
A control bus 24 is connected to the image storage memory 9 for transmitting write control signals. The image storage memory 8 is connected to an inverter 19 that inverts a write control signal input to the image memory 9. Therefore, when a write control signal is sent from a control section to be described later via the control bus 24, for example, when the image storage memory 8 is in the writing state, the image storage memory 9 is in the reading state. And this writing state.

The read state changes alternately every time the write control signal is sent. In this way, in this embodiment, the image storage memory 8 and the image storage memory 9 constitute a storage means that can write and read data complementary to each other.

By the way, the data register 12 is composed of two data registers 12a and 12b. That is,
Of the image data that is sequentially captured, two successive image data can be temporarily stored. Also,
The address register 21 includes three address registers 21a.

It consists of 21b and 21c, and is configured to temporarily store three consecutive address data among address data that are sequentially fetched.

Each element explained above is the control center of the entire device.
Control is performed by a control unit 25 including a PU and the like in synchronization with a clock pulse CP from a clock generator (not shown).

Further, in this embodiment, in addition to the function as the control center, the control unit 25 performs the input/output, readout, and addition processing of the image data to each address corresponding to a different pixel within approximately the same time. The storage means 22 and the addition means 23 each have a function as a control means for carrying out execution control.

FIGS. 2(a), (b), and 3(a) show the functions and effects of this device configured as described above.

(Explanation will be given with reference to b>. Here, it is assumed that image data is written, read, and added for addresses corresponding to three different pixels, and the write control signal from the control unit 25 is Assume that the illustrated image storage memory 8 is in a writing state and the image storage memory 9 is in a reading state.

In addition, in this case, address n-2 is stored in the address register 21c, and address n-1 is stored in the address register 21b.
When address n is set in the address register 21a and address n is set in the address register 20, the address of the image storage memory 8 which is in the write state is set to n-2 by the address selector 10, and the address is set in the read state. The address of the image storage memory 9 is n
Assume that it is set to .

In such a state, the image data corresponding to address n-2 is temporarily stored in the data register 14 due to the previous timing signal. Therefore, the image data is stored in the image storage memory 8 by sending the timing signal. Simultaneously with this writing process, the adder 13 disposed before the data register 14 adds the image data to be written to the address n-1, and the image data stored in the image storage memory 9 is stored in the data register 18.
Image data at address n is read from and temporarily stored. Furthermore, the data register 12b disposed on the previous stage side of the adder 13 has the data register 12a
The image data corresponding to address n stored in is sent out and stored, and the image data corresponding to address n+1 newly fetched is stored in the data register 12a. On the other hand, the data register 17 stores the image data corresponding to the address n-2 sent from the data register 14, and the adder 16 stores the image data corresponding to the address n-1 that was previously recorded in the data register 12b. The image data and the image data corresponding to the same address stored in the data register 17 are added. Although image data corresponding to address n is stored in the data register 15, the image storage memory 9 is in a write-prohibited state, so the stored image data is not written.

This processing state is expressed as shown in FIG. 2(a).

That is, in the image storage memory 8, the image data at the same address that is newly taken in to be added is added to the image data before addition corresponding to the address n-2 read from the image storage memory 9. At the same time, the image data corresponding to address n is read out from the image storage memory 9 (indicated by 26), and at the same time, the adder 13 processes the image data corresponding to address n-1. Image data corresponding to is subjected to addition processing (indicated by 27)
It will be done.

By the way, focusing on the contents stored in the address register immediately after each of the above processes, the address register 21C contains the addresses n-1,
Similarly, address n is set in the address register 21b, address n+1 is set in the address register 21a, and address n+1 is set in the address register 20.

When the next timing signal is sent in this state, the following happens.

The address of the image storage memory 8 in the write state is set to n-1 by the address selector 10 by the timing signal, and the address of the image storage memory 9 in the read state is set to n+1.

First, since the data register 14 stores the image data corresponding to the address n-1 added by the adder 13 according to the previous timing signal, the image data is stored in the image storage memory 8 according to the current timing signal. written. Simultaneously with this writing process, the adder 13 placed before the data register 14 adds the image data to be written to the address n, and roughly the image data from the image storage memory 9 to the address n+1 is added to the data register 18.
image data is read out and temporarily stored. Furthermore, a data register 1 disposed on the previous stage side of the adder 13
The image data corresponding to the address n+1, which had been previously blocked in the data address 12a, is sent to and stored in the data register 2b, and the image data corresponding to the newly fetched address n+2 is stored in the data register 12a. .

On the other hand, the image data corresponding to address n-1 sent from the data register 14 is stored in the data register 17, and at the same time, the adder 16 stores the image data corresponding to the address n-1 sent from the data register 14.
The image data corresponding to address n stored in 2b and the image data corresponding to the same address stored in data register 17 are added. Note that although image data corresponding to address n+1 is stored in the data register 15, the image storage memory 9 is in a write-inhibited state, so the stored image data is not written.

This processing state is expressed as shown in FIG. 2(a) in the same way as described above. In other words, the image storage memory 8 stores the image data at the same address that is newly taken in to be added to the unadded image data corresponding to the address n-1 read out from the image storage memory 9. The image data after the addition process is written (indicated by 31), and at the same time, the image data corresponding to address n+'l is read out from the image storage memory 9 (indicated by 29), and at the same time, the adder 1
In 3, the image data corresponding to address n is subjected to addition processing (3
(indicated by 0). In other words, three different processes are executed within approximately the same amount of time.

By the way, when each process detailed above is completed for one project, the process for the next projection starts. For example, if the above-mentioned process rarely occurs on the P-th projection data shown in FIG. 3(a), then the P+
The first projection data is processed.

In this case, the image storage memory 8 and the image storage memory 9
The read and write states are reversed.

In this way, the previously added image data for each pixel is read out from the image storage memory 8, the newly captured image data is added thereto, and then written to the image storage memory 9. Then, such processing is repeated a predetermined number of times for all image data, and the process ends.

According to the apparatus of the embodiment described in detail above, 3
Compared to the processing time 3t1 required per pixel shown by 5, in this embodiment, the processing time per pixel is 11 as shown by 36, that is, the processing time for the entire process is approximately 1/3. be able to do it. Also, in this case, there is no need to use expensive high-speed processing elements, so there is no increase in costs.

It should be noted that the present invention is not limited to the above-mentioned embodiment illustrated or described, and various modifications can be made within the scope of the gist.

For example, in the above-described embodiment, three processes are executed almost simultaneously within the same time period, but four or more processes may be executed simultaneously. In this case as well, the same effects as in the embodiment described above can be obtained.

[Effects of the Invention] According to the present invention as detailed above, it is possible to reduce the time required for reconstructing image data at low cost.
We can provide a T-instrument reconstruction device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a CT image reconstruction device as an embodiment of the present invention, FIG. 2(a) is an operation explanatory diagram showing processing operations in the present invention, and FIG. 2(b) is the same. Figure (a
) Comparative explanatory diagram of the processing time required for the processing operation and the conventional processing time, Figure 3 (a) and (b> are the input and output of the image storage memory. Relationship between readout state and projection data FIG. 4(a) is a block diagram showing the configuration of the main parts of a conventional CT image reconstruction device, and FIG. 4(b) is an explanatory diagram showing its processing operation.22. - Storage means, 23... Addition means, 25... Control means.

Claims (1)

[Claims] A storage means capable of complementary writing and reading of image data to be back-projected for each pixel at a corresponding address;
A CT image reconstruction device for reconstructing a CT image, comprising: an adding means for cumulatively adding the image data sequentially captured corresponding to the pixel to the image data for each pixel read from the address; In the above, a control means is provided for controlling the writing, reading and adding of the image data to each address corresponding to a different pixel by causing the storage means and the adding means to share and control the execution, respectively, within approximately the same time. Features of CT image reconstruction device.