JPH01222298A - Display controller - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of a CPU, etc., by reading out only data of a on-line portion from an image memory, storing it in an auxiliary memory and thereafter, reading it out repeatedly. CONSTITUTION:Data which is outputted from a bus control circuit 17 is supplied to an RGB decoder 14, and also, supplied to a line memory 18 which comes to be used as an auxiliary memory, and data corresponding to the first one-line portion is written, respectively. Subsequently, read-out data of the remaining second - fourth lines are read out of the line memory 18 and used. Also, a four-scale counter 19 counted by a clock A is provided and a control by which a read-out period is used as an access period of a CPU is executed by a display control circuit 12. In such a way, the access period of a processing unit such as the CPU, etc., for executing a write control of an image memory is increased necessarily, and the processing efficiency is improved.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a digital character/graphic display that performs writing in blocks, such as a captain system terminal device or a character multiplex adapter device. The present invention relates to an image display control device applied to a system.

(Prior Art) Conventionally, for example, an image display control device called a cycle still type is configured as shown in FIG. is executed by the display control circuit 12.

In such a device, reading out data from the image memory 11 will be explained first.The display control circuit I2
Read address counter 1 according to control A from
3 outputs address data, this address data is sent to the image memory If via the address bus, and reading is performed from the address indicated by the address counter 13.

Here, as shown in FIG. 7, the clock pulse CP set by the display control circuit 12 is used as a display timing pulse, and one dot is displayed in one period of this clock pulse CP.

Now, a 16-bit data pulse is assumed here, and therefore, 16-bit data can be displayed by reading data from the image memory 11 once. Then, display is performed by repeating these 16 clocks as one unit.

Further, in this figure, ACC is an access period of the processing unit that accesses the image memory 11, that is, the CPU, and the CPU writes data to the image memory 11 during this period. Also CC5DP.

FG and BG are reading periods for four types of data necessary for character multiplex display control, and 16 bits of data are read out in one readout.

In short, 16 bits of data are read out during the period in which 16 clock pulses CP are generated and are sequentially displayed on the monitor display. While such a display operation is being performed, the CPU access period is set by utilizing the gap between the data read operations, and this is called a cycle still method.

Note that the above FG and BG data are color data, and F
G is the foreground color data, and BG is the background color data. Also, DP is dot pattern data, and when this dot pattern data is "1", it is the above FG, and when it is "0", it is B.
G color will be selected and displayed. CC is data for display control, and performs display control such as francing and concealment.

The control A from the display control circuit 12 is at a low level during the data read period, and during the low level period of the control A, the read address is output from the address counter 13. A read pulse and a data latch pulse are outputted from the display control 6 circuit 12 in synchronization with this address output. This data latch pulse is CC, DP, FGS
The signal is generated on four data lines corresponding to each of BG and supplied to the RGB decoder 14 for data latching.

Next, to explain the case where data is written from the CPU side, which is not shown in this figure, the CPU determines the state of the write busy signal of the display control circuit 12, and if it determines that it is in a writable state, The data to be written and the address data of the image memory 11 to which this data is to be written are set in the write data register 15 and the write address register 1B. Then, a write request is issued to the display control circuit 12. The display control circuit 12 that receives this write request sets the write busy signal to a write-disabled state, and remembers that the write request was received from the CPU until the next CPU access period.

When the CPU access period comes in this state, the display control circuit 12 sets the control B to low level as shown in FIG. They are output to the data bus and address bus, respectively, and at the same time, a write pulse is applied from the display control circuit 12 to the image memory 11, so that the write data is written to a predetermined address of the image memory 11. . After completing the write operation, the display control circuit 12 sets the write busy signal to enable writing, and waits for the next write request to arrive.

That is, in such a display control device, the access period of the processing unit that controls image writing is fixed, making it difficult to write into the image memory 11 quickly. Therefore, when write requests occur frequently, writing to the write register becomes busy, and the data processing efficiency of the processing unit decreases.

(Problem to be solved by the invention) This invention was made in view of the above points, and
By ensuring that the period during which processing units such as U can access is increased, the period for writing to the image memory is sufficiently expanded, and even when write requests to the image memory occur frequently, Display of an image suitable for the terminal of the Captain System or a character multiplex adapter, etc. to enable the processing unit to answer this: I;! It is intended to provide a lI device.

[Means for Solving the Problems] That is, in the image display control device according to the present invention, in the cycle still method, data written in blocks as data is One block is read from the image memory only once, and the data read at this time is stored in the auxiliary memory, so that the data is repeatedly read from the auxiliary memory from the next time onwards.

(Operation) Data that is written in block units is different from data in dot units, and is data that is given in units of rows of dots in a certain specified range.For example, in the case of color data in character multiplexing, , "The range of 4 x 42 dots will be given as one unit, and the same data for 4 rows will be written. Therefore, as described above, only 1 row of data will be written from the image memory. If this is read out, stored in the auxiliary memory, and read out repeatedly from now on, the readout period for three lines, which does not actually need to be read out from the image memory, can be used as an access period for the processing unit. As a result, the processing efficiency of the CPU, etc. can be effectively improved.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows its configuration, which includes an image memory 11 for storing image data to be displayed and a display control circuit 12. During a read operation, a control signal A is applied from the display control circuit 12 to the read address counter 13, and in response to this signal, the address counter 13 outputs address data.
The address data set to 3 is supplied to the image memory 11 via the address bus, and the data at the address corresponding to this address data is read out.

Then, in accordance with this timing, a read pulse is generated from the display control circuit 12, and the data at the address specified above is read out from the image memory 1. C
Data latch pulses corresponding to C, DP, FG, and BG are generated, and these latch pulses are applied to the RGB decoder 14.

Write data and write address data from the CPU side (not shown in the figure) are supplied to a write data register 15 and a write address register 16, respectively, via a data bus. The above data and address are set by a latch pulse given by the CPU. The address data set in the write address register 16 is supplied to the image memory 11 via the address bus, and the data set in the write data register 15 is supplied to the image memory 11 as write data via the data bus. The signal is supplied to the bus control circuit 17.

Now, if we consider the data that will be stored in the image memory 11, we will find that among this data, FG, BG,
, and CC data are “4×4” as shown in FIG.
” This is data written in blocks of dots.

First, if we consider how data is displayed in the conventional device shown in Figure 6, the RGB decoder of this device displays data in accordance with monitor scanning. I am trying to get the output to occur. Therefore, data is read from the memory 11 in a manner consistent with this, and data is read in the direction indicated by the arrow in FIG.

Here, in the apparatus shown in FIG. 6, data for 16 dots is read out at a time;
6 dots is 1 horizontal column of data in the block unit above.
This corresponds to 6 dots. Therefore, when writing data in blocks, it is necessary to read the same data four times (for four lines) in each block.

Therefore, if these four readings of each line are performed only once and the remaining three readings are omitted, the period in which the number of readings is reduced can be used as a period for CPU access. Therefore, the access period of the CPU is inevitably increased, and the processing efficiency of the CPU is improved.

Therefore, in the device of this embodiment, the data output from the bus control circuit 17 is supplied to the RGB decoder 14, and is also supplied to the line memory 18, which is used as an auxiliary memory. And this RGB
For example, 16 dots of data corresponding to the first row are written into the decoder 14 and line memory 18, respectively. The remaining read data on lines 2.3 and 4 are read out from the line memory 18 and used, and the data in blocks (FG, BG, CC) on lines 2.3 and 4 are read out from the line memory 18 and used. Control is executed by the display control circuit 12 so that the read period is used as an access period for the CPU.

For this reason, a quaternary counter 19 that counts with the clock A is provided corresponding to the display control circuit 12. This counter 19 determines which line is currently in the reading period, and as shown in FIG. 3, this clock A is constituted by a signal that rises before the start of reading of each line in the display area. .

In the display control circuit 12, this quaternary counter 19
When it is determined that it is the first row readout period, a readout operation using the conventional cycle still method is executed. That is, the fourth
The bus control circuit 17 is controlled by a bus control signal as shown in the figure.
and connects the bus when this control signal is at high level.

Then, the data read during the data read period is
It is coupled to the GB decoder 14 and line memory 18 so that data latch pulses are supplied to the RGB decoder 14 and line memory 18 at the same time.

Here, the address necessary for accessing the line memory 18 is given from an address counter 20, and this address counter ``20'' is configured to be operated by the display control circuit 12. Since the data required for this purpose only needs to be data in blocks, the memory control signal for this memory access and the clock B for counting the address counter 20 are output from the FG as shown in FIG. , B.G. and C.
This is only during the read period of C.

After reading the first line as described above, the second
．． Although the third and fourth rows are each read out, the operation seen from the RGB decoder 14 is the same during the readout period for each row. However, each block of CC5FGSBG data is read out not from the image memory 11 but from the line memory 18 that stores data for one row.

When reading data from the line memory 18, the bus control signal is set to a low level as shown in FIG. During this period, the control A signal and control B signal are set to low level as shown in FIG. 5, and the image memory 11 side is operated as a CPU access period. That is, CC, F
The G and BG periods are switched and used for access (ACC).

That is, a part of the data read period is returned to the CPU access period, and as a result, the CPU access period is increased, making it possible to improve the processing efficiency of the CPU.

[Effects of the Invention] As described above, according to the display control device according to the present invention, the access period of a processing unit such as a CPU that executes write control of the image memory is inevitably increased, and therefore the image memory The data writing speed is improved, and the display speed is also improved accordingly, so that the processing efficiency of the processing unit is effectively improved. In addition, up until now, we have assumed that the processing unit accesses are only in the writing state to the image memory, but if we take into account that this is just a readout, the frequency of processing unit accesses will be increased even further. As a result, its effects will be even more effective.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram for explaining an image display control device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the state of block data used in the device, and FIG.
The figure is a diagram explaining the state of the clock A of the quaternary counter in the above embodiment, FIG. 4 is a diagram explaining the state of the signal when reading the first row data of the block data in the above device, and FIG. 5 is the same. FIG. 6 is a circuit configuration diagram showing a conventional image display control device, and FIG. 7 is a signal waveform diagram explaining the operation of the conventional device. be. 11... Image memory, 12... Display control circuit, 13
...Read address counter, 14...RGB decoder, I5...Write data register, 16...
Write address register, 17... bus control circuit, 1
8... line memory, 19... quaternary counter, 20
...Address counter (for line memory). Applicant's agent Patent attorney Takehiko Suzue Figure 2 ACCCCACCDP ACCFG ACC8G
Gro・ng B Figure 4 Figure 5

Claims (1)

[Claims] Between an image memory that stores image data including block data written in blocks each consisting of a plurality of pixels, and a period of reading out image data from this image memory, the image memory a processing unit that performs processing control to access the image memory; a memory control means that reads the block data written in the image memory once within the block; and a memory control means that reads the block data written in the image memory once within the block; The apparatus comprises an auxiliary memory for memory setting, and means for repeatedly reading and controlling block data stored in the auxiliary memory a plurality of times, such that a period of reading data from the auxiliary memory is an access period of the processing unit. A display control device characterized by: