JPH08115594A - Data readout, transferring and refreshing method for dual port drams - Google Patents

Abstract

PURPOSE: To shorten the waiting time of a reading or a writing request from a CPU by dividing a frame buffer memory into plural banks for a data readout and transferring cycle and for a refreshing cycle and providing banks in the memory. CONSTITUTION: A prescribed number of dual port DRAMs constituting a frame buffer memory 32 storing displaying picture data are divided into two banks of #1 and #2. A data readout transferring cycle with respect to dual port DRAMs of the divided #1 bank and a refreshing cycle with respect to dual port DRAMs of the divided #2 bank are simultaneously performed. Thus, since the time for only the refreshing cycle conventionally executed in an independent time is unnecessitated and the reading or the writing request from the CPU is made not be waited for a long time, the working rate of the CPU is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual-port DRAM (Dual-Port Dynamic RA) which constitutes a frame buffer memory for storing display image data.
M) method of data read transfer and refresh.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional image display data reading device. In FIG. 5, reference numeral 1 is a CPU, 2 is a memory including a ROM for storing a control program and a RAM for temporarily storing data, and 3 is a CRT display data control unit, which internally has a frame memory control unit 31, a frame buffer memory 32. , And a D / A converter 33. 4 is C
The RT display 5 is a connection bus including an address bus and a data bus. The frame buffer memory 32 is usually composed of a dual port DRAM for displaying image data, and the number of display pixels (pixels) of the CRT display 4 and the number of bits for displaying one pixel (in the case of displaying a pixel in black and white shading This bit number serves as information indicating the black and white stage), D
A required number of dual port DRAMs are used according to the capacity of the RAM and the like.

FIG. 6 is a diagram showing a configuration example of a general dual-port DRAM, which has two input / output ports of A port and B port. The port A in FIG. 6 is a random access port, and the CPU can
It is possible to randomly access the memory cells in the RAM and write or read data in 1-bit units. Port B in FIG. 6 is a serial access port,
For example, the CRT display data collectively read from the DRAM is serially transferred through this B port. The reading and transfer of this serial data are performed by the following two steps. Each DRAM is assumed to be composed of N rows × M columns of memory cells.

In the first "data read transfer" step, D
One row of N rows is decoded by the row data input to the row decoder of the RAM, and the data in the M column of the corresponding row is collectively read and transferred to the serial shift register.
In the next "data serial transfer" step, a desired frequency (for example, a frequency corresponding to a time obtained by dividing one horizontal scanning time of the CRT display for displaying the serial transfer data by the number of horizontal display pixels) is stored in the serial shift register. A clock signal is supplied, and the data stored in the serial shift register is serially transferred bit by bit from the B port to the outside.

Although the serial transfer data of the DRAM of FIG. 6 is 1 bit at a time, n DRAMs are provided in parallel (as indicated by # 1, # 2, ... #n in the depth direction of the drawing). As a result, n-bit serial data can be obtained at the same time. Thus, the advantage of the dual port DRAM having two ports is that when the serial data for CRT display is read out and transferred, the next B port is used after the first "data read transfer" step is completed. Even during the "data serial transfer" process, the CPU can write and read data by accessing an arbitrary memory cell in the DRAM using the A port.

Now, the frame buffer memory 32 shown in FIG.
Each dual-port DRAM in the
It is assumed that the image data to be displayed on the display unit 4 has been written. When the "data read transfer" step, which is a batch read of the CRT display data, is performed, data of one scanning line (one raster) or more of the normal CRT display 4 is output from the corresponding dual port DRAM. It is read and transferred to the serial shift register in the DRAM. Then, in the next "data serial transfer" step, a clock signal having a frequency matching the scanning timing of the CRT display 4 is supplied to the serial shift register, and the serial data synchronized with the clock signal is transferred from the serial shift register to D / The data is sequentially transferred to the A converter 33.

In the D / A converter 33, data for one pixel is usually provided for each clock signal (data of a plurality of bits).
The D / A converter 33 sequentially converts the input data into an analog voltage signal and sequentially supplies it to the CRT display 4 as an analog luminance signal for image display. When the steps of "data read transmission" and "data serial transfer" for one raster are completed in this way, usually the scanning blanking period is paused, and the above two steps for the next raster are repeated again.

Each dual port DRAM used in the frame buffer memory 32 has a "data read transfer" and a "data serial transfer" for the CRT display.
Besides, the stored data may be destroyed unless refreshed within the specified time. In addition, in the case of having a self-refresh function, even if the address signal for designating a row is not supplied, a fixed number of times (for example, 8 mse
Refreshing may be performed 512 times within c. Therefore, the dual-port DRAM that constitutes the frame buffer memory 32 needs to perform the following three operations, and their requirements conflict with each other in terms of time. A, "Data read transfer" is performed to output CRT display data (note that "Data serial transfer is in progress")
Can access the DRAM by another operation. ), B, refreshing is performed to save the stored data within the specified time, and C, and further processing is performed according to a read or write request from the CPU 1.

For this reason, conventionally, the following priorities have generally been set to process three competing requests in the order of the priorities. Priority 1: Request for data read transfer (in order not to miss display on CRT display), Priority 2: Refresh request (for holding data stored in DRAM), Priority 3: Read or write request from CPU,

[0010]

However, in the contention processing method based on the priority order for the frame buffer memory using the dual port DRAM described above, when the read or write request from the CPU is a data read transfer or refresh request. Has a problem that the operating efficiency of the CPU is greatly reduced because the requests are kept waiting until they are processed.

[0011]

A data read transfer and refresh method for a dual-port DRAM according to the present invention comprises:
A predetermined number of dual-port DRAMs forming a frame buffer memory for storing display image data are divided into a plurality of banks, and a data read / transfer cycle for the divided one-port dual-port DRAMs and dual-ports of other banks The refresh cycle for the DRAM is simultaneously performed.

[0012]

According to the present invention, the predetermined number of dual port DRAMs forming the frame buffer memory for storing the image data for display are divided into a plurality of banks, and the data read / transfer for the divided one port dual port DRAMs. Since the refresh cycle for the dual-port DRAMs of other banks is executed at the same time as the cycle is being executed, the time only for the refresh cycle, which was conventionally executed at an independent time, is unnecessary, and the read from the CPU Alternatively, the write request is not kept waiting for a long time, and the operating efficiency of the CPU is improved.

[0013]

1 is a diagram showing a configuration example of a CRT display data control unit according to the present invention, FIG. 2 is a diagram explaining a display example of a CRT screen by two banks in FIG. 1, and FIG. FIG. 6 is a state machine transition diagram of the frame memory control unit according to the present invention, and FIG. 4 is a time chart of each control signal for the frame memory buffer according to the present invention. First of all, the gist of the present invention will be described.
Is divided into a plurality of banks, and the "data read transfer cycle" for the dual port DRAM of one bank and the dual port DR of the other banks.
The "refresh cycle" for the AM is performed simultaneously (in parallel).

The present invention will be described in detail below with reference to FIGS. The "data read / transfer cycle" for CRT display is a cycle at a certain timing unique to each device, depending on the specifications of the CRT display 4 (the number of display pixels, horizontal and vertical sync frequencies, etc.) and the configuration of the frame buffer memory 32. Will be needed. Therefore, the frame buffer memory is divided into a plurality of banks, and a control signal is connected to each bank so that each bank can be individually controlled. In the example of FIG. 1, the frame buffer memory 32 is divided into two banks, # 1 bank and # 2 bank, and the frame memory control unit 31
Therefore, the # 1 control line and the # 2 control line are connected to each bank. In addition, FIG. 2 shows an example of the display area of the CRT screen by the two banks in FIG.
The number of display rasters (number of horizontal scanning lines) of the RT display is 10
In the case of 24 lines, the output data of the # 1 bank is displayed on the 512 rasters in the upper half of the screen, and the 5th raster in the lower half of the screen is displayed.
It is shown that the output data of the # 2 bank is displayed on the 12 raster lines.

While the "data read transfer cycle" is being performed on one bank (for example, the # 1 bank) of the frame buffer memory 32, the DRAM of the other bank (the # 2 bank in this example) is simultaneously written to the other bank. Each control signal is controlled so that a "refresh cycle" is performed. In this way, two operations of "data read transfer" of one bank and "refresh" of another bank are simultaneously performed. When deciding the number of banks n of this frame buffer memory, be careful of each dual port DRAM.
Since the maximum allowable cycle T of refreshing and the number of times x are determined, it is necessary to complete the number of times of refreshing x within this refresh cycle T. For example, (1) below
The number of banks n may be determined so as to satisfy the formula.

[0016]

[Equation 1]

The meaning of each symbol in the equation (1) is as follows (see each time in FIG. 2). Vp: CRT vertical sync signal cycle (time) Vdisp: CRT vertical display time (excluding non-display time) n: Number of banks of memory x: Number of refreshes within a specified cycle of DRAM (512 times in the above example) ) T: DRAM refresh cycle (8 m in the above example)
s) R: Number of display vertical rasters of CRT (display section only, 1024 in the above example) Rall: Total number of vertical rasters of CRT That is, refresh of DRAM performed in another bank during data read transfer of one bank is: It is necessary to satisfy the cycle T and the number of times x specified in the DRAM.

From the state machine transition diagram of the frame memory controller of FIG. 3 and the time chart of the control signal of FIG.
Detailed operations of the "data read transfer cycle" and the "refresh cycle" will be described. In "idle" of FIG. 3, the frame memory control unit is in the idle state, and when there is a data read transfer request, it immediately moves to "dtras0" (FIG. 4).
(See (a)). In "dtras0", assert RAS (row active by row address strobe signal) of the bank that has requested the data read transfer.
At the same time, CAS (row active by a column address strobe signal) of another bank is asserted. 4C and 4F show a state in which the RAS1 of the # 1 bank goes low and the CAS2 of the # 2 bank simultaneously changes to low level. Next, the state transits to "dtrasl" and the state of "dtras1" is held for a certain period of time.

Then, the transition to "dtcas" is made, the CAS of the bank for which the data read transfer is requested is asserted, and at the same time, the RAS of the other bank is asserted. (E) of FIG.
And (d) CAS1 of # 1 bank becomes low level,
At the same time, the state in which the RAS2 of the # 2 bank changes to the low level is shown. Transition to the next "swaprow", and the RAS, C of the bank for which the data read transfer request has been made.
AS is negated, and at the same time, RAS and CAS of other banks are also negated. Then "dt
Pch0 ", all control signals related to data read transfer and refresh (except for CPU access) are set to high level, and the state returns to" idle ".

That is, the state of the frame memory control section is "d".
, rdt0 ”, ...,“ dtpch0 ”, and C
At the same time as controlling the control signal to perform the data read transfer of the bank which has requested the RT display data, all the other banks are "CAS before RAS refresh".
The control signal is controlled so that

The "CAS before RAS refresh" is a refresh method suitable for the DRAM self-refresh, and in the example of the # 2 bank which is refreshed in FIG. 4, (f) and (d) in FIG. ), CAS2 becomes low level (enable) at a timing earlier than RAS2, and then R
If there is a high level state of AS2, this self refresh starts. With this refresh method, the external address input is not required, and the row specified by the internally generated refresh address is refreshed. Therefore, in the present invention, when the data read / transfer cycle is performed in one bank and the refresh cycle is performed in the other banks, the case where "CAS before RAS refresh" is used in the example of FIG. 4 as a convenient refresh method. Is shown. However, the refresh method of the present invention is not limited to this method, and the present invention can be implemented by a refresh method other than the “CAS before RAS refresh”.

Dual port DRA in this embodiment
The refresh of M is performed 512 times within a period of 8 ms. And the request for "data read transfer" is
It is performed for each raster of the CRT display device, and data for one raster is read and transferred to the serial shift register for each request. In the example of FIG. 2, the CRT screen is 1054 raster including the display unit 1024 raster and the non-display unit. Data read transfer cycle and refresh cycle of FIG. 4 (from “idle” to “dtpc0” in the figure)
Is a processing time for one raster, and when this cycle ends and the next "idle" state is entered, the CPU access period becomes possible. During this period, the CPU can access the DRAM via the random access port (A port) to write and read data. Then, a request for data read transfer for the next raster is generated again.

The above operation will be specifically described. # 1 in FIG. 2
In the bank and # 2 bank display areas, at the same time as the first raster data read transfer of the # 1 bank,
The second refresh is performed. CP for a certain period after that
After the U accessible period, the second refresh of the # 2 bank is performed simultaneously with the data read transfer of the second raster of the # 1 bank. After that, the CPU accessible period starts again. The same operation is repeated thereafter and the fifth bank of the # 1 bank is
The data read transfer of 12 rasters and the 512th refresh of the # 2 bank are performed. The time from the first refresh to the completion of the 512th refresh is 8 msec or less. Then, this time, the first refresh of the # 1 bank 1 is performed at the same time as the first raster data read transfer of the # 2 bank, and then the CPU accessible period starts. By repeating this operation, the 512th refresh of the # 1 bank is performed at the same time as the 512th raster data read transfer of the # 2 bank.

After that, in the non-display portion (29 raster sections), the data read transfer is not performed, so the refresh is not performed. When it is preferable to perform the data read transfer of the corresponding scan line earlier than the timing when the horizontal scanning of the CRT display is started, the first bank of the next # 1 bank is selected.
Only the raster data read transfer may be performed once in the non-display portion. Thereafter, the first refresh of the # 2 bank is performed at the same time as the first raster data read transfer of the # 1 bank. After that, it repeats similarly.

As described above, according to the present invention, the dual port DRAM which constitutes the frame buffer memory is divided into a plurality of banks, and the other banks are set at the time when the data read / transfer cycle is being performed for the one bank. However, since the refresh cycle is performed in parallel, the time required only for the refresh cycle as in the past has been eliminated. When the period of the data read transfer cycle and the refresh cycle for each raster ends, there is always a CPU accessible period. Therefore, the read or write request from the CPU is not kept waiting for a long time, and the operating efficiency of the CPU is improved.

In the above embodiment, an example in which data for one raster of the display is read and transferred to the serial shift register by data read and transfer to the dual port DRAM of one bank of the plurality of banks will be described. However, the present invention is not limited to this,
Data for one raster or more, for example, data for two rasters may be read and transferred. In the present invention, the number of repetitions of the data read / transfer cycle of the one bank and the refresh cycle of the other banks is the required number of refreshes defined in the dual port DRAM (512 in the embodiment).
And the time required to complete the number of repetitions of each cycle is set to be equal to or shorter than the refresh cycle (8 ms in the embodiment) specified for the dual port DRAM. Just do it.

[0027]

As described above, according to the present invention, a predetermined number of dual port DRAMs forming a frame buffer memory for storing display image data are divided into a plurality of banks, and the divided one bank is dual. Port DRAM
Since the data read / transfer cycle for the memory and the refresh cycle for the dual-port DRAMs of the other banks are performed at the same time, the time required only for the refresh cycle as in the conventional case is unnecessary, and the read or write request from the CPU is long. There is no need to wait for time, and the operating efficiency of the CPU is greatly improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a CRT display data control unit according to the present invention.

FIG. 2 is a diagram illustrating a display example of a CRT screen by the two banks in FIG.

FIG. 3 is a transition diagram of a state machine of a frame memory control unit according to the present invention.

FIG. 4 is a time chart of each control signal for the frame memory buffer according to the present invention.

FIG. 5 is a configuration diagram of a conventional image display data reading device.

FIG. 6 is a diagram showing a configuration example of a general dual port DRAM.

[Explanation of symbols]

 1 CPU 2 memory 3 CRT display data control unit 4 CRT display unit 5 connection bus 31 frame memory control unit 32 frame buffer memory 33 D / A converter

Claims (4)

[Claims] 1. A predetermined number of dual-port DRAs forming a frame buffer memory for storing display image data.
Data of a dual port DRAM, characterized in that M is divided into a plurality of banks, and a data read / transfer cycle for the dual port DRAM of one divided bank and a refresh cycle for the dual port DRAMs of other banks are simultaneously performed. Read transfer and refresh method. 2. The CPU sets an arbitrary memory cell of a dual port DRAM for a period from the end of both the data read transfer cycle and the refresh cycle to the start of the next data read transfer cycle and the refresh cycle. 2. The dual-port DRA according to claim 1, wherein a period during which data can be written or read by accessing the dual port DRA is set.
M data read transfer and refresh method. 3. The dual bank DR of the one bank
The data read of the dual port DRAM according to claim 1 or 2, wherein at least one raster of image data of display image data is read and transferred to a serial shift register in the corresponding dual port DRAM in a data read / transfer cycle for AM. Transfer and refresh method. 4. The number of repetitions of the data read transfer cycle and the refresh cycle is equal to the required number of refreshes specified in the dual port DRAM, and the time required to complete the number of repetitions of each cycle is 2. The refresh cycle is set to be equal to or shorter than the refresh cycle specified for the dual port DRAM.
A method of data read transfer and refresh of a dual port DRAM according to claim 3.