JPH0631927B2 - Display data transfer method and display system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display system using a dual port memory, and more particularly, to a spray system having a drawing means for drawing asynchronously with display reading on a display device and the same. Display data transfer method.

[Conventional technology]

Due to recent advances in hardware technology and software technology, a man-machine interface mainly for displaying graphics has been adopted for an information processing apparatus represented by a personal computer or a workstation. One of the typical ones is the man-machine interface called the window operation environment. The window operation environment is one in which one or more rectangular windows called windows are displayed on a display and an application program is operated in each window. Since all the characters and figures displayed in this window are drawn by graphics, it is essential to speed up the graphics drawing process in order to improve the usability for the user. In the present specification, the above-mentioned devices are generically referred to as a display system or a display device. In a display device that mainly draws characters and figures using such graphics, how to increase the ratio of access time for drawing to a display memory (frame buffer or VRAM) that stores display data such as characters and figures Is the key to improving performance. That is, in the raster scan type display device, since the stored contents of the frame buffer must be read out and sent to the display device for display, it is necessary to constantly perform read access for display to the frame buffer. This read operation is hereinafter referred to as display read. If it takes time to read the display, the drawing access is suppressed and the drawing speed of the graphics is relatively reduced. Specifically, in order to draw in the frame buffer by the CPU or the like during the display period, the display read cycle and the drawing access cycle are allocated in a time-sharing manner, or the display read cycle and the drawing access cycle are not performed, for example, horizontal and vertical return. Drawing access was performed after waiting for the line period. That is, the access to the frame buffer is dominated by the display reading, and the access cycle for drawing is limited to a specific time slot (between certain fixed times). For the above reasons, how to increase the ratio of accessible time for drawing to the frame buffer is a key point for performance improvement.

As a technique for solving this problem, Japanese Patent Laid-Open No. 59-1
Japanese Laid-Open Patent Publication No. 31979 or Japanese Patent Laid-Open No. 61-11791 discloses a dual port memory and a computer system using the dual port memory. This dual port memory is equipped with a random access memory part (random access memory part) and a serial access memory part (serial access memory part). The random access memory part has memory cells arranged in rows and columns as in a normal dynamic memory. The serial access memory unit is configured by a matrix of (columns), and the bits of the columns included in one row are so that the data for one row of the random access memory unit can be copied in one memory cycle called data transfer. It has the capacity to store several minutes of data. Then, paying attention to the fact that the read access for display may read the display data stored in the random access memory unit in the order of the addresses, the contents once transferred to the serial access memory unit do not need to be given a read address. , Can be sequentially read by simply giving a read clock. Further, the serial access memory unit is composed of a shift register, and the first read position can be changed to some extent by selecting a plurality of taps provided in this shift register. By using this dual-port memory as a frame buffer, if display data is first transferred to the serial access memory unit and read out, the data transfer cycle from the random access memory unit to the serial access memory unit and the refresh cycle of the memory can be performed. All the remaining periods other than the required period can be accessed for drawing, and the drawing process can be speeded up.

The dual port memory is of a system in which a plurality of taps provided in the shift register constituting the serial access memory unit are selected as output signals, so that there is a limitation in the designation of the read position. On the other hand, JP-A-6
The dual port memory disclosed in 0-72020 is capable of data transfer such that reading is started from an arbitrary position of the serial access memory unit so as to be suitable for scroll processing. This is a memory suitable for moving the display area 54-a on the frame buffer 10 as shown in FIG. 6 (b), for example.

[Problems to be solved by the invention]

In the above-mentioned prior art, only the case where the memory width in the horizontal direction (or the number of pixels forming the bitmap) is a power of 2 has been considered. The case where the value of the power of 2 is 512 pixels or 1024 pixels is described. On the other hand, the number of pixels in the horizontal direction of the display device is generally not a power of 2, and often has a resolution of, for example, 640 pixels or 1120 pixels. In addition, in the conventional apparatus, when the unused area as shown in FIG. 6 (b) is not provided in the frame buffer, and the frame buffer is effectively used with the bitmap configuration as shown in FIG. 6 (a). There are many. This will be specifically described. In FIG. 6A, the memory width 400 and the display area 54-a are both 640 pixels, and the 641st pixel of the frame buffer corresponds to the first pixel of the next horizontal line. It is possible that Further, in FIG. 6B, when the memory width 400 is, for example, 1024 pixels and the display area 54-a is 640 pixels, the 641st pixel to the 102nd pixel of the frame buffer are displayed.
Up to the 4th pixel is an unused area.

One of the reasons why the bitmap structure as shown in FIG. 6 (a) is often used is that the frame buffer can be effectively used, but the biggest reason is that the compatibility with the conventional device is maintained. Is. In other words, hardware compatibility is essential in order to improve performance without changing the vast amount of software assets that have been developed and operated so far. Since the memory device for the frame buffer is relatively expensive in the conventional device, the bitmap structure as shown in FIG. 6 (a) is adopted in order to keep the capacity to the minimum necessary and reduce the cost of the entire device. However, even if the increase in the memory cost due to the decrease in the semiconductor manufacturing cost and the provision of the unused area as shown in FIG. 6 (b) does not affect the cost of the entire device, the compatibility is still maintained. Therefore, the bitmap structure as shown in FIG. 6 (a) is required.

Now, when using dynamic memory for the frame buffer for display, not limited to dual port memory,
In order to realize the bit map configuration as shown in FIG. 6A, it is necessary to store the display data for one horizontal line in a plurality of rows of the random access memory unit. This is because the number of bits in the column direction of these memory elements is almost always a power of 2, and as described above, the number of pixels in the horizontal direction (display area 54-a in FIG. 6) of the display device is 640, Generally, it is not a power of 2 in many cases such as 1120. Therefore, if the number of bits of a column included in one row is n, and the number of bits per memory cell array required to perform horizontal display is m, then n
Is not a multiple of m, the display data is written over a plurality of rows of the random access memory section depending on the line. Since it is assumed here that a dual port memory is used for the frame buffer, a data transfer cycle called real-time data transfer is required to read the data stored in such a plurality of rows. Real-time data transfer is performed when the display data currently transferred to the serial access memory section is completed during display readout, and the subsequent display data stored in the next row is displayed and read. It is a control to transfer data to the serial access memory unit without any break.

First, the above-mentioned Japanese Patent Laid-Open Nos. 59-131979 and 6
Since the prior arts disclosed in JP-A-11-11791 and JP-A-60-72020 do not have means for performing real-time data transfer, only real-time data transfer is unnecessary and only when the memory width is a power of 2. Was being discussed.

By the way, a raster scan type display device has two scanning methods, a non-interlace method and an interlace method. The non-interlaced method is a method for displaying data of one screen by scanning the horizontal scanning in order from top to bottom. The interlaced method is a horizontal scanning performed every other line like television broadcasting, and an even number. This is a method of displaying one screen (one frame) by two vertical scans of a field including only lines and a field including only odd lines. The interlace method is suitable for constructing a low-cost system because the operating frequency of the display device can be lower than that of the non-interlace method, and is often used in personal computers and the like. However, when a frame buffer is constructed using a dual port memory in such an interlace type display device, a problem occurs. As described above, in the interlaced method, the display data for every other line must be read out to the display unit, so that the storage addresses of the data to be displayed become discontinuous (interleaved) every horizontal scanning, and this is corrected. Therefore, one data transfer is always required at the beginning of horizontal scanning.

Therefore, a first object of the present invention is to use a dual port memory as a frame buffer and to perform real-time data transfer so that control can be performed even when the memory width is other than a power of 2, in the serial access memory unit. It is an object of the present invention to provide a display data transfer method capable of generating a timing for performing the real-time data transfer without counting the remaining data number.

A second object of the present invention is to provide a display data transfer system in which a dual port memory can be used as a frame buffer even in the case of interlaced scanning.

A third object of the present invention is to use a dual port memory as a frame buffer and to perform real-time data transfer for realizing a case where the memory width is other than a power of 2, when the number of remaining data in the serial access memory unit is increased. It is an object of the present invention to provide a display system capable of generating the timing of performing the real-time data transfer without counting the number of times.

A fourth object of the present invention is to provide a display system capable of using a dual port memory as a frame buffer even in the case of interlaced scanning.

[Means for solving problems]

A first object of the present invention is to decode that a column address signal of the dual port memory has reached a predetermined value at the time of read access for display to the dual port memory, and to decode the random access memory according to the decoding result. This is accomplished by generating a timing signal for the first data transfer from the section to the serial access memory section.

The second object of the present invention is achieved by, in addition to the means for the first object, generating a second data transfer timing in response to a synchronizing signal for display prior to each horizontal scanning.

Further, a third object of the present invention is to provide a dual display device in which display data accumulated in a plurality of rows of a random access memory unit corresponding to a scanning line of the display unit are transferred to the display unit in real time when the display data is read. Achieved by providing means for decoding that the column address signal of the port memory has reached a predetermined value and generating a first timing signal for data transfer from the random access memory unit to the serial access memory unit. To be done.

A fourth object of the present invention is, in addition to the means for the third object, a second object for data transfer from the random access memory unit to the serial access memory unit in accordance with the synchronization signal group of the display control means. This is achieved by providing means for generating the timing signal.

[Action]

The display address output by the display controller or display control means is constantly updated (counted up) during the display period.
Has been done. Since the update of the display address and the reading of the serial access memory unit are synchronized, it is possible to detect how many times the reading is required for real-time data transfer without using other means such as a counter. . That is, real-time data transfer is necessary because of the display addresses output by the display controller,
This is when the address of the part corresponding to the column address of the dual port memory overflows. Therefore, read access for display, that is, when the column address signal of the dual port memory output by the display controller reaches a predetermined value when reading the display, it is decoded, and when the column address signal reaches a predetermined value, the random access memory Unit to the serial access memory unit for generating a first data transfer timing signal, and in accordance with the timing signal, data is transferred from the row following the first row to the serial access memory unit, thereby performing real-time data transfer. To do.

Now, it is assumed that display data corresponding to one scanning line of the display is stored in a plurality of rows of the random access memory portion of the dual port memory. In the case of a raster scan type display device, the display is performed in the full screen by repeating scanning in horizontal units (horizontal scanning) in the vertical direction. There are types of this vertical scanning system such as interlace (interlaced scanning) and non-interlace, but here, the two are not particularly distinguished and attention is paid to horizontal scanning of one line. At the beginning of this horizontal scanning, it is necessary to first transfer the display data at the beginning of the horizontal scanning to the serial access memory unit. For this, a plurality of rows (rows) of the random access memory unit in which the display data corresponding to the one scanning line are accumulated by generating the second data transfer timing in response to the synchronizing signal for display. The display data can be transferred to the serial access memory unit by specifying the column position from the first row of the above. As the data transfer address at this time, of the display addresses output by the display controller, the address of the horizontal display start position may be used as it is. Here, the lower part of the display address output by the display controller corresponds to the column address, and the upper part corresponds to the row address. As a result, the display data is sequentially output according to the read clock of the serial access memory unit, and the display associated with the horizontal scanning can be started regardless of the interlace system or the non-interlace system. After that, when real-time data transfer is required as described above, the fact that the column address signal of the dual port memory has reached a predetermined value is decoded, and the random access memory unit transfers to the serial access memory unit according to the decoding result. Real-time data transfer is performed by generating a data transfer timing signal of 1.

Since the real-time data transfer is performed according to the above-described operation principle, the display system using this data transfer method can use the dual port memory even when the memory width is a frame buffer configuration other than a power of 2.

In accordance with the above-described operation principle, the display system using this data transfer method can be used for the dual port memory associated with each horizontal scanning regardless of whether the interlace method is used or the memory buffer has a frame buffer configuration other than a power of 2. You can control.

〔Example〕

The first embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a schematic configuration diagram of a display device using the present invention. In the figure, 50 is a microprocessor (hereinafter referred to as CPU) for drawing and the like, 1 is a display controller (DC
, 10 is a frame buffer with dual port memory (hereinafter referred to as VRAM), 3 is a data transfer timing generation circuit (hereinafter referred to as DTX-DET), 2 is a CPU 50 prior to the timing signal generated by the DTX-DET 3. Signal generation circuit for prohibiting access start to VRAM10 (hereinafter AD-D
ET), 52 is a memory access interface circuit (hereinafter referred to as Mi) for accessing the VRAM 10 of the CPU 50.
/ F), 8 is a circuit (hereinafter referred to as ARB) that arbitrates the access right of VRAM 10 by receiving the output signals of AD-DET2, DTX-DET3, Mi / F52, and 9 is the data transfer by the output 190 of ARB8. Circuit that creates control signals for dual port memory necessary for reading and writing memory and memory (hereinafter referred to as T-GEN), 11D
Display address 100 output from C1 and address bus 1 of CPU50
Address multiplexer (hereinafter referred to as MPX) that switches 10 to output address 240 to VRAM 10, 51 is a clock generation circuit for display (hereinafter referred to as CLK), 210 is a data bus of CPU 50, and 230 is a serial access memory of VRAM 10. Read data bus, 54 is a display (DISP), 53 is a display interface circuit (Di / F) that converts the display data of the read data bus 230 into a signal suitable for DISP 54, and 270 is ARB
A signal for switching MPX11 by arbitration of 8, 250 is an access request signal from CPU 50, 260 is a permission signal for access request signal 250, 220 is a serial read clock of VRAM 10, and 2
90 is a DC1 timing clock, 280 is a CPU 50 control bus, 120 is a DC1 display control signal, 150 is an access start prohibition signal, and 160 is a data transfer timing signal.

The detailed circuits of ARB9 and T.GEN10 will be described later.

First, the data transfer of the VRAM 10 will be outlined with reference to FIG.
FIG. 5 shows the internal structure of the dual port memory which constitutes the VRAM 10. 320 is a random access memory unit (hereinafter referred to as RAM
330) is a serial access memory unit (hereinafter referred to as SAM).
It is referred to as a section). The RAM section 320 is composed of 2 ^m (m is a natural number) rows 310 and 2 ⁿ (n is a natural number) bit column 300 for each row 310, and comprises a total of 2 _{(m + n)} memory cells. The SAM unit 330 has a capacity capable of accommodating the bit number for one row 310 (2 ⁿ bits). Data transfer means transferring data of a specific row 310 to the SAM unit 330. Specifically, for example, the address line 240 given to the VRAM 10
Specifies a specific row 350 (i-th), then specifies a column position 360 at which to start serial reading, and gives the timing of data transfer by the access control line signal (ACS) 200. Are all transferred to the SAM section 330 as indicated by the arrow 340, and then a pulse is given by the serial read clock (SRCK) 220 to sequentially read the data from the jth column position.
It is output to the read data bus 230.

Next, the operation of the present invention will be described with reference to FIG. Fig. 3
In (a) and (b), C indicates an access start prohibition signal. In the figure, the prohibition signal C is valid when it is at "1" level. In FIG. 7A, access A for drawing starts at time α before time γ when the inhibition signal C becomes valid. In this case, the time interval t between the time γ when the inhibit signal C becomes valid and the start time β of the data transfer cycle.
_{If cyc} (max) is set to be equal to or longer than the maximum value that the cycle time t _cyc of the access A for drawing can take, that is, if t _cyc (max) ≧ t _cyc , then FIG. In the case of), the access A for drawing is surely completed by the start time β of the data transfer.

FIG. 6B shows a case where a request for access A for drawing occurs at time α after the inhibition signal C becomes valid and before the data transfer cycle B starts. The conventional example under the same conditions as this corresponds to (c) in FIG. In the case of FIG. 2C, the access A for drawing starts at the time α, and the cycle of the data transfer B occurring at the time β cannot be started normally, that is, the normal display operation is not guaranteed. On the other hand, in FIG. 3B, since the access start prohibition signal C is valid at the time α, the start of the access A for drawing is delayed until the end time α ′ of the data transfer cycle B. Be done. As a result, data transfer cycle B
Starts exactly at time β and access A for drawing
Can be done normally.

Here, the access start prohibition signal is described as positive logic, but it may be configured with negative logic, contrary to the figure. Further, in the shaded portion of the prohibition signal C in FIG. 3, the prohibition signal may be valid or invalid. That is, the data transfer cycle B is already being executed in this shaded area, and ARB 8 in FIG. 1 is set so that no other access is allowed until this cycle is completed.
Should be configured. In this case, the drawing access request generated at any time corresponding to the shaded area in FIG.
The operation ends normally with the same operation as described with reference to FIG.

As explained above, according to the present invention, in FIG.
-By providing DET2, CPU50 and DC1 can be operated completely asynchronously.

Next, the relationship between AD-DET2, DTX-DET3 and the display control signal 120 from DC1, which is a main part of the present invention, will be described in detail.

FIG. 4 shows the correlation between the display screen and the timing of various signals when a raster scan type CRT display is used for DISP54. 54-a indicates a display area in which a picture or a character is actually displayed. 120-a is a horizontal synchronizing signal, 120-b is a display enable signal indicating a display area, which is DC1 in FIG.
Are included in the display control signal 120 from. 160 is DTX-DET3
The data transfer timing signal output by AD-DET2, 150 is the access start prohibition signal output by AD-DET2, and 100 is the output of DC1
This is a display address signal of VRAM10. In order to display with VRAM10 which uses dual port memory, it is necessary to perform SA from the initial setting and RAM section 320 (Fig. 5) inside dual port memory.
Data must be transferred in advance to the M section (Fig. 5). Data transfer for this initialization is DC
Time 1'in FIG. 4 in which 1 outputs the display address at the beginning of each horizontal scan to VRAM 10 to start display.
Must be performed. Display enable signal 120-
Time b'can be detected by using b. However, with this, it is not possible to generate the time γ ′ which is earlier than the time β ′ by t _cyc (max) in FIG.

Generally, in a display device, the time interval from the time ε when the horizontal synchronizing signal 120-a becomes valid or the time ε ′ when it becomes invalid to the time β ′ at which the first display address for each horizontal scanning is output is specified by the designer. Can be uniquely determined based on. That is, the designer knows the time from the time ε or ε ′ to the time γ ′ and the time β ′. Therefore, the means for delaying the horizontal synchronization signal 120-a by a certain time is combined with the data transfer timing signal 160 and access start. The prohibition signal 150 can be created. It should be noted that AD-DET2 and DTX-DET3 can be configured by a person skilled in the art using a shift register, a counter, or the like, and thus detailed description thereof is omitted.

FIG. 6 shows the correspondence by arranging the VRAMs 10 two-dimensionally so as to fit the display area 54-a. Display readout is performed horizontally from left to right toward the display area 54-a.
The scanning is performed from the upper side to the lower side.

In the figure (a), the memory width of the VRAM 10 in the horizontal direction is the display area 54-a.
8B, the memory width of the VRAM 10 in the horizontal direction is wider than the display area 54-a. If the interlaced scanning is not performed in FIG. 4A (non-interlace) and the serial read clock 220 in FIG. 1 is stopped during the non-display period _tr in FIG. The data transfer may be performed once at the time of scanning one screen (one frame) at the upper left corner of FIG. 6 (a). In other cases, data transfer for initial setting of the dual port memory needs to be performed every horizontal scanning.

In either of the above cases, the horizontal synchronizing signal 120-a or a signal similar thereto is input, and it can be generated using AD-DET2 and DTX-DET3 configured using a delay circuit, a shift register, a counter, or the like.

FIG. 7 shows still another embodiment of the present invention. The operation of this embodiment will be described with reference to FIGS. Further, the difference between FIG. 7 and the embodiment (FIG. 1) is that AD-DET in FIG.
2, DTX-DET3 timing generation signal is only the synchronization signal 120 generated by DC1, whereas in Figure 7 D
This is because AD-DET2 'and DTX-DET3', which are based on the display address 100 where C1 is generated, are added as timing generation sources.

As outlined at the outset, FIG. 5 is an illustration of a dual port memory that comprises the VRAM 10. RAM described above
The section 320 and the SAM section 330 correspond to one data line of the data bus 210. Therefore, if the data bus is 8 bits, 8 pairs,
In the case of 16 bits, 16 sets of RAM section 320 and SAM section 320 exist in the backward direction 370 in the figure. Assuming that the number of memory cells per row 310 is 2 ⁿ (n is a natural number), data for 2 ⁿ cycles of the serial read clock 220 is transferred to the SAM unit 330 by one data transfer. However, the memory width 400 (Fig. 6) generally required for one horizontal scan and the corresponding S
The amount of data transferred to the AM section 330 is different. That is,
Generally, the column position j360 (0
Data is read from j2 ⁿ −1: j is a natural number. This indicates that the data required for one horizontal scan may extend over two rows 310, for example, the i th row 350 and the i + 1 th row 380. In this case, the data in the last column (j = 2 ⁿ −1) of the i-th row 350 is read and at the same time, the i + 1-th row 380 is read by the SAM.
It is necessary to transfer the data to the unit 330 and read from the first column (j = 0). This is called real-time data transfer (hereinafter referred to as R data transfer),
It will be distinguished from the above-mentioned data transfer.

The present embodiment is an example of control for R data transfer. As mentioned above, depending on the configuration of the VRAM 10, the R data bus 210
16 bits wide, 1 row 310, 2 ⁸ (= 256) bits, non-interlaced display with a memory width 400 of 70 words (70 words x 16 bits = 1120 pixels) with the configuration shown in Fig. 6 (a). With a graphic display device
R data transfer is required at the designated column position of the raster (horizontal scanning, counting from 0 raster) shown in FIG. 8 (a). As another example, data bus 210 width 8 bits, 1 row 3
The number of bits of 10 is 2 ⁸ (= 256) bits, and the memory width 400 is 80 words (80 words x 8 bits = 640 pixels) in the configuration shown in Fig. 6 (b). Data bus 210 width 1 as an example
6 bits, 1 row number of bits 2 ^8-bit 310, FIG. 6 memory width 400 in the configuration of (b) is 80 words (80 words × 16 bits = 1
In a graphic display device for displaying 280 pixels) in a non-interlaced manner, R data transfer is required at a designated column position of the raster shown in FIG.
The examples of FIGS. 9A and 9B show the case where non-interlacing is performed, but the case where interlacing (interlaced scanning) is performed becomes more complicated, and DTX is performed based on the synchronization signal described in the second embodiment. -It is difficult to construct DET3 and AD-DET2.

Therefore, the inventor reexamined the conditions when the R data transfer shown in FIG. 5 is performed. Then, it was found that the column position j360 at the time of R data transfer was always 0. That is, of the display addresses 100 to the VRAM 10 output from DC1, only the address bits designating the column 300 of the RAM section 320 are focused on, and when all of these are 0, the R data transfer timing is reached. Similarly, the access start prohibition signal is the VR of the display address 100 output by DC1.
Before h (h is a natural number) of the bit R data transfer indicating the column position j360 of the RAM section 320 of AM10, that is, the number of columns
When the 2 ^n, by the address value of a bit indicating the column position j360 is detected by decoding the case of 2 ⁿ -h-1 or more, it can be created. Time when DC1 counts up the display address And the access cycle time t of the CPU 50 in FIG.
maximum value of _cyc Therefore, the value of h can be determined as follows.

However Is a symbol indicating rounding up after the decimal point.

As a result, t _cyc (max) in FIG. 3 becomes t _cyc (max) = h × t _chr .

In consideration of the above, the second embodiment which can also perform the R data transfer which is not successful in the first embodiment is the embodiment of FIG. In the figure, when AD-DET2 and DTX-DET3 create the timing of the present invention based on the synchronization signal 120 of DC1 described in the first embodiment, AD-DET2 'and DTX-DET3' are R The respective output timing signals 130 and 150, 140 and 1 in the timing generating part of the present invention for data transfer.
60 is synthesized by OR means 6 and 7 and input signals 170 and 18 of ARB 8
It becomes 0.

It is apparent from the above description that the AD-DET2 'and DTX-DET3' can be configured by inverting, ANDing or ORing the signal of the predetermined bit of the display address 100.

As described above, in the present embodiment, data transfer for initial setting is performed for each raster, and only when R data transfer is necessary, R data is transferred during horizontal display only when R data is transferred. Transfers can be made. Therefore, there is the first effect that the initial number of accesses permitted for drawing by the CPU 50 can be maximized. Moreover, there is a second effect that the DC1 for the conventional standard (single port) memory, such as the Hitachi CRT controllers HD6845, HD63484, and the NEC μPD7220 can be used without using the DC1 dedicated to the dual port memory. In the AD-DTX2 'and DTX-DET3', the RAM section 320 shown in FIG. 5 is used.
When the total number of column bits of (that is, equal to the number of bits accommodated in the SAM unit 330) is 2 ⁿ , only n of the display addresses 100 output by DC1 need be decoded, that is, with a small amount of hardware. There is a third effect that can be realized. Further, when the timing for R data transfer is created by the method described in the present embodiment, even if the reading method of the VRAM 10 of the display device is changed on the way, that is, by changing the memory width 400, scroll processing, or the like. Even if the display read address changes, the fourth effect is obtained in that the display accurately follows the complicated timing as shown in FIG. 8 and the normal display operation is guaranteed.

FIG. 9 is an example of ARB 8 in FIGS. 1 and 7. 8
1, 82 and 83 are D flip-flops (hereinafter simply referred to as FF), 84, 86 and 87 are AND gates (hereinafter referred to as AND), 8
Reference numeral 5 is an OR gate (hereinafter referred to as OR), AND84, AND87
A circle on the input / output of indicates that the signal is a negative logic input / output.

The input / output signals to ARB8 in this example have the following meanings.
When the access request signal 250 from the CPU 50 is "1", it indicates that there is a request. The permission signal 260 for the access request is a signal that immediately becomes “1” when the access request comes and returns to “0” when the access is permitted. The signal 150 or 170 for prohibiting the access start of the CPU 50 indicates that it is prohibited when it is "1". Data transfer request line 160 or 180
Indicates that there is a request when "1". The access request to the T-GEN9 is made when the signal 190 rises from "0" to "1". A signal 191 is a signal for making the T-GEN9 discriminate whether the access is a data transfer (“1”) or an access from the CPU 50 (“0”) at that time.
2 is usually “1” and when the demand line 190 becomes “1”
This is a response signal from T-GEN9, and is "1" for a certain period of time when responding. 193 is a signal which becomes "1" only while the T-GEN9 is executing an access cycle. When the address switching signal 270 of the MPX11 is "1", it indicates that the address output by DC1 is selected.

FIG. 10 shows an example of T-GEN9 in FIGS. 1 and 7.
91 is FF, 92 is shift register (hereinafter referred to as SR), 93
Is AND, 94 is the data transfer timing generation circuit, 95 is the CPU 50
The access timing generation circuit, and 96 are data switching gates. FF9 when an access request is input by signal 190
1 is set, the data of sequentially "1" to _Q 1 ~Q _n of SR92 is slide into shift. This starts the access timing of VRAM10, but when the access starts
The response signal 192 is generated by D93. Further, one of the timing generation circuit 94 for data transfer or the access timing generation circuit 95 of the CPU 50 is selected by the selection circuit 96 by the signal 191 and supplied to the VRAM 10 as the signal line group 200. The signal 193 indicating the access cycle is generated by decoding the output of SR92. Circuits 94, 95, 96 are VRAM
There are as many as 10 given.

ARB8 and T-GEN9 have been described by way of example, but even if they are realized by other methods, they do not have any relation to the essence of the present invention.

As described above, the embodiments have been described, but the present invention can be implemented in other display devices that sequentially read out the frame buffer (display memory). For example DISP54
Is not limited to CRT, but LCD (liquid crystal display), EL, plasma display, fluorescent display, etc. may be used. Further, the Di / F 53 in FIG. 1 may simply be a parallel-serial conversion unit, or may include a character generator that converts a code into an image. They have nothing to do with the essence of the invention.

〔effect〕

According to the display data transfer method of the present invention, the dual port memory is used as the frame buffer, and when the real-time data transfer is performed so that the memory width can be controlled even when it is not a power of 2, the column address is simply used. Since it is only necessary to decode, the timing for carrying out the real-time data transfer can be generated without counting the number of data remaining in the serial access memory unit, so that the data transfer control circuit of the dual port memory can be easily constructed.

Further, according to the display data transfer method of the present invention, the data transfer can be controlled not only when the memory width is other than a power of 2, but also when interlaced scanning is performed. Can be used for the frame buffer.

According to the display system of the present invention, since the dual port memory can be used as the frame buffer even in a display system in which the memory width of the frame buffer is not a power of 2, the drawing speed can be increased three times or more.

Further, according to the display system of the present invention, even in the case of interlaced scanning, the dual port memory can be used for the frame buffer, so that the drawing speed can be increased three times or more.

[Brief description of drawings]

1 and 7 are diagrams showing an embodiment of the present invention, FIG. 2 is a timing diagram of a conventional method, FIG. 3 is a timing diagram of the present invention, FIG. 4 is a correlation diagram of a display screen and a synchronizing signal, FIG. 5 is an explanatory diagram of data transfer, FIG. 6 is a relational diagram between the display screen and the frame buffer, FIG. 8 is a diagram showing the origin of the R data transfer, FIG. 9 is the access in FIG. 1 and FIG. FIG. 10 is a detailed circuit diagram of the arbitration circuit 8, and FIG. 10 is a detailed circuit diagram of the access control signal generation circuit 9. 1 ... Display controller, 2 ... Drawing access start prohibition signal generation unit, 3 ... Data transfer timing generation unit, 8
...... Access arbitration circuit, 9 ...... Access control signal generation circuit, 10 ...... Dual port memory frame buffer, 11 ...... Address multiplexer, 50 ...... Microprocessor, 110 ...... Address bus, 100 ...... Display address bus, 210 …… Data bus.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Yoshiaki Kitazume Yoshiaki Kitazume 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Inside the Microelectronics Device Development Laboratory, Hitachi, Ltd. (56) Reference JP-A-60-72020 (JP , A) JP 61-11791 (JP, A) JP 62-42228 (JP, A)

Claims (4)

[Claims] 1. A method of transferring display data from a random access memory unit of a dual port memory in which display data to be displayed on a raster scan type display means is accumulated to a serial access memory unit, the method comprising: Upon read access to the dual port memory, decoding that the column address signal of the dual port memory has reached a predetermined value, and decoding from the random access memory unit to the serial access memory unit is performed according to the decoding result. By generating the data transfer timing signal No. 1, the display data corresponding to one scanning line of the display means accumulated in a plurality of rows of the random access memory unit is transferred in real time. Data transfer method. 2. Prior to each horizontal scanning, a second data transfer timing is generated according to a synchronizing signal for display, and the display corresponding to the one scanning line from the first row of the plurality of rows. The display data transfer method according to claim 1, wherein data is transferred from the random access memory unit to the serial access memory unit. 3. A display means, a dual port memory having at least a random access memory section and a serial access memory section, means for drawing display data in the dual port memory, a display address signal of the dual port memory and the display. A display system having a display control means for generating a plurality of synchronization signal groups for a synchronous operation with the means, wherein a plurality of rows of the random access memory unit corresponding to the scanning lines of the display means when the display data is read. In order to transfer the display data stored in the display unit to the display unit in real time, the random access memory unit decodes when the column address signal of the dual port memory has reached a predetermined value and the serial access memory unit Timing signal for data transfer to and from A display system comprising means for generating a signal. 4. A means for generating a second timing signal for data transfer from the random access memory section to the serial access memory section is provided according to the synchronization signal group of the display control means. The display system according to claim 3, wherein: