JPH01219890A - Musical interval modulating circuit - Google Patents

Abstract

PURPOSE:To prevent a tremolo modulation noise from being generated by outputting a detection signal and resetting a write address when an input sound signal reaches its peak value or a specific reference value and resetting a read address when the read address reaches or exceeds the final address at the time of detection signal output. CONSTITUTION:While a peak value of the input sound signal is detected, the sound signal begin to be written in a memory from an address 0 and when a next peak value is detected, data is written again from the address 0, so that a signal which has a similar phase and a similar address is written in the storage area of the same addresses of the memory repeatedly. Consequently, even if the read address exceeds the write address or vice versa, a sound signal which is read out of the memory varies continuously and never varies discontinuously unlike a conventional device, so the generated tremolo modulation noise can be suppressed until it can be ignored.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a pitch modulation circuit that modulates and outputs the pitch of a sound signal using a cut and splice method.

[Prior Art] Pitch modulation circuits using cut and splice methods have been known. This pitch modulation circuit has a memory that sequentially stores input sound signals according to write addresses and sequentially outputs them according to read addresses, and controls the ratio of the address switching speed of the write address and the address switching speed of the read address. By doing so, the pitch of the input sound signal is modulated to both higher and lower pitches.

However, while the conventional pitch modulation circuit using such a cut and splice method can modulate the pitch with a simple circuit, there is a problem in that tremolo modulation sound is mixed in as noise.

FIG. 6 shows an example of a conventional pitch modulation circuit using the cut and splice method, and this conventional circuit includes a first address counter 12A that outputs a write address, and a first address counter 12A that outputs a read address. second address counter 12
B, and a switch 14 that alternately switches the outputs of the counters 12A and 12B and outputs them to the memory 10.

Then, the sound signal 100 inputted via the amplifier 16A.
is converted into a digital signal by the A/D converter 18A and input to the memory 10. The input signals are sequentially written and stored in a predetermined memory area of the memory 1o according to the write address output from the first address counter 12A.

Furthermore, the sound signals written in the memory 10 are sequentially read out according to the read addresses output from the second address counter 12B, converted into analog signals using the D/A converter 18B, and then sent to the amplifier 16B. output via

FIG. 7 shows an example of the memory map of the memory 10, in which each address counter 12A, 12B sequentially specifies the address from ``ro'' to ``n'' until the address reaches ``n''. Then, addresses are designated again in sequence starting from "0".

Therefore, when the switching speed ratio of the addresses output from both the write and read counters 12A and 12B is 1, that is, when the speed at which both count values are incremented is the same, the input sound signal remains at the same pitch. will be output.

Further, the increment speed of the write address output from the address counter 12A is different from that of the address counter 12B.
If the increment speed is faster than the increment speed of the read address output from the input sound signal 100, the input sound signal 100 will be modulated to a lower pitch and output. This means that, for example, when the write address is sequentially incremented as 0°1.2, 3.4, etc., the read address is incremented as 0,0°1.1, 2, 2, etc. at 1/2 the speed. This is because when the frequency is incremented as . . . , the frequency of the output sound signal becomes relatively lower than that of the input sound signal.

Conversely, if the increment speed of the write address is slower than the increment speed of the read address, the frequency of the output sound signal will be relatively higher than that of the input sound signal, and the pitch will be higher. It will be modulated and output.

This pitch modulation output method is called the cut and splice method. In such a circuit, as described above, by controlling the increment speed ratio of each address counter 12A, 12B, that is, the address switching speed ratio, it is possible to modulate and output the input sound signal 100 to an arbitrary pitch. can.

Therefore, this pitch modulation circuit includes an oscillator 20 that oscillates and outputs a reference clock, a counter 22B that counts and outputs this reference clock, a frequency divider 22A that divides and outputs the reference clock, a comparator 24, and a pitch modulator. A level setting circuit 26 is provided.

The frequency divider 22A divides the reference clock output from the oscillator 20 into 1/8 as shown in FIG.
The frequency-divided output is outputted to the first address counter 12A.

Further, the counter 22B is formed as a 4-bit counter, and counts the reference clock output from the oscillator 20 as shown in FIG. Hemu is outputting.

Further, the pitch modulation level setting circuit 26 is configured to be able to set pitch modulation levels in 15 adjacent steps from "1" to "15" according to the count range of the 4-bit counter 22B, and the set value is The signals are outputted to the comparator 24 as 4-bit modulation degree digital signals D1 to D4.

FIG. 5 shows the pitch modulation level setting circuit 2 in this way.
The relationship between the pitch modulation level of the 15th stage adjacent to the pitch modulation level set using the pitch modulation level 6 and the 4-bit modulation degree digital signals D1 to D4 output in accordance with this pitch modulation level is shown.

The comparator 24 outputs the count outputs Q1 to Q4 of the 4-bit counter 22B to the pitch modulation level setting circuit 26.
At the same time as reaching the set values D1 to D4, a coincidence pulse signal is output to the second address counter 12B, and
Reset the 4-bit counter 22B.

Therefore, if the setting value of the pitch modulation level setting date #t26 is set to "8" according to the frequency division cycle of the frequency divider 22A, the comparator 24 will output pulses at the same frequency as the frequency divider 22A. That will happen. In this case, address counter 1
Since the increment speed of the count values 2A and 12B is the same, the input sound signal 100 is output at the same pitch without being modulated in any way.

Furthermore, when the setting value of the pitch modulation level setting circuit 26 is set to a value higher than "9", the cycle at which pulses are output from the comparator 24 becomes longer than the cycle at which pulses are output from the frequency divider 22A. Therefore, in this case, the increment speed of the read address output from the second address counter 12B is slower than the increment speed of the write address output from the first address counter 12A, so the sound signal is modulated to a lower pitch. It will be output.

For this reason, for example, the setting value of the pitch level setting circuit 26 can be changed to "
15", the read address increment speed is about 1/2 of the write address increment speed, so the frequency of the output sound 110 is also reduced to about 1/2 compared to the input sound signal 100. However, it is possible to modulate and output a sound signal to a low tone that does not reach one octave, but is close to it.

Conversely, if the setting value of the pitch modulation level setting circuit 26 is set to a value of "7" or less, the period at which pulses are output from the comparator 24 is the same as that at which pulses are output from the frequency divider 22A. It becomes more pheasant than the period.

Therefore, in this case, the increment speed of the read address output from the second address counter 12B is
Since the increment speed is faster than the increment speed of the write address output from the first address counter 12A, the sound signal is modulated and output at a high pitch.

For example, the setting value of the pitch modulation level setting circuit 26 is set to r4.
．． When set to , the increment speed of the read address is twice the increment speed of the write address, so the frequency of the output sound signal 110 is twice the frequency of the input sound signal 100, and the sound signal can be modulated and output to a tone one octave higher.

[Problems to be Solved by the Invention] As described above, in the pitch modulation circuit using the cut and splice method, by controlling the speed at which the read address and the write address are incremented, that is, the switching speed ratio of both addresses, It modulates and outputs the pitch of the input sound signal, both high and low.

Therefore, when modulating and outputting a high pitch level, the read address periodically overtakes the write address, and when modulating and outputting a low pitch level, the write address periodically overtakes the read address. become.

However, when focusing on the same memory area, when sound signals are sequentially written into the memory according to write addresses, the level of the previously written sound signal and the level of the newly written sound signal are usually significantly different. Therefore, the sound signals written to the memory areas at the addresses before and after the write address become discontinuous sounds whose phases differ greatly from each other.

Therefore, in conventional pitch level modulation circuits, when one address overtakes the other address, the read sound signal becomes discontinuous, and this discontinuous portion becomes tremolo modulation noise in the output sound signal. There was a problem that they were mixed together.

In particular, if the pitch modulation level is set by -1 using the pitch modulation level setting circuit 26, tremolo modulation noise will be periodically mixed in, and depending on the pitch modulation level setting value, this tremolo modulation noise may be There is a problem in that the value is relatively large, and the output sound signal becomes unpleasant to the ears.

[Object of the Invention] The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to adjust the pitch of an input sound signal to both lower and higher pitches without generating tremolo modulation noise. Another object of the present invention is to provide a pitch modulation circuit capable of modulating output.

[Means for Solving the Problems 1] In order to achieve the above object, the present invention has a memory that sequentially stores input sound signals according to write addresses and outputs them sequentially according to read addresses, A pitch modulation circuit that modulates and outputs the pitch of an input sound signal by controlling the address switching speed ratio of the read address and the read address outputs a detection signal when the input sound signal reaches a peak value or a predetermined reference value. and a control circuit that resets the write address when the detection signal is output, and resets the read address when the read address matches or exceeds the final address when the detection signal is output. Effect] In the pitch modulation circuit using the cut-and-splice method as in the present invention, when a sound signal is input, the input sound signal is sequentially stored in the memory according to the write address. Then, the sound signals stored in the memory are sequentially output according to the read addresses. By controlling the address switching speed ratio between the write address and the read address, the pitch of the input sound signal is modulated and output.

By the way, normally, input sound signals, especially human voice signals, have similar waveforms between adjacent waveforms. Therefore, as in the present invention, a signal detection circuit is used to detect the input sound signals. A detection signal is output when the peak value or a predetermined reference value is reached, and at the same time as this detection signal is output, the input sound signals are sequentially written from address O in the memory, and the next detection signal is output. By writing data in the same manner again from address O at this point in time, signals with similar phases and levels will be written in each storage area of the memory.

Therefore, according to the present invention, even when the read address overtakes the write address and vice versa, the read sound signal becomes a continuous sound, and tremolo modulation noise can be suppressed to a negligible level.

As described above, according to the present invention, it is possible to modulate and output the pitch of an input sound signal in both high and low pitch without generating tremolo modulation noise.

[Example] Next, preferred embodiments of the present invention will be described based on the drawings.

Note that the same reference numerals are given to the members corresponding to those of the conventional device, and the explanation thereof will be omitted.

11] FIG. 1 shows a preferred first embodiment of the pitch modulation circuit according to the present invention, and the pitch modulation circuit of the embodiment writes an input sound signal 100 to a memory 10 according to a write address. The sound signals stored in the memory 10 are sequentially stored and output in accordance with the read address.

By the way, in sound signals, especially human voice signals, adjacent waveforms have similar waveforms as shown in FIG.

The present invention focuses on such characteristics of sound signals, particularly human voice signals, and makes it possible to eliminate the possibility of tremolo modulation noise occurring even when the read address overtakes the write address or vice versa. This is characterized in that the sound signals are written to and read from the memory 10 so as to prevent the sound from occurring.

For example, as shown in Figure 2, at the same time as the peak value of the input sound signal is detected, the sound signal is sequentially written from address O in the memory 10, and when the next peak value is detected, it is written again at address 0. If data is written in the same manner from then on, signals with the same phase and level will be repeatedly written in the storage area of the memory 10 at the same address.

Therefore, even if the read address overtakes the write address, or vice versa, the sound signal read out from the memory will change continuously, and will not change discontinuously as in conventional devices. Therefore, the generated tremolo modulation noise can be suppressed to a negligible value.

In order to write and read such data, the circuit of the present invention includes a detection circuit 40 that outputs a detection signal when the input sound signal reaches a peak value or a predetermined reference value.
and a control port #150 that resets the write address when the detection signal is output, and further resets the read address when the read address matches or exceeds the final address when the detection signal is output.

In the embodiment, the detection circuit 4o detects the peak value of the sound signal based on the sound signal 1oo input through the amplifier 16a, and outputs this peak detection signal to the control circuit 50.

Further, the control circuit 50 writes the final address data to the area of the memory 10 designated by the write address at the same time as the peak value is detected, and then sets the write address outputted by the address counter 12A to "o". Reset.

Furthermore, this control circuit 5o has an address counter 12B.
When the final address data is read from the memory 10 according to the read address output by the address counter 12B, the read address output by the address counter 12B is simultaneously reset to "0".

By doing this, at the same time as the peak value of the sound signal input to the memory 1o is detected, the sound signal is written sequentially from address O in the memory 10, and when the next peak value is detected, Data is written again in the same way starting from address 0. Therefore, signals of similar phase and level are written in each storage area of the memory 40. The data written in this way is read out sequentially according to the read address. Therefore, even if the read address overtakes the write address or vice versa, the sound signal read out from the memory 10 will change continuously and will not change discontinuously as in conventional devices. Therefore, the generated tremolo modulation noise can be suppressed to a negligible value.

By the way, a normally inputted sound signal may have a plurality of local peak values, as shown in FIG. 3, for example.

In preparation for such a case, the detection circuit 4O of this embodiment provides a dead zone time for a certain period after detecting the first peak.
All peaks that occur within this dead zone time are judged to be invalid.

That is, the detection circuit 4o of the embodiment includes the peak detector 42
) filter 44 and one-shot pulse generator 46 (
For example, it is formed using a leading edge type monostable multivibrator, etc.).

The peak detector 42 detects a peak value in the input sound signal and at the same time outputs a detection pulse to the filter 44.

The filter 44 smoothes the input signal in this manner with a constant time constant, and outputs the smoothed signal to the one-shot pulse generator 46. Therefore, even if other peak values are detected within a certain period of time after the peak detector 42 detects the first peak value, the first peak detection signal h is
4 to the one-shot pulse generator 46, and the remaining peak detection signal is never input to the one-shot pulse generator 46.

The one-shot pulse generator 46 outputs a one-shot pulse to the control circuit 50 at the same time that the peak detection signal is input.

In this embodiment, the control circuit 50 is formed using two sets of buffers 52 and 54, one for input and one for output, and a delay circuit 58.

The input buffer 52 is usually an A/D converter 18.
The audio signal input via A is output to the memory 10. When a pulse signal is output from the one-shot pulse generator 46, this is outputted to the memory 10 as final address data.

Further, when a pulse signal is output from the one-shot pulse generator 46, the delay circuit 56 delays this signal for a predetermined short time and outputs it as a reset signal to the address counter 12A for outputting a read address. There is.

Therefore, according to the embodiment, when the peak value of the input sound signal 100 is detected using the detection circuit 40, the buffer 52 writes the final address data to the memory 10 according to the write address output at that time. At the same time, the write address output from the address counter 12A is reset to "0".

Further, the read buffer 54 normally converts data output from the memory 10 according to the read address into a D/A.
It is configured to output to converter 18B. and,
When the final address data is output from the memory 10, the second address counter 12B, which outputs the read address, is reset to "0" at the same time.

In this way, according to this embodiment, even if there are multiple local peak values in the input sound signal, the peak value of one waveform can be changed from the peak value of one waveform to the peak value of the next waveform without being affected by the local peak values. can be detected accurately and tremolo modulation noise can be effectively reduced.

By the way, in the pitch modulation circuit, when the setting value of the pitch modulation level setting circuit 26 is set to "15", the increment speed of the read address decreases to approximately 172 times the increment speed of the write address. Therefore, the frequency of the output sound signal 110 decreases to about 1/2 compared to the input sound signal 100, and as a result, the sound signal is modulated into a low sound that does not reach one octave, but is close to it. can do. This means that, as shown in Figure 9,
This means that when modulating the pitch to a lower pitch, there is a modulation degree resolution of 8 steps per octave.

Furthermore, when the setting value of the sound level setting circuit 26 is set to "4", the increment speed of the read address becomes twice as high as the increment speed of the write address. In comparison, the frequency of the output sound signal 110 is also doubled, and as a result, the sound signal can be modulated and output to a sound one octave higher. This means that, as shown in FIG. 9, when modulating and outputting a higher pitch, only four levels of modulation degree resolution can be achieved per octave.

In this way, the pitch modulation circuit has a relatively low modulation resolution when modulating the pitch to the lower side, but has a relatively low modulation resolution per octave when modulating the pitch to the higher side. There was a problem in that the modulation depth decreased to about 1/2, making adjustment of the modulation degree extremely rough.

FIG. 4 shows an example of a pitch modulation circuit according to the present invention that solves this problem.

In this embodiment, the pitch modulation level setting circuit 26 is configured such that the modulation level can be set in 16 stages from "0" to "15" as shown in FIG. - Outputs a 4-bit modulation degree digital signal consisting of D4 data.

The features of this embodiment include the inverter 30 and the write/read control circuit 3.
2 is provided, and the sound signal is formed to be modulated and output with high modulation degree resolution in both the lower and higher directions.

In the embodiment, the inverter 30 determines whether to modulate the pitch higher or lower based on the modulation degree digital signal output from the pitch modulation level setting circuit 26. When modulating to a lower value, the modulation degree digital signal is output as is to the comparator 24. In addition, when modulating to a higher level, a complement of "1" of the input modulation degree digital signal is created and outputted to the comparator 24.

FIG. 5 shows 4-bit digital signals 11-4 outputted from the inverter 30 in correspondence with 4-bit modulation degree digital signals D1-D4.

Further, the write/read control circuit 32 determines whether to modulate the sound signal to a lower level or a higher level based on the modulation degree digital signal.

When modulating to the lower side, similarly to the circuit shown in FIG. 1, switching is performed so that the address output from the address counter 12B is used as the read address, and the address output from the address counter 12A is used as the write address. Vessel 1
4. Control the memory 10. At this time, the modulation degree digital signal output from the pitch modulation level setting circuit 26 is input directly to the comparator 24 via the inverter 30.
The comparator 24 sets the reference clock to 8 in total from 8 to 15.
It functions as a frequency division counter that divides the frequency and outputs the frequency in stages.

Therefore, by switching the modulation degree digital signal output from the pitch modulation level setting circuit 26 over eight stages from "8" to "15", the address counter 12B's The count period of the read address to be output can be set relatively long over eight stages, and even when the sound signal is modulated to a lower level, a high modulation degree resolution of at least eight stages per octave can be obtained.

Conversely, when modulating the sound signal to a higher level, the switch 14 sets the address output from the address counter 12B as the write address and the address output from the address counter 12A as the read address. ,
Controls memory 10. At this time, the modulation degree digital signal output from the pitch modulation level setting circuit 26 is converted into a "1's complement" by the inverter 30 and input to the comparator 24, as described above, so the comparator 24 receives the reference clock. 8
It will function as a frequency division counter that divides and outputs frequencies over a total of 8 floors (15 to 15).

Therefore, by using the pitch modulation level setting circuit 26 to appropriately switch the modulation degree digital signal over eight stages from 0 to 7, the write address output from the address counter 12B can be adjusted to match the count cycle of the read address output from the address counter 12A. The count period can be set relatively long over eight stages. Therefore, even when the sound signal is modulated to a higher level, a resolution of at least 8 steps per octave can be obtained.

In this way, according to the present embodiment, as shown in FIG. The address switching speed ratio of count and write address count can be controlled.

Therefore, whether the sound signal is modulated lower or higher, the pitch can be modulated with high modulation degree resolution.

By the way, in the pitch modulation circuit of this embodiment, the counters 12A and 12B that output the read address and the write address are different depending on whether the pitch is modulated higher or lower, as described above. Become something. Therefore, in order to suppress tremolo modulation noise, it is necessary to determine whether to modulate the pitch higher or lower, and then set the corresponding address counter 12A or 12B.
It is necessary to reset the .

For this reason, the control circuit 50 of this embodiment is provided with a reset circuit 56 in addition to the buffers 52 and 54.

This reset circuit 56 is connected to the pitch modulation level setting circuit 26.
Based on the modulation degree digital signal output from the controller, it is determined whether to modulate the pitch higher or lower.

When modulating to a lower level, the first address counter 12A is output every time the peak detection signal is output from the one-shot pulse generator 46, as in the first embodiment.
and set the write address to "0". Then, at the same time that the final address signal is output from the memory 10 via the buffer 54, the second address counter 12
B is reset and its read address is set to "0".

Furthermore, when the reset circuit 56 determines that the pitch level is to be modulated to a higher level, it resets the second address counter 12B at the same time as the peak detection signal is detected, and sets the write address to "0". . Then, at the same time as the final address signal is output from the memory 10 via the buffer 54, the first address counter 12A is reset and the read address is set to "0".

In this way, in this embodiment, whether the pitch is modulated higher or lower, tremolo modulation noise can be suppressed to a negligible level, as in the first embodiment. can.

Note that the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the gist of the present invention.

For example, in the embodiment described above, the detection circuit 40 detects the peak value of the output sound signal, but the present invention is not limited to this. Various means other than this can be used as necessary, as long as the detection can be performed reliably.

For example, a predetermined reference level may be set in advance, and the detection signal may be output at the same time as the input sound signal reaches this reference level.

In this case, the sound signal usually crosses the reference level twice per cycle. Therefore, the detection circuit 40 may be formed to detect the point at which the sound signal intersects the reference level at either the rise or the fall.

Further, in the present invention, the detection circuit 40 is configured to set the slope of the sound signal as a predetermined reference value, and output a detection signal when the slope of the input sound signal reaches the set slope. You may.

By doing so, it is possible to reliably detect one period of the waveform of the sound signal, as in the case of detecting the peak value.

Furthermore, in the embodiment described above, the final address data is written in the storage area of the memory 10 specified by the write address when the detection signal is output, but the present invention is not limited to this. For example, memory 10
Separately, there is a buffer in which the final address data is written, and the final address data written in this buffer is compared with the read address, and a match signal is output when the read address matches or exceeds the final address data. A discriminator may be provided, and the control circuit 50 may be formed to reset the read address when a match signal is output from the discriminator.

Further, in addition to this, for example, the control circuit 50 is provided with a down counter in which the final address data is preset as an initial value and counts down in synchronization with the read address, and as soon as the count value of this down counter reaches 0, It is also possible to configure the read address to be reset.

[Effects of the Invention] As explained above, according to the present invention, an input sound signal can be modulated and output without generating tremolo modulation noise in a pitch modulation circuit using the force/soto & splice method. Can be done.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a preferred first embodiment of the pitch modulation circuit according to the present invention, and FIGS. 2 and 3 show operations when reducing tremolo modulation noise using the circuit shown in FIG. 1. 4 is a block circuit diagram showing a second preferred embodiment of the present invention; FIG. 5 is an explanatory diagram showing the operation of each embodiment shown in FIGS. 1 and 4; FIG. 6 is an explanatory diagram showing the operation of each embodiment shown in FIGS. is a block circuit diagram showing an example of a conventional pitch modulation circuit, FIG. 7 is an explanatory diagram of a memory used in the pitch modulation circuit, FIG. 8 is a timing chart diagram of the circuit shown in FIG. 7, and FIGS. 9 and 10 The figure is an explanatory diagram of the pitch modulation operation. 10... Memory 12A... First address counter 12B
... Second address counter 14 ... Switch 40 ... Detection circuit 42 ... Peak detector - 44 ... Filter 46 ... One-shot pulse generator 50 ...
Control circuit 52, 54...Buffer 56...Reset circuit Agent Patent attorney Husband (and 1 other person) Fig. 7 Fig. 8 Fig. 9 Fig. 10

Claims (3)

[Claims] (1) It has a memory that sequentially stores input sound signals according to write addresses and outputs them sequentially according to read addresses, and by controlling the address switching speed ratio of the write address and read address, the input sound In a pitch modulation circuit that modulates and outputs the pitch of a signal, there is a detection circuit that outputs a detection signal when the input sound signal reaches a peak value or a predetermined reference value, and a detection circuit that resets the write address when the detection signal is output and also reads the signal. a control circuit that resets the read address when the address matches or exceeds the final address at the time of outputting the detection signal; Features a pitch modulation circuit. (2) In the circuit according to claim (1), the detection circuit is formed so as not to perform peak detection for a certain period of time after detecting the first peak, and even if a plurality of local peaks occur, This pitch modulation circuit is characterized by accurately detecting the first peak of each waveform without being affected by this. (3) In the circuit according to any one of claims (1) and (2), the control circuit writes final address data to a storage area of a memory specified by a write address when outputting a detection signal. and a pitch modulation circuit configured to reset a write address and also to reset a read address when final address data is read from the memory.