JPH01217274A - Method for testing lsi circuit and lsi circuit for executing the same - Google Patents

Abstract

PURPOSE:To simultaneously test a plurality of circuit blocks in parallel, by making a test pattern signal multiple to separate the same into indivisual test pattern signals and applying said signals to the corresponding circuit blocks and also making the response signals therefrom multiple to separate the same to perform display. CONSTITUTION:Input test pattern signals T1N1...T1Nn are made multiple by a multiplexing circuit 1 to be inputted to a plurality of the circuit blocks of an LSI circuit 10. Next, said signals are separated into individual test pattern signals T1N1'...T1Nn' by the first separation circuit 2 to be applied to the respective circuit blocks 31...3n. Further, the outputs TOUT1'...TOUTn' responding to the test pattern signals from said blocks are also made multiple by the second multiplexing circuit 4 to be outputted from the LSI circuit 10 and separated into response outputs TOUT1...TOUTn by the second separation circuit 5 to be detected. By this method, a plurality of the circuit blocks in the LSI circuit can be simultaneously tested in parallel without increasing the number of pins.

Description

[Detailed Description of the Invention] [Summary] A method for testing an LSI circuit consisting of a plurality of circuit blocks, and an LSI circuit for carrying out the test.
The LSI circuit testing method is a testing method for an LSI circuit consisting of a plurality of circuit blocks, with the purpose of making it possible to simultaneously test multiple circuit blocks inside a circuit in parallel. After multiplexing the test pattern signals to be input to each of the circuit blocks, the signals are input to the LSI circuit, and the LSI circuit separates the multiplexed signals into individual test pattern signals to be input to the plurality of circuit blocks. The outputs from each of the plurality of circuit blocks in response to the test pattern signals are also multiplexed and output, and the multiplexed outputs are applied to the corresponding ones of the test pattern signals outside the LSI circuit. The LSI circuit for carrying out the test method is an LSI circuit consisting of a plurality of circuit blocks, and is a test method in which multiplexed test pattern signals are serially manually input. a signal output terminal; a separation circuit that separates the multiplexed test pattern signal into individual test pattern signals; and a signal output terminal from each of the plurality of circuit blocks.
The device is configured to include a multiplexing circuit that multiplexes outputs responsive to the separated test pattern signals, and a test signal output terminal that serially outputs the outputs of the multiplexing circuit.

[Industrial application field]

The present invention relates to a method for testing an LSI circuit consisting of a plurality of circuit blocks, and an LSI circuit for carrying out the test.

During the development and manufacture of LSI circuits, the LSI circuits are tested by inputting test pattern signals and detecting outputs responsive to the test pattern signals. By the way, in recent years, with the increase in the scale of LSI circuits, it has become possible to reduce the test time by dividing circuits within the LSI circuit into multiple circuit blocks and testing each circuit block simultaneously in parallel. There is a demand.

However, for this purpose, it is necessary to provide the LSI circuit with a large number of signal input/output pins for testing.

Therefore, there has been a need for a technique that can simultaneously test a plurality of circuit blocks inside an LSI circuit in parallel without increasing the number of signal pins.

[Prior art and problems to be solved by the invention]

The internal circuit of an LSI circuit is divided into multiple circuit blocks, a test pattern signal is manually applied to each circuit block simultaneously in parallel, and the output in response to each test pattern signal is detected. Tests are being conducted in a short period of time. Conventionally, in order to perform the above tests, test signal input/output pins dedicated to each circuit block were provided in the L31 circuit, and test input/output signals were sent in parallel via the dedicated signal output bins. I was inputting and outputting to.

Therefore, there was a problem in that it was necessary to provide the LSI circuit with a large number of signal input/output pins for testing purposes.

The present invention has been made in view of the above problems, and is an LSI circuit that enables multiple circuit blocks within an LSI circuit to be tested in parallel without increasing the number of test signal input/output pins. The object of the present invention is to provide a test method and an LSI circuit for carrying out the test.

[Means to solve the problem]

FIG. 1 is a basic configuration diagram of an LSI circuit testing method according to the present invention. Figure 2 shows the steps to carry out the test.
1 is a diagram showing a basic configuration including an LSI circuit according to the present invention.

As shown in FIG. 1, the LSI circuit testing method according to the present invention includes a plurality of circuit blocks 31 + 32 +...
- A test method for an LSI circuit 10 consisting of 3o, including test pattern signals TINI, TIN□, . . . to be input to each of the plurality of circuit blocks 31, 31, .
- After multiplexing TlN0, the first stage S1 is input to the LSI circuit 10, and the LSI circuit 10 separates the multiplexed signal M I N to the plurality of circuit blocks 31, 31, . . 3n, a second step S2 of applying voltage to each corresponding one of the plurality of circuit blocks 31, 31,
. . 3, the separated test pattern signals ('F181', TIN
□ ',..."rlNn ')) (also shown in Figure 2 are TOUTl ', TOLI72
' + . . . TOUT, , )) is multiplexed and outputted, and the multiplexed output M is outside the LSI circuit IO. Outputs in response to LIT (TOUTl, TOUT2. . . Toll in Figure 2)
A fourth stage S4 separates and detects the two parts (not shown by Tn).

FIG. 2 is a diagram showing the basic configuration for carrying out the above-described test method of the present invention, and in FIG.
0 is L according to the present invention for carrying out the test method.
This shows the basic configuration of an SI circuit.

In FIG. 2, ▪ is the first multiplexing circuit, 2 is the first R11 circuit, and 3. ．． 32. -3n is the LSI circuit 10
4 is a second multiplexing circuit, 5 is a second separation circuit, 6 is a test input terminal, and 7 is a test output terminal.

Among these configurations, the LSI circuit 10 according to the present invention has the following configurations:
The plurality of circuit blocks 34, 3°, . . . 3. .

In addition, it includes a first separation circuit 2, a second multiplexing circuit 4, a test input terminal 6, and a test output terminal 7. The test input terminal 6 is a multiplexed test pattern signal M.
1N serially, the first separation circuit 2 converts the multiplexed test pattern signal MIN into individual test pattern signals TINI'.

The second multiplexing circuit 4 separates the separated test pattern signals TIN+' from each of the plurality of circuit blocks 31+32+...3, . , TlN2
Z...Output TOU in response to T I N ,,'
T+ ' + Tot+rz ' + ”・TOI
IT11' is multiplexed, and the test output terminal 7 is the output M of the second multiplexing circuit 4. It outputs UT serially.

Furthermore, in order to carry out the above-described LSI circuit testing method according to the present invention, as shown in FIG.
The first multiplexing circuit 1 is connected to the test input terminal 6 of the I circuit 10.
is connected to the test output terminal 7 of the LSI circuit IO, and a second isolation circuit 5 is connected to the test output terminal 7 of the LSI circuit IO. The first multiplexing circuit 1
is the plurality of circuit blocks 3. ．． The eggplant 1-pattern signal TlN1.31, . TlN
2+.-T, N, , and the second separation circuit 5 receives the multiplexed output M. The test pattern signals Tl1l□, Tl from each of the plurality of circuit blocks 33131, . . . 3n are separated from the LIT.
821...Response signal T OutT+ to T1N□,
T0LI72. ”・ToLIT, .

[For production]

Test pattern signals T, N, T, N□,...T applied to each of the plurality of circuit blocks 31H321...3n that constitute the internal circuit of the LSI circuit 10
Before being input to the LSI circuit 10, INfi is multiplexed in the first multiplex circuit 1 and converted into a serial signal M I N, which is then input to the LSI circuit 10 from the test input terminal 6. After that, the plurality of circuit blocks 3I, 31, .
...3n, the individual test pattern signals T, old ', T, N are applied in the first separation circuit 2 to each of
It is separated into □ ′, . . . T I N n ′.

In addition, the plurality of circuit blocks 30, 31, . . . 3 described above
．． .

The test pattern signal TIN+' from each of the test pattern signals TIN+'.

T,,2', ``Response To to 'TINn'
urs'.

TOII72' + ”'TOUTn' also corresponds to the L
'Before being output from the SI circuit 10, it is multiplexed by the second multiplexing circuit 4 and output serially from the test output terminal 7. The serial output M. lla, the L
After being output from the SI circuit 10, the above response TOUT1. TOIIT21
...Separated into TOIITn.

In this way, a plurality of circuit blocks within an LSI circuit can be tested simultaneously and in parallel by providing only a very small number of test input/output terminals.

〔Example〕

FIG. 3 shows an example of a configuration for implementing the LSI circuit testing method according to the present invention.

The configuration of FIG. 3 corresponds to the above-mentioned FIG. 2, and in FIG. 3 as well, 10 indicates an LSI circuit for implementing the test method of the present invention, 31, 311, . . . 3. .

1 shows a plurality of circuit blocks forming the internal circuit of the LS1 circuit 10. In FIG. 3, 11 and 41 are parallel-to-serial conversion circuits, which correspond to the first and second multiplexing circuits in FIG. 2, respectively. Also, 21 and 5
Reference numeral 1 denotes a serial-parallel conversion circuit, which corresponds to the first and second separation circuits in FIG. 2, respectively. Furthermore, the frame synchronization signal generation circuit 8 shown in FIG. 3 outputs a frame synchronization signal that provides input/output timing in the parallel/serial conversion circuit 11° 41 and the serial/parallel conversion circuit 21° 51. Clock signal generation circuit 9 also outputs a clock signal for synchronizing the operations in parallel/serial conversion circuit 11.4L and serial/parallel conversion circuit 21.51.

In the configuration shown in FIG. 3, as well as in the configuration shown in FIG.
181. T 182. ...TINn is multiplexed in the parallel-serial conversion circuit 11 and converted into a serial signal M1N before being input to the LSI circuit 10, and is input to the LSI circuit 10 from the test input terminal 6. Thereafter, the serial signal M 1 H is sent to the plurality of circuit blocks 31, 31 described above.

. . 3n, the serial/parallel conversion circuit 21 applies each test pattern signal T to each test pattern signal T.
1□ ', TIN□ ',...T I N n
′. Further, the plurality of circuit blocks 3I,
The above test pattern signals TIN+', TIN□',...T I from each of 31,...3 degrees
Response signal Tout+' to Nr+',
TOUT2', -Touyr+' are also multiplexed by the parallel-to-serial conversion circuit 41 before being output from the output LSI circuit 10, and sent to the test output terminal 7.
It is output more serially. The serial output M. U7
After being output from the LSI circuit IO, the above response signal T is output in the serial/parallel conversion circuit 51. U1
1', ToU12',...'r011T. ′ TOLIT+, ′rOUTZ+ ”’TOU
It is separated into Tn.

The timing of the operation of the configuration in Figure 3 is as shown in Figures 4A and 4.
This is shown in Figure B. In FIGS. 4A and 4B, a plurality of circuit blocks 31, 31.

Test pattern signals input from the outside (TINl, TIN□, ...T'
8. , ) as (D, (-1), D2(-1), -Dn(-1)).

(DI(0), D2(0),...D,,(0))
.

(D, (1), D2(1), -Dn(1)), and (D + (2), D2(2),...D,
, (2)) are applied to the parallel-to-serial conversion circuit 11 of FIG. 3 at appropriate time intervals, and correspondingly, (
D+'(-1), D2'(-1),...D
,,' (-1)).

(D,'(0), D2'(0),...D,,'(
0)).

(]3) CDI'(1), D2'(1),...D,'(1)
), and (D,'(2), D2'(2),...
The case of detecting D,,'(2)) is shown.

FIG. 4A shows the plurality of circuit blocks 3. ．． 31...
3 degrees, and FIG. 4B shows the output side timings of each of the plurality of circuit blocks 31, 31, . . . 3 degrees.

At the rising edge of the clock signal CLK at time t1 shown in FIG. 4A, since the output of the frame synchronization signal generation circuit 8, the frame synchronization signal F, is at the °'H" level, the parallel-to-serial conversion is performed at this time. The test pattern signal (DI(
1), D2(1), . . . D, (1)) are input in parallel to the parallel-serial conversion circuit 11.

Also, at this time, the previously input test pattern signal (
DI(0).

Dz(0),...D,,(0)) are signals TINI', TIN from the serial/parallel conversion circuit 21.
□',...'raNn are output in parallel.

At time L2, the parallel/serial conversion circuit 11
The cent of the test pattern signal to be input next is (D, (2), I)2(2), -o,, (2)
) is applied.

From time L3, which is the rising timing of the next clock signal after time t1, the test pattern signal (
D, (1), D2 (1), . . . D, , (1)) are serially output as a signal M1N from the parallel-to-serial conversion circuit 11 and input to the serial-to-parallel conversion circuit 21.

The above test pattern signal (DI(1), D2(1)
, . . D, , the timing of the rise of the clock signal after the serial output of (1)) is completed, time L4
At this time, the frame synchronization signal F becomes "H" level again, and as a result, the test pattern signal (DI(2) applied to the parallel-to-serial conversion circuit 11 at this time
), D2(2), ·D, (2)) are input to the parallel-to-serial conversion circuit 11 in parallel. At this time, the above-mentioned test pattern signal (DI(1)
, D2(1), . . . D, , (1)) are the signals T, ,,', TlN2 from the serial/parallel conversion circuit 21.
Z...T I N n ' is output in parallel, and the corresponding circuit blocks 31, 31
, . . .3n. Moreover, from the next rising timing of the clock signal, time t5, the test pattern signals (DI(2), D2(2), . . . , D, (2)
) is the signal MI from the parallel/serial conversion circuit 11
It is output serially as N.

As shown in FIG. 4B, at the aforementioned time tl, the output signal TINI from the serial-to-parallel conversion circuit 21
', T+N□', . . . TINr+ ' for each circuit block 3 in the LSI circuit 10. ．． 31,・
・Test pattern signal CD applied at 3°, (
0).

Response signal 1 from each circuit block 31.31, . . . 3n to Dz(0), . . . D, , (0)): (
0), D'2 (OL...D,,'(0)) have already been output at the time t4, and at the time t
4, these response signals (D,'(0), DZ
'(0),...D,,'(0)) is the signal TOU
T+', Tou'r□',...TOLITn
' is input in parallel to the parallel/serial conversion circuit 41 shown in FIG.

Also, at time t4, the previously input test pattern signal (D, (-1),
Response signals (D
+'(-1), D,'(-1), ・D,'
(-1)) is the signal TOUT1. Tou'rz
, . . . are output in parallel as T OUT n. These outputs are detected as indicating the test results of each circuit block 31, 31, . . . 3n of the LSI circuit 10.

At time t5, which is the rising edge of the clock signal after time L4, the serial-to-parallel conversion circuit 41 outputs the response signal (D,'(0 ), D2
'(0), ·D,,' (0)) is the signal M.

It is output serially as u7.

Other test pattern signal cents (D, (1), D2 (1), ・D, (
1)) and (D, (2), D2(2),...D
, , (2)), each circuit block 3I, 31, .
...Response signal from 3n (D1'(1), DJ(1),
...D,, (1)), and <D', (2)
.

The above CD I'(0) also applies to D 2'(2) ,...D,,'(2)).

Similarly to D2'(0),...D,,'(0)),
At each timing when the frame synchronization signal becomes "H" level, the parallel/serial conversion circuit 41 of FIG. 3 inputs the cent of the response signal applied in parallel,
Serial output of the input signal data is started, and the serial-to-parallel conversion circuit 51 in FIG. One.

As described above, according to the configuration shown in FIG. 3, it is possible to simultaneously test a plurality of circuit blocks inside an LSI circuit in parallel without increasing the number of test signal input/output pins.

〔Effect of the invention〕

According to the present invention, it is possible to simultaneously test a plurality of circuit blocks inside the L S 1 circuit in parallel without increasing the number of test signal output pins.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the LSI circuit testing method according to the present invention, FIG. 2 is a diagram of the basic configuration for implementing the LSI circuit testing method according to the present invention, and FIG. 3 is a diagram of the basic configuration for implementing the LSI circuit testing method according to the present invention. Figures 4A and 4 illustrating an example of a configuration for carrying out the method;
Figure B is a timing diagram for the configuration of Figure 3. [Explanation of symbols] ■...first multiplexing circuit, 2...first separation circuit,
35, 31, ~3. ．． ...Circuit block, 4...Second multiplexing circuit, 5...Second separation circuit, 6...Test input terminal, 7...Test output terminal, 8...Frame synchronization signal Generation circuit, 9... Clock signal generation circuit, 11.41... Parallel-serial conversion circuit, 21
51... Serial/parallel conversion circuit.

Claims (1)

[Claims] 1. A plurality of circuit blocks (3_1, 3_2,...3n
) is a test method for an LSI circuit (10) consisting of a test pattern signal (T_I_N_1) to be input to each of the plurality of circuit blocks (3_1, 3_2, . . . 3n).
, T_I_N_2, . . . T_1_N_n) is input to the LSI circuit (10), and the LSI circuit (10) receives the multiplexed signals (M, N).
as individual test pattern signals (T_I_N_1_', T
_I_N_2_', ... T_I_N_n_'), and the plurality of circuit blocks (3_1, 3_2, ...
. . 3n), and the test pattern signals (T_I_N_1_', T
The output (T_O_U_T_1_', T_O_U_T_
2_',...T_O_U_T_n_') are also multiplexed and output, and the multiplexed output (M_O_U_T) is outputted from the responded output (T_O_U_T_1) outside the LSI circuit (10).
, T_O_U_T_2, . . . T_O_U_T_n). 2. Multiple circuit blocks (3_1, 3_2,...3_
an LSI circuit consisting of a test signal input terminal (8) that serially inputs the multiplexed test pattern signal (M, N), and a test signal input terminal (8) that serially inputs the multiplexed test pattern signal (M, N); Individual test pattern signals (T_I_N_1_', T_I_N_2_',
...T_I_N_n_') separation circuit (2)
and the plurality of circuit blocks (3_1, 3_2, . . .
3_n) from each of the separated test pattern signals (T_I_N_1_', T_I_N_2_', . . .
・Output (T_O_U_) in response to T_I_N_n_′)
T_1_', T_O_U_T_2_', ...T_O_
An LSI comprising: a multiplexing circuit (4) that multiplexes the output (M_O_U_T) of the multiplexing circuit (4); and a test signal output terminal (8) that serially outputs the output (M_O_U_T) of the multiplexing circuit (4). circuit.