JPH01216675A - Clamp circuit - Google Patents

Abstract

PURPOSE:To improve the reliability of the circuit by controlling switchingly a voltage set by a reference voltage power supply device synchronously with the ON/OFF of an emitter current, turning on a clamp transistor(TR) at clamp period and applying the on-control to the emitter current. CONSTITUTION:A base potential of a clamp TR 16 is lowered by a value corresponding to the resistance of a resistor R1 for a period other than the clamp period when TRs 19, 20 are turned off in a clamp circuit, since the TR 19 is turned off, the charge in a capacitic 12 is held. In this state, even if a signal with a voltage lower than the DC potential during the clamp period is inputted to an input terminal 11, no effect is caused in the output in a range where the clamp TR 16 is not turned on. Thus, the resistance of the resistor R1 is selected to be a potential difference or over between the DC level and the minimum potential the clamp period of the input signal. Thus, the TR 16 is not turned on for a period except the clamp period and no effect is caused to the output.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Technical Field of the Invention) The present invention relates to a clamp circuit used in a video signal processing circuit in, for example, a television device.

(Prior art) Figure 4 shows an example of a conventional clamp circuit.
The input signal input to the input terminal is supplied to the base of the output transistor Ql via the capacitor C, and the output signal is taken out from the emitter of this transistor Ql.The collector of this transistor Ql is connected to the power supply Vcc, and the emitter is connected to constant current source ■1.

Further, transistors Q2 and Q3 are set so that their emitters and collectors are connected to each other, and the connection point between the emitter of transistor Q2 and the collector of Q3 is connected to the base of transistor Q1, and the collector of transistor Q2 is connected to the base of transistor Q1. The connection point between Q3 and the emitter of Q3 is connected to the reference power supply V rer. The bases of these transistors Q2 and Q3 are connected to the transistor Q4.
Connect to power supply Vcc via. This transistor Q4
The base of the transistor Q5 is connected to the collector of the transistor Q5 together with the base of the transistor Q5 to form a current mirror circuit. The emitter of the transistor Q5 is connected to the power supply Vec, and the collector is connected to a switch SW controlled by a clamp pulse and turned on during the clamp period.
It is connected to constant current source 2 via.

In the clamp circuit configured as described above, when switch SW is turned on during the clamp period, transistors Q4 and Q5 are turned on, and transistor Q2 is turned on.
A base current corresponding to this clamp period is supplied to Q3.

Therefore, transistors Q2 and Q3 will operate in the saturation region during the clamp period.

During such a ramp period, if the saturation impedances of transistors Q2 and Q3 operating in the saturation region are sufficiently low, the base potential of transistor Ql becomes approximately equal to the reference voltage V rer of the reference power supply.

On the other hand, in a state other than the clamp period in which the switch SW is turned off, the impedance of the base of the transistor Q1 is set high, so that the charge in the capacitor C is held as is.

That is, this conventional clamp circuit is used as a beddeskle clamp circuit in which the potential generated at the output during the clamp period is set to the pedestal level. Such a ramp circuit is effectively used for an input signal that has a positive or negative potential with respect to the pedestal level.

However, in such a lamp circuit, if the saturation impedance of the transistors Q2 and Q3 cannot be set to a sufficiently low value, an offset voltage will occur in the output, and normal lamp operation will not be possible. It disappears.

(Problems to be Solved by the Invention) This invention has been made in view of the above points, and can effectively suppress the occurrence of offset voltage in the output, especially during the clamp period. It is an object of the present invention to provide a highly reliable clamp circuit that allows an output voltage at an accurate pedestal level to be obtained, thereby ensuring that, for example, a pedestal clamping operation is performed reliably.

[Structure of the Invention] (Means for Solving the Problems) In the clamp circuit according to the present invention, an input signal is supplied to the base of the output transistor via the capacitor, and the input signal is supplied to the base of the output transistor through the capacitor. A clamp transistor is provided whose emitter is connected and which is controlled to be on during the clamp period to maintain the base potential at a constant level, and this transistor is controlled to be on and off during the clamp period and other periods, and this on/off control is The emitter current of the clamp transistor is controlled to be turned on and off in synchronization.

(Function) In other words, in the clamp circuit configured as described above, the potential during the clamp period is determined by the emitter of the clamp transistor, and the clamp transistor is completely disabled outside the clamp period. Becomes controlled off. Therefore, the output level during the clamp period is determined by the emitter current of the clamp transistor, and unlike the conventional method, the saturation impedance of the clamp transistor is not used.
The clamp voltage can be set accurately to, for example, the pedestal level.

(Example of the invention) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

Figure 1 shows the circuit configuration, with input terminal 1
An input signal, such as a video signal, supplied to the output transistor 1 is supplied to the base of the output transistor 13 via the capacitor 12. This output transistor 13 has its collector connected to the power supply Vcc, and its emitter connected to a current of 1
The emitter of this transistor 13 is connected to the output terminal 15.

The base of this output transistor 13 is connected to the emitter of a clamp transistor 1B, and the collector of this transistor 16 is connected to a power supply vCC. The base of this transistor 16 is connected via a resistor R1 to a reference power source 17 to which a reference voltage V ref is set, and further connected to a power source Vcc via a current source 18.

The emitter of the clamp transistor 1B is further grounded via a transistor 19 and a resistor R2, and this transistor 19 is connected to a transistor 20.
At the same time, it is controlled to be turned on and turned off by a clamp pulse input supplied to the control terminal 21. The emitter of the transistor 20 is grounded via the resistor R3, and the collector is connected to the power supply Vc via the current source 22.
connected to c.

Here, the current source 22 and the current source 18 perform a current mirror operation, and the amount of current of the current source 18 is controlled according to the amount of current of the current source 22.

That is, the clamp circuit configured as described above is controlled by the clamp pulse input to the control terminal 21, and during the clamp period when the input clamp pulse is at a high level, the transistor 19 and 20 are turned on. And this transistor 19
When 20 and 20 are turned on, a current flows through the current source 22, and the current mirror causes a current to flow through the current source 18, thereby controlling the base potential of the clamp transistor 1B and turning on this transistor 18. It becomes like this. In this case, since the transistor 19 is turned on, the emitter current of the clamp transistor 16 flows through the transistor 19 and the resistor R2, and the output voltage VO during this clamp period is as shown in the following equation. Become.

VO-Vre(' +Vrl-Vbe18-Vbe1
3 Here, Vrl...voltage drop occurring across resistor R1.

V be18SV beL3-h Base-emitter voltage of transistor IB and transistor 13 In this clamp circuit, transistors 19 and 2
During a period other than the clamp period in which 0 is in the off state, the base potential of the clamp transistor 1B is lowered by an amount corresponding to the resistance value of the resistor R1, and the transistor 19 is turned off. Condensation 12
The charge of will be held. In this state, even if a signal with a voltage lower than the DC potential during the clamp period is input to the input terminal 11, the output will not be affected as long as the clamp transistor IB is not turned on. Therefore, if the value of the resistor R1 is selected to be greater than the potential difference between the DC level and the lowest potential during the clamp period of the input signal, the transistor 1B will not be turned on during periods other than the clamp period, and the output will be It is unlikely that any effects will occur.

That is, in this circuit, the clamp transistor 16 is controlled to be turned on during the clamp period, and the emitter current of this transistor 16 is determined by the transistor 19 and the resistor R2, so that the clamp level is stably set. Even during periods other than the clamp period, the clamp transistor 16 can be reliably prevented from being turned on, and a stable output can be obtained.

Here, by synchronizing the timing of turning on and off the transistor 19 with the timing of raising and lowering the base potential of the clamp transistor 16, it is possible to reliably suppress the DC offset of the output during the clamp period.

FIG. 2 shows another embodiment, in which the resistor R1 in the embodiment of FIG. 1 is constituted by diode-connected transistors 31 and 32. The output voltage VO during the clamp period in this circuit is expressed by the following equation.

V O-V ref' 10V be31+ V be3
2-VbelB-VbelB Here, Vbe31 and Vbe32 are base-emitter voltages of transistors 31 and 32, respectively.

In this embodiment, transistors 31 and 32 can cancel out temperature changes in the output voltage, and operations corresponding to temperature changes can be performed. The operation of this embodiment is similar to that of the embodiment shown in FIG. 1, and the same parts are given the same reference numerals and detailed explanation thereof will be omitted.

FIG. 3 shows yet another embodiment, which is basically the same as the embodiment shown in FIG. In this embodiment, the switching of the transistors 41 and 42 is controlled by the clamp pulses supplied to the control terminals 211 and 212, and the transistor 41 is turned on during the clamp period. In other cases, the transistor 42 is turned on. Transistors 43 and 44 are connected in series to the transistors 41 and 42, respectively, and a current [2] is supplied from the current [45] to each series circuit.
Further, it is arranged to be grounded via a resistor R4.

When the transistor 41 is turned on during the clamp period, the transistor 19 is turned on by the transistor 43.
is controlled to set the emitter current of the clamp transistor 16, and when the transistor 42 is on outside the clamp period, the transistor 19 is turned off, the transistor 46 is turned on, and the base of the clamp transistor 16 is connected to the resistor R2. It is designed to be grounded through.

Since the other parts are the same as those in the embodiment shown in FIG. 1, the same reference numerals are given and the explanation thereof will be omitted. Here, the transistor 46
operates similarly to transistor 20, and transistors 43 and 44 have similar functions to transistors 31 and 32 in the embodiment shown in FIG.

In this embodiment, the timing at which the transistor 19 is turned on and off can be easily synchronized with the timing at which the transistor 46 is turned on and off to switch the base potential of the clamp transistor 16 up and down.

[Effects of the Invention] As described above, in the clamp circuit according to the present invention,
During the clamp period, with the clamp transistor turned on reliably, the base potential of the output transistor is
This is determined by the emitter current of the clamp transistor, and effectively suppresses the occurrence of offset voltage in the output. Therefore, it can be used with high reliability, for example, as a pedestal clamp circuit to which a video signal is supplied.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a clamp circuit according to an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams showing other embodiments of the invention, and FIG. 4 is a conventional clamp circuit. FIG. 11...Input terminal, 12...Capacitor, 13...
・Output transistor, 14.18.22... current source,
15... Output terminal, 1B... Clamp transistor, 17... Reference power supply, 19.20... Transistor (sui clamp corresponding to clamp), 21... Control terminal (clamp noculus input). 1rA Figure 2

Claims (1)

[Claims] A capacitor having an input signal supplied to one terminal part and an output transistor connected to the other terminal part, and an emitter connected to the other terminal part of the capacitor, and the above-mentioned capacitor being in an on state only during the clamping period. A clamp transistor that clamps the signal supplied to the output transistor to a constant DC level is connected to the base of this clamp transistor, and different voltages are set for the above-mentioned clamp period and periods other than the clamp period, and the above-mentioned clamp transistor is turned on and off. The reference voltage power supply device includes a reference voltage power supply device that performs off control, and a means for controlling on/off the emitter current of the clamp transistor, and the voltage is set by the reference voltage power supply device in synchronization with the on/off of the emitter current. What is claimed is: 1. A clamp circuit that switches and controls the voltage value of the clamp transistor, turns on the clamp transistor, and turns on the emitter current during a clamp period.