JPH0582783B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clamp circuit suitable for use in a sync separation circuit of a VTR.

[Summary of the invention]

In a clamp circuit suitable for use in a VTR's synchronization separation circuit, this invention has a structure in which a synchronization signal is clamped by a synchronous type clamp circuit, and the output slice circuit of the clamp circuit is set to a level that can operate when there is no signal. By generating a clamp pulse from the slice circuit, clamping can be performed immediately upon signal input.

[Conventional technology]

FIG. 3 shows an example of a conventional VTR sync separation circuit. In FIG. 3, 51 indicates an input terminal, and a video signal is supplied from the input terminal 51 to a clamp circuit 53 via a low-pass filter 52. The clamp circuit 53 clamps the sync chip portion of the synchronizing signal in the video signal to a predetermined clamp level. The output of the clamp circuit 53 is supplied to the slice circuit 54.

A pulse is generated from the slice circuit 54 when the input level is lower than the slice level. The slice level is set to a level higher than the level of the sync chip portion of the video signal after clamping and lower than the level of other signal portions of the video signal. Therefore, when the signal of the sync chip portion is supplied to the slice circuit 54, a pulse is generated from the slice circuit 54, thereby separating the synchronization signal. The separated synchronization signal is taken out from the output terminal 55.

Conventionally, the clamp circuit of the synchronous separation circuit is
The one shown in Figure 4 was used.

FIG. 4 shows a clamp circuit called a diode clamp circuit. In Figure 4, 61,6
2 and 63 are NPN transistors. A reference power supply 65 is connected to the base of the transistor 61. A collector of transistor 61 is connected to power supply terminal 64 . The emitter of transistor 61 is connected to input terminal 67 via capacitor 66 and to the base of transistor 62.

The emitter of transistor 62 is transistor 6
The collector of the transistor 62 and the collector of the transistor 63 are commonly connected, and the transistors 62 and 63 constitute a Darlington-connected emitter follower transistor. A common connection point between the collectors of transistors 62 and 63 is connected to power supply terminal 64 . The emitter of the transistor 63 is grounded via a current source 68, and an output terminal 69 is led out from the emitter of the transistor 63.

The base-emitter voltage of transistor 61 is
V _BE61 and the voltage of the reference power supply 65 is V ₁₁ , the voltage V ₁₂ at the emitter of the transistor 61 is V ₁₂ =V ₁₁ −V _BE61 . Therefore, when the signal level supplied from input terminal 67 is lower than voltage V ₁₂ , the current flowing through transistor 61 charges capacitor 66 and the level applied to the base of transistor 62 is raised to voltage V ₁₂ . Input terminal 6
When the signal level supplied from 7 is higher than the voltage _V12 , transistor 61 is cut off. Therefore, the charge stored in the capacitor 66 is gradually discharged by the base currents of the transistors 62 and 63, and the signal level applied to the base of the transistor 62 is gradually lowered.

In the diode clamp circuit, since the charging current to the capacitor 66 is large and the discharging current is small, a signal at a level lower than the clamp voltage is instantly clamped, and a response to a signal at a level higher than the clamp voltage is slow. In this way, the sync chip level in the synchronization signal of the video signal supplied from the input terminal 67 is equal to the voltage V ₁₂
is clamped to and supplied to the transistor 62,
It is taken out from the output terminal 69.

When using the diode clamp circuit described above,
In the equalization pulse part of the vertical blanking interval, the fifth
As shown in Figure B, there was a problem in that the signal level fluctuated. This signal level fluctuation is
This is a particularly large variation when the capacitance of the capacitor 66 is small. When the clamp circuit is integrated into an integrated circuit, it is difficult to increase the capacitance of the capacitor 66. Therefore, this problem becomes a big problem when integrating the clamp circuit.

The signal level fluctuations occurring during the equalization pulse portion of the vertical blanking interval are explained as follows.

As described above, the voltage V ₁₂ at the emitter of transistor 61 is V ₁₂ =V ₁₁ −V _BE61 . . . , and the level applied to the base of transistor 62 is clamped to voltage V ₁₂ . The base-emitter voltage V _BE61 of the transistor 61 is expressed as V _BE61 = (kT/q) ln (I _C61 /I _S ). In the formula, q is the charge of the electron, k
is the Boltzmann constant, T is the absolute temperature, I _C61 is the collector current, and I _S is the reverse saturation current. Therefore,
From the equation, the base-emitter voltage V _BE61 of the transistor 61 changes depending on the collector current I _C61 of the transistor 61, which changes the voltage V ₁₂ and changes the clamped level. As shown in FIG. 6, the collector current I _C61 is a charging current i ₁ for the capacitor 66 and a leakage current i ₂ .
The charging current i ₁ for the capacitor 66 changes depending on the duty ratio (T ₂ /T ₁ ) of the input signal.

That is, as shown in FIG. 7, at time T ₁ when the signal level supplied from the input terminal 67 is higher than the clamp voltage V ₁₂ , the transistor 6
1 is cut off, and the charge stored in the capacitor 66 is discharged. Therefore, at time T ₁ ,
The level applied to the base of transistor 62 drops by ΔV _A as shown in FIG. This voltage ΔV _A is ΔV _A =(I ₁ /C)T ₁ . . . where I ₁ is the discharge current and C is the capacitance of the capacitor 66.

The signal level supplied from the input terminal 67 is the voltage
At time T ₂ when the level becomes lower than V ₂ , a charging current flows through the capacitor 66, and the level applied to the base of the transistor 62 becomes as shown in FIG.
It increases by ΔV _B. This voltage ΔV _B controls the charging current
Assuming I ₂ , ΔV _B =(I ₂ /C)T ₂ . At time _T2 , the voltage increases by the amount that the voltage decreases, so ΔV _A = ΔV _B . . . Therefore, (I ₁ /C)T ₁ =(I ₂ /C)T ₂ I ₁ T ₁ =I ₂ T ₂ I ₁ /I ₂ =T ₂ /T ₁ .... From the formula, the charging current I ₂ is the duty ratio
Varies depending on T ₂ /T ₁ .

In the vertical blanking period, as shown in FIG. 5A, 3H equalization pulses with different duty ratios (T ₂ /T ₁ ) are inserted before and after the vertical synchronization pulse. Therefore, the charging current I ₂ for the capacitor 66 during the equalization pulse part of the vertical blanking interval
changes. Therefore, the clamp voltage V ₁₂ changes in the equalization pulse part of the vertical blanking interval,
Fluctuations in signal level occur.

When the capacitance of the capacitor 66 is large,
According to the formula, since ΔV _A is small, the change in signal level caused by the equalization pulse in the vertical blanking interval does not pose a problem. However, the capacitance of a capacitor that can be realized within an integrated circuit is only a few hundred pF. When the capacitance of the capacitor 66 is small as described above, this variation in signal level becomes a big problem.

Therefore, as shown in FIG.
A synchronous clamp circuit is used in which one end is connected to a current source 72 via a switch circuit 70, a clamp pulse is supplied to the switch circuit 70 from a terminal 71, and the clamp pulse controls the switch circuit 70 to perform a clamp operation. is possible. This clamp pulse is formed by a synchronization signal taken from the slice circuit 54 in FIG.

A video signal is supplied from input terminal 67.
The clamp pulse from the slice circuit 54 in FIG. 3 is supplied from the terminal 71. While this clamp pulse is at low level, the switch circuit 70
is off. Therefore, the transistor 61 and the capacitor 66 operate as a diode clamp circuit.

When the clamp pulse becomes high level, the switch circuit 70 is turned on. Therefore, the capacitor 66
One end of the circuit is connected to a current source 72 via a switch circuit 70. As a result, the input signal is strongly clamped and taken out from the output terminal 69.

In other words, if the voltage applied to the base of the transistor 71 is V ₁₁ and the voltage between the base and emitter of the transistor 71 is V _BE61 , then the transistor 71
The voltage V ₁₂ at the emitter of is V ₁₂ = V ₁₁ − V _BE61 . When the signal level supplied from input terminal 67 is lower than voltage V ₁₂ , the current flowing through transistor 71 charges capacitor 66 and the signal level applied to the base of transistor 62 is raised to voltage V ₁₂ . When the signal level supplied from input terminal 67 is higher than voltage _V12 , transistor 61 is cut off. Therefore, the electric charge stored in the capacitor 66 is discharged by the current source 72, and the signal level applied to the base of the transistor 62 is lowered to the voltage _V12 . In this way, since the discharge current to the capacitor 66 is caused to flow by the current source 72, the response is quick even in the direction of lowering the signal voltage, and the signal level applied to the base of the transistor 62 is clamped to the voltage _V12 .

The current value I ₁₀ of the current source 72 is sufficiently larger than the charging current of the capacitor 66 . Therefore, the current flowing through the transistor 61 while the high-level clamp pulse is supplied is equal to the current value of the current source 72.
It is approximately equal to I ₁₀ and is constant. Therefore, according to the above equation, the base-emitter voltage V _BE61 of the transistor 61 is constant, and the clamp voltage V ₁₂ does not vary even if the duty ratio changes.

[Problem that the invention seeks to solve]

In the conventional synchronous clamp circuit shown in FIG. 8, it is necessary to supply a clamp pulse to the switch circuit 70. This clamp pulse is generated by the slice circuit 54 from the output of the clamp circuit 53 in FIG. That is, the slice level is set in the slice circuit 54, and the clamp circuit 53
A synchronizing signal is extracted in response to the output of the sync chip portion whose output becomes lower than this slice level, and a clamp pulse is generated.

In the conventional synchronous clamp circuit shown in FIG. 8, when the signal from the input terminal 67 becomes no signal, the output taken out from the output terminal 69 is
The charge stored in the signal becomes higher than the slice level, and the synchronization signal is not extracted and the clamp pulse is not generated. For this reason, there was a problem in that synchronous clamping could not be performed on an input signal supplied after a period of no signal.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a clamp circuit that can reliably clamp an input signal supplied after a period of no signal. Another object of the present invention is to provide a clamp circuit that does not use a large capacitance capacitor and is easy to integrate.

[Means for solving problems]

The present invention includes an input terminal 16 to which an input signal to be clamped is supplied, an emitter follower transistor 17 having one end connected to the input terminal 16 and the other end connected to the input terminal 16.
A clamp pulse is supplied to a series circuit consisting of a capacitor 15 connected to an output terminal 20 via a capacitor 18, a resistor 12 and a diode 11 connected between the first reference voltage source 13 and the other end, and the base. a first transistor 21 whose collector is connected and whose emitter is connected to the first current source 23; and a first transistor 21 whose base is connected to the second reference voltage source 28 and whose emitter is connected to the first current source 23. a third transistor 24 whose base is connected to the second reference voltage source 28, whose collector is connected to the connection point between the resistor 12 and the diode 11, and whose emitter is connected to the second current source 26; A fourth transistor 25 whose base is supplied with a clamp pulse and whose emitter is connected to a second current source 26, an output terminal 14, the first and fourth transistors 21,
25, and a slice circuit 6 which is connected between the base of 25 and generates a clamp pulse corresponding to a synchronization signal in an input signal.

[Effect]

A clamp pulse is supplied and the transistor 21
When turned on, one end of the capacitor 15 is connected to the current source 23 via the transistor 21, and the input signal is clamped to a constant level by the transistor 11, capacitor 15, and current source 23. When the input signal becomes non-signal, the transistor 24 is turned on, and current flows through the resistor 12 and the transistor 24. As a result, the output level becomes the clamp level, and the slice circuit 6 generates a clamp pulse.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows an example in which the present invention is applied to a sync separation circuit for a VTR. In FIG. 2, 1 indicates an input terminal, and a video signal is supplied from the input terminal 1 to a clamp circuit 3 via a low-pass filter 2. A clamp pulse generated by a slice circuit 6 is supplied to the clamp circuit 3 . The clamp circuit 3 clamps the sync chip portion of the synchronizing signal of the video signal.
The output of the clamp circuit 3 is supplied to a slice circuit 6 via a limiter 4 and an amplifier 5.

A slice level is set in the slice circuit 6. When the input level is below this slice level, a pulse is generated from the slice circuit 6. The slice level is set higher than the level of the sync chip portion of the clamped video signal and lower than the other signal portions of the video signal. Therefore, the signal from the sync chip is sent to the slice circuit 6.
, a pulse is generated from the slice circuit 6, which separates the synchronization signal. The separated synchronization signal is taken out from the output terminal 7, a clamp pulse is formed from this synchronization signal, and the clamp pulse is supplied to the clamp circuit 3.

The clamp circuit 3 is configured as shown in FIG. In Figure 1, 11 indicates an NPN type transistor, and the base of transistor 11 is connected to resistor 12.
It is connected to the reference power supply 13 via. A collector of transistor 11 is connected to power supply terminal 14 .
The emitter of transistor 11 is connected to input terminal 16 via capacitor 15, and also connected to the base of transistor 17 and the collector of transistor 21.

The emitter of transistor 17 is transistor 1
8, the collector of transistor 17 is connected to the collector of transistor 18,
Transistors 17 and 18 constitute a Darlington-connected emitter follower transistor. The collectors of transistors 17 and 18 are connected to power supply terminal 14. The emitter of the transistor 18 is grounded via a current source 19, and an output terminal 20 is led out from the emitter of the transistor 18.

The emitters of transistors 21 and 22 are commonly connected, and this common contact is grounded via a current source 23 whose current value is I ₀ . transistor 24
and 25 are commonly connected, and this common connection point is grounded via a current source 26 whose current value is _I1 . The base of the transistor 21 and the base of the transistor 25 are commonly connected, and a terminal 27 to which a clamp pulse is supplied is led out from this connection point. The base of transistor 22 and the base of transistor 24 are commonly connected, and a DC power supply 28 is connected to this connection point.

A collector of transistor 22 is connected to power supply terminal 14 . The collector of transistor 24 is connected to the connection point between the base of transistor 11 and resistor 12. A collector of transistor 25 is connected to power supply terminal 14 .

A video signal is supplied from input terminal 16.
The clamp pulse from the slice circuit 6 in FIG. 2 is supplied from the terminal 27. While this clamp pulse is at a low level, transistors 22 and 24 are on and transistors 21 and 25 are off. Therefore, the transistor 11 and the capacitor 15 operate as a diode clamp circuit.

When the clamp pulse becomes high level, transistors 21 and 25 are turned on, and transistor 22 is turned on.
and 24 is turned off. For this reason, capacitor 15
One end of the transistor 21 is connected to a current source 23 via a transistor 21. As a result, the input signal is strongly clamped and taken out from the output terminal 20.

That is, when the voltage V ₁ applied to the base of the transistor 11 is V 1 and the voltage between the base and emitter of the transistor 11 is V _BE1 , the voltage V ₂ at the emitter of the transistor 11 is as follows: V ₂ =V ₁ -V _BE1 . When the signal level supplied from input terminal 16 is lower than voltage V ₂ , the current flowing through transistor 11 charges capacitor 15 and the signal level applied to the base of transistor 17 is raised to voltage V ₂ . When the signal level supplied from input terminal 16 is higher than voltage _V2 , transistor 11 is cut off. Therefore, the charge stored in the capacitor 17 is discharged by the current source 23, and the signal level applied to the base of the transistor 17 is lowered to voltage _V2 . In this way, since the discharge current to the capacitor 15 is caused to flow by the current source 23, the response is quick even in the direction of lowering the signal voltage, and the signal level applied to the base of the transistor 17 is clamped to the voltage _V2 .

The current value I ₀ of the current source 23 is sufficiently larger than the charging current of the capacitor 15 . Therefore, the current flowing through the transistor 11 while the high-level clamp pulse is supplied is equal to the current value I ₀ of the current source 23.
is approximately equal to and constant. Therefore, the base-emitter voltage V _BE1 of transistor 11 is constant, and even if the duty ratio changes, the clamp voltage
V ₂ does not fluctuate.

When there is no signal from the input terminal 16, no synchronization signal is detected. Therefore, the clamp pulse becomes low level, and transistors 22 and 24 are turned on. At this time, since the transistor 24 is on, the reference current 13 is connected to the resistor 12,
Current flows through transistor 24. Therefore, the voltage V ₂ ' at the emitter of transistor 11 is
V ₂ ′=V ₁ −I ₁ R−V _BE1 ′ ...... In the equation, R represents the resistance value of the resistor 12, and _VBE1 ' represents the base-emitter voltage of the transistor 11 when almost no current flows.

From the above formula, when the clamp pulse is at a high level, the voltage at the emitter of transistor 11 is
V ₂ is V ₂ =V ₁ −V _BE1 . Therefore, if the value of I ₁ R is set appropriately so that V ₂ = V ₂ ′, the transistor 1 becomes
The level applied to the base of transistor 17 matches the level applied to the base of transistor 17 when the clamp pulse is supplied. Therefore, by setting the value of I ₁ R in this manner, a clamp pulse is generated from the slice circuit 6 when there is no signal, and the transistor 21 is turned on by this clamp pulse. As a result, even if the no-signal state continues, one end of the capacitor 15 is connected to the current source 23 via the transistor 21. Therefore, a signal supplied after a period of no signal can be reliably clamped.

〔Effect of the invention〕

According to this invention, when the signal from the input terminal 16 becomes non-signal, the signal level taken out from the output terminal 20 becomes equal to or lower than the slice level of the slice circuit 6. Therefore, a clamp pulse is generated even in a no-signal state. Therefore, even signals supplied after a period of no signal can be reliably clamped.

Further, according to the present invention, since a capacitor 15 having a small capacity can be used, integration is easy.

[Brief explanation of the drawing]

Fig. 1 is a connection diagram of an embodiment of the present invention, Fig. 2 is a block diagram of an example of the invention applied to a VTR sync separation circuit, and Fig. 3 is a block diagram of an example of a conventional VTR sync separation circuit. 4 is a block diagram of an example of a conventional clamp circuit, FIG. 5 is a waveform diagram used to explain an example of a conventional clamp circuit, and FIG.
The figure is a connection diagram used to explain a conventional clamp circuit.
FIG. 7 is a waveform diagram used to explain an example of a conventional clamp circuit, and FIG. 8 is a connection diagram of another example of the conventional clamp circuit. Explanation of main symbols in the drawings, 6: slice circuit, 11: transistor, 16: input terminal, 1
7, 18: Emitter follower transistor, 2
0: Output terminal, 21, 22, 24, 25: Switching transistor.

Claims (1)

[Claims] 1 an input terminal to which an input signal to be clamped is supplied; a capacitor having one end connected to the input terminal and the other end connected to an output terminal via an emitter follower transistor; a first reference voltage source; a series circuit consisting of a resistor and a diode connected between the other end, and a first transistor whose base is supplied with a clamp pulse, whose collector is connected to the other end, and whose emitter is connected to a first current source. and,
a second transistor having a base connected to a second reference voltage source and an emitter connected to the first current source; a base connected to the second reference voltage source and a collector connected to the resistor and the diode; a third transistor whose base is supplied with the clamp pulse and whose emitter is connected to the second current source; and a fourth transistor whose base is supplied with the clamp pulse and whose emitter is connected to the second current source; and a slice circuit connected between the bases of the first and fourth transistors and generating a clamp pulse corresponding to a synchronization signal in the input signal.