JPS61174883A - Clamping circuit - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a wide pulse due to the noise by integrating the synchronizing signal from the slice circuit at an integrating circuit and supplying it through the waveform shaping circuit to the switching element of the clamping circuit as a clamping pulse. CONSTITUTION:A video signal is supplied from an input terminal 15, and by a transistor 11, a capacitor 14, an electric current source 18 and a transistor 16 to switch the electric current source 18, the video signal is clamped at the timing of a clamping pulse supplied to the transistor 16. The clamping pulse integrates the synchronizing signal taken by a slice circuit 6 from the output of an output terminal 24 at an integrating circuit 8 and is supplied through a waveform shaping circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lamp circuit suitable for use in a sync separation circuit of a VTR.

[Summary of the invention]

The present invention has a lamp circuit suitable for use in a synchronization separation circuit of a VTR, in which a synchronization signal is clamped by a synchronization type clamp circuit, and a clamp pulse is supplied via an integration circuit and a waveform shaping circuit to reduce noise. This is a clamp circuit designed to eliminate the negative effects of

[Conventional technology]

FIG. 10 shows an example of a conventional VTR sync separation circuit. In FIG. 10, 71 indicates an input terminal, and a video signal is sent from the input terminal 71 to a low-pass filter 72.
is supplied to the clamp circuit 73 via. The clamp circuit 73 clamps the sync tip portion of the synchronization signal of the video signal to a predetermined clamp level. The output of the clamp circuit 73 is supplied to a slice circuit 74.

A pulse is generated from the slice circuit 74 when the input level is lower than the slice level. The slice level is
The level is set higher than the level of the sync tip portion of the video signal after clamping, and lower than the level of other signal portions of the video signal. Therefore, when the signal of the sync chip portion is supplied to the slice circuit 74, the slice circuit 74
A pulse is generated from 4, which separates the synchronization signal. The separated synchronization signal is taken out from the output terminal 75.

Conventionally, a clamp circuit shown in FIG. 11 has been used as a clamp circuit for a synchronous separation circuit.

FIG. 11 shows a clamp circuit called a diode clamp circuit. In FIG. 11, 81°82.83 is an NPN transistor. A reference power source 85 is connected to the base of the transistor 810. A collector of transistor 81 is connected to power supply terminal 84 . The emitter of transistor 81 is connected to an input terminal 87 via a capacitor 86, and is also connected to the base of transistor 82.

The emitter of the transistor 82 is connected to the base of the transistor 83, the collector of the transistor 82 and the collector of the transistor 83 are commonly connected, and the transistor 82
and 83 constitute a Darlington-connected emitter follower transistor. A common connection point between the collectors of transistors 82 and 83 is connected to power supply terminal 84 . The emitter of the transistor 83 is grounded via a current source 88, and the emitter of the transistor 83 is connected to the output terminal 8.
9 is derived.

The base-emitter voltage of the transistor 81 is V I
E @ I + If the voltage of the reference power supply 85 is vII, then
The emitter voltage vI□ of the transistor 81 is VIz=
V eyes V! It becomes IEII+. Therefore, when the signal level supplied from input terminal 87 is lower than voltage V12, capacitor 86 is charged by the current flowing through transistor 81, and the level applied to the base of transistor 82 is raised to voltage V12. When the signal level supplied from input terminal 87 is higher than voltage VI2, transistor 81 is cut off. Therefore, the charge stored in the capacitor 86 is gradually discharged by the base current of the transistors 82 and 83, and the signal level applied to the base of the transistor 82 is gradually lowered.

In the diode clamp circuit, since the charging current to the capacitor 86 is large and the discharging current is small, a signal at a level lower than the clamp voltage is instantly clamped, and a response to a signal at a level higher than the clamp voltage is slow. In this way, the sync chimp level in the synchronization signal of the video signal supplied from the input terminal 87 is clamped to the voltage VI2 and supplied to the transistor 82,
It is taken out from the output terminal 89.

Diode clamp circuits have a slow response to small signal signals. Therefore, it is less likely to be adversely affected by noise.

When the conventional diode clamp circuit shown in FIG. 11 is used, the first
As shown in FIG. 2B, there was a problem in that the signal level fluctuated. This signal level fluctuation becomes particularly large when the capacitance of the capacitor 86 is small. When the clamp circuit is integrated into an integrated circuit, it is difficult to increase the capacitance of the capacitor 86. Therefore, this problem becomes a big problem when integrating the clamp circuit.

The signal level fluctuations occurring during the equalization pulse portion of the vertical blanking interval are explained as follows.

As mentioned above, the voltage vI at the emitter of transistor 81
! Ha, V l! = VII −vgts+ ・
...■, and the level applied to the base of the transistor 82 is clamped to the voltage ■1□. The base-emitter voltage Vlltl11 of the transistor 81 is indicated by -. (2) In the equation, q is the electron charge, k is Boltzmann's constant, T is the absolute temperature + (2)C□ is the collector current, and Is is the reverse saturation current. Therefore, from formulas ■ and ■, the base-emitter voltage VIIE of transistor 81
II+ is the collector current ■ of the transistor 81. As a result, the voltage ■I□ changes, and the level to be clamped becomes i.

As shown in FIG. 13, the collector current I C1l+ is the charging current i for the capacitor 86 and the leakage current
It is. The charging current i for the capacitor 86 changes depending on the duty ratio ('rz/71) of the input signal.

That is, as shown in FIG. 14, at time T1 when the signal level supplied from the input terminal 87 is higher than the clamp voltage V I 2, the transistor 81 is cut off and the charge stored in the capacitor 86 is discharged. Discharged. Therefore, at time T, the level applied to the base of transistor 82 falls by ΔvA, as shown in FIG. This voltage Δ■1 is calculated as follows: Δva = (II /C) TI, where the discharge current is II + and the capacitance of the capacitor 86 is C.
・It is ■.

At time T2 when the signal level supplied from the input terminal 87 is lower than the voltage ■1□, a charging current flows through the capacitor 86, and the level applied to the base of the transistor 82 increases by ΔvI+ as shown in FIG. Rise. This voltage Δ■8 is calculated as follows: ΔVa = (tz /C)Tz...
・It is ■. At time T2, the voltage increases by the amount that the voltage decreases, so Δ■ months=ΔV, . . . ■. Therefore, (II /C)TI = (Tz /C)Tz■ Weight
Tr −Tz Tz r r / I 2 = Tz / 'r” +
−■ becomes. According to Equation 0, the charging current I2 changes depending on the duty ratio T2/T.

In the vertical blanking section, as shown in FIG. 12A,
Before and after the vertical synchronization pulse, the duty ratio (Tz/T+)
Different equalization pulses are inserted for 3H. Therefore,
During the equalization pulse portion of the vertical blanking interval, the charging current I2 for the capacitor 86 changes. Therefore, the clamp voltage vI! at the equalization pulse portion of the vertical blanking interval! changes, causing signal level fluctuations.

When the capacitance of the capacitor 86 is large, Δ■ is smaller than the equation (2), so the change in signal level caused by the equalization pulse in the vertical blanking section does not pose a problem. However, the capacitance of a capacitor that can be realized within an integrated circuit is several hundred pF. When the capacitance of the capacitor 86 is small as described above, this variation in signal level becomes a big problem.

Therefore, as shown in FIG. 15, the current value is changed to one end of the capacitor 86 through a switch circuit 90.

terminal 91 to the switch circuit 90.
It is conceivable to use a synchronous clamp circuit that supplies a clamp pulse from the circuit and controls the switch circuit 90 using the clamp pulse to perform a clamp operation. This clamp pulse is formed by a synchronization signal taken from slice circuit 74 in FIG.

A video signal is supplied from input terminal 87.

The clamp pulse from the slice circuit 74 in FIG. 10 is supplied from the terminal 91. While this clamp pulse is at a low level, the switch circuit 90 is off.

Therefore, the transistor 81 and the capacitor 86 operate as a diode clamp circuit.

When the clamp pulse becomes high level, the switch circuit 90
turns on. Therefore, one end of the capacitor 86 is connected to a current source 92 via a switch circuit 90. As a result, the input signal is strongly clamped and taken out from the output terminal 89.

In other words, the voltage applied to the base of transistor 81 is V++, and the voltage between the base and emitter of transistor 81 is Vll! If I11, the voltage at the emitter of transistor 81 is ■,! is, VB=V11-VB@.

becomes. When the signal level supplied from input terminal 87 is lower than voltage vIz, capacitor 86 is charged by the current flowing through transistor 81, and the signal level applied to the base of transistor 82 is raised to voltage V1□. When the signal level supplied from input terminal 87 is higher than voltage V1□, transistor 81 cants off. Therefore, the electric charge stored in the capacitor 86 is discharged by the current source 92, and the signal level applied to the base of the transistor 82 is lowered to the voltage V,2. In this way, since the discharge current to the capacitor 86 is caused to flow by the current s, 92, the response is quick even in the direction of lowering the signal voltage, and the signal level applied to the base of the transistor 82 is clamped to the voltage VI2.

The current value 110 of the current source 92 is sufficiently larger than the charging current of the capacitor 86. Therefore, the current flowing through the transistor 81 while the high-level clamp pulse is being supplied is approximately equal to the current value 1° of the current source 92, and is constant. Therefore, according to the above equation 0, the base-emitter voltage VBE81 of the transistor 81 is constant, and the clamp voltage VI2 does not vary even if the duty ratio changes.

[Problem that the invention seeks to solve]

The conventional synchronous clamp circuit shown in FIG. 15 strongly clamps the input signal to a clamp level at the timing when a clamp pulse is supplied. For this reason, a problem arises in that the clamping operation is performed even on noise that drops below the clamp level, resulting in a wide pulse being output. For example, Figure 16A
As shown in FIG. 10, when switching noise N is included in the video signal, when this signal is supplied from the input terminal 87, this noise N causes the slice circuit 74 in FIG. 10 to generate a clamp pulse. A clamp operation is performed by a clamp pulse. A clamp pulse is generated by the slice circuit 74 from the output of the clamp circuit, and when the clamp pulse is supplied, the input signal supplied from the input terminal 87 is strongly clamped. Therefore, even when the noise N exceeds the clamp level EC, the noise N is lowered to the clamp level Ec, and the output shown in FIG. 16B is taken out from the output terminal 89. This output is supplied to the slice circuit 74, and is output as a pulse when the slice level is E or below.
The slice circuit 74 outputs a wide pulse P due to this noise N, as shown in FIG. 16C. This pulse P causes the synchronous separation circuit to malfunction.

Therefore, an object of the present invention is to provide a clamp circuit in which malfunctions caused by noise are improved.

Another object of the invention is to provide a lamp circuit that is easy to integrate.

[Means for solving problems]

The present invention comprises an input terminal 5 to which an input signal to be clamped is supplied, and a capacitor 14 having one end connected to the input terminal 15 and the other end connected to the output terminal 24 via an emitter follower type transistor 21, 22. , a diode 11 connected between the first reference voltage source 12 and the other end, a current source 18 connected between the other end and the reference potential point via a switching element 16.17, and an output terminal 24. It has a connected slice circuit 6 for extracting the synchronization signal, an integration circuit 8 for integrating the synchronization signal, and a waveform shaping circuit 9 for shaping the waveform so as to advance the phase of the edge portion of the output of the integration circuit 8. The output of the shaping circuit 9 is connected to the switching element 16
．． This is a clamp circuit configured to supply a clamp pulse to 17 control electrodes.

[Effect]

A video signal is supplied from an input terminal 15, and is clamped by a transistor 11, a capacitor 14, a current source 18, and a transistor 16 that switches the current source 18 at the timing of a clamp pulse supplied to the transistor 16. This clamp pulse is produced by integrating a synchronizing signal taken out by the slice circuit 6 from the output of the output terminal 24 by the integrating circuit 8 and supplied via the waveform shaping circuit 9.

〔Example〕

An embodiment of the present invention will be described in the following order with reference to the drawings.

A. Description of an embodiment applied to a synchronization separation circuit of a VTR.

B. Configuration and explanation of a clamp circuit in one embodiment.

C2 Configuration and explanation of an integrating circuit in one embodiment.

D. Configuration and explanation of a waveform shaping circuit in one embodiment.

A. Description of an embodiment applied to a synchronization separation circuit of a VTR.

FIG. 1 shows an example in which the present invention is applied to a sync separation circuit for a VTR. In FIG. 1, 1 indicates an input terminal, and a video signal is supplied from the input terminal 1 to a clamp circuit 3 via a low-pass filter 2. A clamp pulse is supplied to the clamp circuit 3 from a waveform shaping circuit 9. The clamp circuit 3 clamps the sync depth portion of the synchronization signal of the video signal. The output of the clamp circuit 3 is connected to the limiter 4. The signal is supplied to a slice circuit 6 via an amplifier 5.

A slice level is set in the slice circuit 6. When the input level is below this slice level, a pulse is generated from the slice circuit 6. The slice level is set higher than the level of the sync tip part of the video signal after clamping and lower than the level of other parts of the video signal.

Therefore, when the signal of the sync tip portion is supplied from the clamp circuit 3 to the slice circuit 6, a pulse is generated from the slice circuit 6, thereby separating the synchronization signal. The separated synchronizing signal is taken out from the output terminal 7 and is supplied to the integrating circuit 8.

The pulse of the synchronization signal output from the slice circuit 6 is integrated by the integrating circuit 8 to form a pulse with a blunted rise. This pulse with a blunted rise is supplied to the waveform shaping circuit 9.

Two reference levels are set in the waveform shaping circuit 9. When the output of the integrating circuit 8 is at a level between these two reference levels, a pulse is output from the waveform shaping circuit 9. This pulse is supplied to the clamp circuit 3 as a clamp pulse.

B. Configuration and Description of Clamp Circuit in One Embodiment The clamp circuit 3 is configured as shown in FIG. In FIG. 2, numeral 11 is an NPN type transistor.

A reference power supply 12 is connected to the base of the transistor 11 via a resistor 10.

A collector of transistor 11 is connected to power supply terminal 13 . The emitter of transistor 11 is connected to input terminal 15 via capacitor 14, and transistor 1
6 and the base of transistor 21.

The emitter of the transistor 16 and the emitter of the transistor 17 are commonly connected, and this common connection point is connected to the constant current source 18.
grounded through. A terminal 19 is led out from the base of transistor 16. Reference voltage #20 is connected to the base of transistor 17. A collector of transistor 17 is connected to power supply terminal 13 .

The emitter of transistor 21 is connected to the base of transistor 22! The collector of the transistor 21 and the collector of the transistor 22 are commonly connected, and the collector of the transistor 21 and the collector of the transistor 22 are connected in common.
and 22 constitute a Darlington-connected emitter follower transistor. A common connection point between the collectors of transistors 21 and 22 is connected to power supply terminal 13 . The emitter of the transistor 22 is grounded via the current source 23, and the emitter of the transistor 22 is connected to the output terminal 2.
4 is derived.

A video signal is supplied from input terminal 15.

A clamp pulse is supplied from terminal 19. While this clamp pulse is at a low level, transistor 17 is on and transistor 16 is off. Therefore, the transistor 11 and the capacitor 14 function as a diode clamp.

When the clamp pulse becomes high level, transistor 1
6 is turned on and transistor 17 is turned off. For this reason,
One end of the capacitor 14 is connected to a constant current source 18 via a transistor 16. As a result, the input signal is strongly clamped and taken out from the output terminal 24.

That is, the reference voltage applied to the base of the transistor 11 1. If the voltage between the base and emitter of the transistor 11 is □, then the voltage at the emitter of the transistor 11 is v
2 is V2=V, -V. .

becomes. When the signal level supplied from input terminal 15 is lower than voltage V2, capacitor 14 is charged by the current flowing through transistor 11, and the signal level applied to the base of transistor 21 is raised to voltage V2. The signal level supplied from input terminal 15 is voltage ■
When higher than 2, transistor 11 cants off. Therefore, the electric charge stored in the capacitor 14 is discharged by the current source 18, and the signal level applied to the base of the transistor 21 is lowered to the voltage V2.

In this way, since the discharge current to the capacitor 4 is caused to flow by the current source 18, the response is quick even in the direction of lowering the signal voltage, and the signal level applied to the base of the transistor 21 is clamped to the voltage Vz.

As mentioned above, the clamp pulse is formed by the output of the clamp circuit 3 in FIG.
Integrating circuit 8. It is supplied via the waveform shaping circuit 9.

Therefore, the sync chimp level in the video signal is clamped to the voltage V2 and supplied to the transistor 21, and taken out from the output terminal 24.

Configuration and Description of Integrating Circuit in Embodiment C1 Integrating circuit 8 is configured as shown in FIG. In FIG. 3, numeral 31 indicates an NPN type transistor, and the emitter of the transistor 31 is grounded. transistor 3
1 is connected to an input terminal 34 through a parallel connection of a capacitor 32 and a resistor 33, and is also grounded through a resistor 35. The collector of transistor 31 is resistor 3
6 to the power supply terminal 37 and to the base of the transistor 38.

A resistor 39 is inserted between the base of transistor 38 and ground. The emitter of transistor 38 is grounded. The collector of the transistor 38 is connected to the power supply terminal 3 via the resistor 40.
7, and a capacitor 41 is inserted between the collector of the transistor 38 and ground, and the transistor 38
An output terminal 42 is led out from the collector of.

The output of the slice circuit 6 in FIG. 1 is supplied from the input terminal 34 in FIG. from the input terminal 34 to the fourth
When the pulse shown in Figure A is applied, this pulse is inverted in transistor 31 and the pulse shown in Figure 4B is applied to the base of transistor 38. This transistor 3
At the falling edge of the pulse supplied to base 80, transistor 38 turns off. When the transistor 38 turns off, a charging current flows through the capacitor 41, and the transistor 38
The voltage at the collector of , gradually increases with the time constant of the capacitor 41 and the resistor 40 . When the pulse supplied to the base of transistor 38 goes high, transistor 38 turns on. When the transistor 38 turns on,
The charge stored in the capacitor 41 is transferred to the transistor 3.
8, the voltage at the collector of transistor 38 becomes low level.

Therefore, when a pulse shown in FIG. 4A is supplied from the input terminal 34, a pulse with a blunted rise shown in FIG. 4C is outputted from the output terminal 34.

In FIG. 1, the clamp pulses supplied to the clamp circuit 3 are supplied via the integrating circuit 8, so that malfunctions due to noise are reduced.

In other words, when a signal containing noise N is supplied from the input terminal 1 in FIG. 1 as shown in FIG. A narrow pulse P7 shown in FIG. 5B is output. The output of the slice circuit 6 is integrated by an integration circuit 8. Therefore, the potential of the narrow pulse Pl does not rise to the predetermined level 2, as shown in FIG. 5B. Therefore, even if a pulse due to this noise is supplied from terminal 19 in FIG.
Transistor 16 will not turn on and will not act as a clamp pulse.

Incidentally, since the clamp pulse supplied to the clamp circuit 3 is generated by the slice circuit 6 from the output of the clamp circuit 3, there is a delay with respect to the synchronization signal supplied to the clamp circuit 3. For this reason, the DC level of the entire signal falls compared to the clamp level, and as shown in FIG. 6, the synchronization signal Sy is shrunk. If the output of the slice circuit 6 is supplied to the clamp circuit 3 via the integration circuit 8, this delay time will increase and the contraction of the synchronization signal will become more noticeable.

The shrinkage of the synchronization signal is explained as follows. As shown in FIG. 7, if the clamp pulse CP appears after the delay time T with respect to the synchronization signal Sy, then at time t1 to t2, even though the period of the synchronization signal has ended, the clamp pulse does not appear. It continues to be output. Therefore, time t1-t
At step 2, a clamping operation is performed, and the DC level drops by ΔV. Therefore, the level of the sync tip portion of the next synchronization signal is lowered by Δ■ compared to the clamp level. The level of this sync tip portion is lowered to the clamp level by the next clamp pulse. This clamp pulse also has a delay time T with respect to the synchronization signal.
Only late. Therefore, the clamp operation is not performed for a time T after the synchronization signal is supplied, and the level of this portion becomes lower than the clamp level. Therefore, as shown in FIG. 6, the synchronization signal is compressed.

D. Configuration and Description of the Waveform Shaping Circuit in One Embodiment The waveform shaping circuit 9 is provided so as to prevent the synchronization signal from being compressed due to the delay of the ramp pulse.

The waveform shaping circuit 9 is configured as shown in FIG. In FIG. 8, 51 indicates an NPN transistor,
An input terminal 52 is led out from the base of transistor 51. A collector of transistor 51 is connected to power supply terminal 53. The emitter of transistor 51 is grounded via resistor 54 and connected to the bases of transistor 55 and transistor 62.

The emitters of transistor 55 and transistor 56 are commonly connected, and this common connection point is grounded via resistor 57. The collector of the transistor 55 is the power supply terminal 5
Connected to 3. The collector of transistor 56 is connected to the base of emitter follower transistor 63. The base of transistor 56 is grounded via current source 60 and connected to power supply terminal 53 via series connection of resistors 58 and 59.

The emitters of transistor 61 and transistor 62 are commonly connected, and this common connection point is grounded via resistor 64. The base of transistor 61 is connected to the connection point between resistor 58 and resistor 59. A collector of transistor 61 is connected to power supply terminal 53. The collector of transistor 62 is connected to power supply terminal 53 via resistor 65 and to the base of transistor 630.

The collector of emitter follower transistor 63 is connected to power supply terminal 53. An output terminal 66 is led out from the emitter of the transistor 63, and the emitter of the transistor 63 is grounded via a current source 68.

Transistors 55 and 56 constitute a first comparison circuit, and transistors 61 and 62 constitute a second comparison circuit. The output of the integrating circuit 8 in FIG. The resistors 58 and 59 form a comparison voltage Vrl and a comparison voltage VrZ higher than the comparison voltage vr+. The comparison voltage v1.1 is supplied to the base of the transistor 56, and the comparison voltages 2, , 2 are supplied to the base of the transistor 62.

The input signal and the comparison voltage V are connected by transistors 55 and 56.
A level comparison is made with rl. The input signal is the comparison voltage V
1, when lower, transistor 56 is on;
Transistor 55 is off.

When the input signal becomes higher than the comparison voltage V, -1, transistor 55 is turned on and transistor 56 is turned off. Input signal and comparison voltage ■1 by transistors 6I and 62
A level comparison is made with □. The input signal is the comparison voltage ■,
, 2, transistor 61 is on and transistor 62 is off. The input signal is the comparison voltage ■,
When it becomes higher, transistor 62 turns on and transistor 63 turns off.

The levels at the collector of transistor 56 and the collector of transistor 62 are taken out from output terminal 66 via emitter follower transistor 63. Therefore, the output taken out from the output terminal 66 indicates that the input signal is at the comparison voltage ■
7. It becomes high level when the input signal is between Vr1 and Vr2, and becomes low level when the input signal is lower than the comparison voltage vrl or higher than the comparison voltage V, , 2.

When the output of the integrating circuit 8 shown in FIG. 9A is supplied from the input terminal 52, when the output of the integrating circuit 8 is at a level between the reference voltage is being output. The pulse shown in FIG. 9B is output.

This pulse is supplied as a clamp pulse to the clamp circuit 3 in FIG. 1. The generation of this pulse is stopped when the input level reaches the reference voltage ■7□, so the clamp pulse will not be output after the sync signal section ends (this will prevent the sync tip portion of the sync signal from being output). Therefore, the DC level of the entire signal level will not drop, and the synchronization signal will not be compressed.

〔Effect of the invention〕

According to the present invention, the synchronizing signal taken out from the slicing circuit 6 is integrated by the integrating circuit 8, and is supplied as a clamp pulse to the switching element of the clamp circuit via the waveform shaping circuit 9. Therefore, the noise component output from the slice circuit 6 is
It is integrated at , does not rise to a predetermined level, and does not work as a clamp pulse. Therefore, wide pulses are not output due to noise. In addition, the waveform shaping circuit 9
Ensures that the sync tip portion of the sync signal is clamped, while other signal portions are not. Therefore, the signal level does not drop and the synchronization signal does not shrink. Furthermore,
Since it is a synchronous clamp configuration, the clamp capacitor 1
4 can be made small in capacity, and integration is easy.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment in which the present invention is applied to a synchronization separation circuit of a VTR, Fig. 2 is a connection diagram of a clamp circuit in an embodiment of the invention, and Fig. 3 is an embodiment of the invention. FIGS. 4 and 5 are waveform diagrams used to explain the integration circuit in an embodiment of the present invention, and FIGS. 6 and 7 are waveform diagrams used to explain the contraction of the synchronization signal. , FIG. 8 is a connection diagram of a waveform shaping circuit in an embodiment of the present invention, FIG. 9 is a waveform diagram used to explain the waveform shaping circuit in an embodiment of the present invention, and FIG. 10 is a synchronization separation diagram of a conventional VTR. Block diagram of an example of the circuit, 1st
Figure 1 is a connection diagram of an example of a conventional clamp circuit, Figure 12 is a waveform diagram used to explain the conventional clamp circuit, Figure 13 is a connection diagram used to explain the conventional clamp circuit, and Figure 14 is a diagram of the conventional clamp. FIG. 15 is a waveform diagram used to explain the circuit, FIG. 15 is a connection diagram of another example of the conventional synchronous clamp circuit, and FIG. 16 is a waveform diagram used to explain the influence of noise on the conventional synchronous clamp circuit. Explanation of main symbols in the drawings 3: Clamp circuit, 6: Slice circuit, 8: Integrating circuit,
9: Waveform shaping circuit, 11: Transistor, 12: Reference power supply, 14: Capacitor, 15: Input terminal, ts, t7:
Switching transistor, 18: Current source, 21.22
: Emitter follower transistor, 24: Output terminal. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Waveform water conditioning circuit Figure 8 Figure 10 Figure 12

Claims (1)

[Claims] an input terminal to which an input signal to be clamped is supplied; a capacitor having one end connected to the input terminal and the other end connected to an output terminal via an emitter follower transistor;
a diode connected between the first reference voltage source and the other end; a current source connected between the other end and the reference potential point via a switching element; and a current source connected to the output terminal to output a synchronizing signal. It has a slicing circuit for extracting the synchronizing signal, an integrating circuit for integrating the synchronizing signal, and a waveform shaping circuit for shaping the waveform so as to advance the phase of the edge portion of the output of the integrating circuit, and the output of the waveform shaping circuit is controlled by the switching. A clamp circuit that supplies a clamp pulse to the control electrode of the element.