JPS61156915A - Threshold value switching circuit - Google Patents

Threshold value switching circuit

Info

Publication number
JPS61156915A
JPS61156915A JP59274278A JP27427884A JPS61156915A JP S61156915 A JPS61156915 A JP S61156915A JP 59274278 A JP59274278 A JP 59274278A JP 27427884 A JP27427884 A JP 27427884A JP S61156915 A JPS61156915 A JP S61156915A
Authority
JP
Japan
Prior art keywords
voltage
threshold value
trs
transistor
threshold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59274278A
Other languages
Japanese (ja)
Other versions
JPH0588566B2 (en
Inventor
Toshiyuki Tawara
俊幸 田原
Hiroyasu Uehara
上原 啓靖
Tadakatsu Kimura
木村 忠勝
Toshio Hayashi
林 敏夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP59274278A priority Critical patent/JPS61156915A/en
Publication of JPS61156915A publication Critical patent/JPS61156915A/en
Publication of JPH0588566B2 publication Critical patent/JPH0588566B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE:To attain threshold switching setting with high accuracy by using two transistors (TRs) having an identical characteristic to switch the threshold value and controlling the setting of threshold value with high accuracy by a resistor and a reference power supply independently of the saturated voltage of the TRs. CONSTITUTION:An input voltage is applied to a non-inverting input of a comparator OP1, the comparator OP1 compares the input voltage VIN with an inverting input voltage Vth and outputs the result as a voltage Vout. Then a current of an input TRQ3 of a current mirror comprising the TRs Q3, Q4 connected to the output is controlled to allow the output TRQ4 to control a TRQ0 in the threshold switching TRs Q1, Q0 to actuate the TRQ1 for the threshold value change. It is possible to decrease the setting error from nearly 10% of a conventional threshold value switching using a low reference voltage into an error of 1% or below by providing the paired TRs for the threshold value switching. Thus, the comparison with high accuracy is attained even when the reference voltage is low without being affected by the saturated voltage of the TRs.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、閾値切替えによるヒステリシス特性を有する
信号検出回路に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a signal detection circuit having hysteresis characteristics by threshold switching.

(従来の技術) 従来のヒステリシスを有する検出回路は、第7図に示さ
れるような構成であり使用されるコンパレータの回路例
を第8図に示す(SEMICONDUC−TOR,DA
TA BOOK、産業用リニアIC,インターフェース
用IC,頁789頁831日立製作所カタログ)。
(Prior Art) A conventional detection circuit with hysteresis has a configuration as shown in FIG. 7, and an example of the comparator circuit used is shown in FIG.
TA BOOK, Industrial Linear IC, Interface IC, page 789, page 831 Hitachi Catalog).

第7図に示す回路は、出力V。utが低レベル(=OV
)から高レベル(”Vcc)に移行する入力電圧VIN
の条件は(1)式で示され、高レベルから低レベルに移
行する入力電圧条件は(2)式で示される。
The circuit shown in FIG. 7 has an output of V. ut is low level (=OV
) to high level (Vcc)
The condition for input voltage is expressed by equation (1), and the input voltage condition for transition from a high level to a low level is expressed by equation (2).

ここで(1)式において、Youtは第8図に示すトラ
ンジスタQ、の飽和電圧であり近似的にゼロとおけば(
11(2)式で示される2つの閾値は基準電源である電
源電圧VCCと抵抗によって決まる。
Here, in equation (1), Yout is the saturation voltage of the transistor Q shown in FIG. 8, and if approximately set to zero, then (
The two threshold values shown by equation 11(2) are determined by the power supply voltage VCC, which is a reference power supply, and the resistance.

(発明が解決しようとする問題点) しかしながら、VCCが低く、かつ閾値精度を要求され
る場合、上記で近似的にゼロとした(11式のVou 
t、すなわち第8図のQ8の飽和電圧の影響が無視でき
ない。すなわちトランジスタの飽和電圧はコレクタ電流
温度等により数mV〜500 mV程度まで変動する。
(Problem to be solved by the invention) However, when VCC is low and threshold accuracy is required, the above value is approximately zero (Vou in equation 11).
t, that is, the influence of the saturation voltage of Q8 in FIG. 8 cannot be ignored. That is, the saturation voltage of a transistor varies from several mV to about 500 mV depending on the collector current temperature and the like.

従って、R,−R3としVcc 5Vとすると最大10
係程度の誤差が発生し精度の高い閾値設定が困難である
という欠点があった。
Therefore, if R, -R3 and Vcc 5V, the maximum is 10
However, this method has the drawback that it is difficult to set a highly accurate threshold value due to the occurrence of errors of the order of magnitude.

従って、本発明は集積回路に適した回路構成により高精
度な閾値切替え設定が可能な回路を得ることを目的とす
る。
Therefore, an object of the present invention is to obtain a circuit that can perform highly accurate threshold switching settings using a circuit configuration suitable for integrated circuits.

(問題点を解決するための手段) 本発明の特徴は、閾値切替えとして集積化することによ
り容易に得られる同一特性を有する2ケのトランジスタ
を用いて閾値切替えを行い、かつ閾値設定がトランジス
タの飽和電圧等と無関係に抵抗と基準電源によって精度
よく設定できることにある。
(Means for Solving the Problems) A feature of the present invention is that threshold switching is performed using two transistors having the same characteristics that can be easily obtained by integrating them for threshold switching, and that the threshold setting is different from that of the transistor. The advantage is that it can be set accurately using a resistor and a reference power supply, regardless of the saturation voltage, etc.

(作 用) 上記構成により、閾値電圧は基準電圧を抵抗分割するこ
とにより得られ、かつ閾値切替えスイッチには同一特性
のペアトランジスタを用いるので、トランジスタの飽和
電圧の影響をうけずに、基準電圧が低い場合でも精度の
よい比較を行なうことが出来る。
(Function) With the above configuration, the threshold voltage is obtained by dividing the reference voltage by resistance, and a pair of transistors with the same characteristics is used for the threshold selection switch, so the reference voltage can be adjusted without being affected by the saturation voltage of the transistor. Accurate comparisons can be made even when the

(実施例) 第1図は、本発明の第一の実施例である。(Example) FIG. 1 shows a first embodiment of the invention.

コンパレータOPlの正相端子に入力電圧が印加され、
コンパレータOPlは、入力電圧VINと負相端子電圧
Vthを比較し、結果を電圧Vou tとして出力する
と同時に出力に接続された、トランジスタQ3.Q、か
らなるカレントミラーの入力トランジスタQ3の電流を
制御し、出力トランジスタQ4は、閾値切替え用のトラ
ンジスタQ。r QlのQ。
An input voltage is applied to the positive phase terminal of the comparator OPl,
Comparator OPl compares input voltage VIN and negative phase terminal voltage Vth, outputs the result as voltage Vout, and simultaneously outputs the result from transistor Q3. The output transistor Q4 is a transistor Q for threshold switching. Q of r Ql.

を制御しこれによりQ、が動作し閾値変更が行なわれる
。入力電圧VINに対する比較電圧Vth、出力電圧V
ou tの波形を第3図に示す。すなわち、VINに対
して以下の条件で出力が変化する。
As a result, Q is operated and the threshold value is changed. Comparison voltage Vth with respect to input voltage VIN, output voltage V
The waveform of out is shown in FIG. That is, the output changes with respect to VIN under the following conditions.

(3)式はVoutが高レベルから低レベルへの変化の
場合であり、(4)式はV。utが低レベルから高レベ
ルへの変化の場合である。ここで、ΔVBEはトランジ
スタQ。rQl 0ベ一スエミツタ間電圧差であり各々
のコレクタ電流をIC0T IC+とすると(5)式で
示される。
Equation (3) is when Vout changes from a high level to a low level, and Equation (4) is when Vout changes from a high level to a low level. This is the case when ut changes from a low level to a high level. Here, ΔVBE is the transistor Q. rQl 0 is the base-emitter voltage difference, and if each collector current is IC0T IC+, it is expressed by equation (5).

rso j FランジスタQ。の逆方向飽和電流■s1
;トランジスタQ1の逆方向飽和電流■T=亘(”26
mV)  Ta=2b℃K ;ボルツマン定数 q ;電子の電荷 T ;絶対温度 丁s。、■s、はトランジスタQ。、Ql  が同一形
状で同一プロセス条件であるならほぼ同一となり集積回
路化することで容易に実現できる。
rso j F transistor Q. Reverse saturation current ■s1
;Reverse saturation current of transistor Q1■T=Wataru("26
mV) Ta=2b℃K; Boltzmann's constant q; electron charge T; absolute temperature ds. , ■s is a transistor Q. , Ql have the same shape and the same process conditions, they are almost the same and can be easily realized by integrated circuits.

従って、トランジスタQ。jQIのコレクタ電流比が2
倍程度異なっても(5)式よりISO”ISIとすると
、 ΔVBE−=26X10−36m(2):18XlO−
”(V)(Ta=25°C)程度であり式(4)に誤差
として及ぼす影響度は、VEE=5V  R2=FL3
としても0.4 q6程度でありほぼ無視し得る。コン
パレータOP1の構成として第2図に示す構成とすれば
、カレントミラーを構成するトランジスタQ3.Q、は
不用であり代りに集積回路では容易なダブルコレクタを
有するPNP トランジスタQ2で構成できる。
Therefore, transistor Q. The collector current ratio of jQI is 2
Even if the difference is about a factor of two, if we take ISO''ISI from equation (5), ΔVBE-=26X10-36m(2):18XlO-
”(V) (Ta=25°C), and the degree of influence on equation (4) as an error is VEE=5V R2=FL3
Even so, it is about 0.4 q6 and can be almost ignored. If the comparator OP1 has the configuration shown in FIG. 2, the transistors Q3. Q is unnecessary, and can instead be constructed with a PNP transistor Q2 having a double collector, which is easy to use in an integrated circuit.

第4図は正の入力信号に対する構成例を示す。FIG. 4 shows a configuration example for a positive input signal.

閾値切替え用トランジスタとしてPNPトランジスタペ
アQ。、Qlを用い、トランジスタQ。の駆動用にトラ
ンジスタQ、、Q、からなるカレントミラー回路が追加
されている。入力VINに対する各点の動作電圧は第5
図に示す。また閾値設定は式(3)(41の−VEEを
+VCCに変更すれば良く同様に、トランジスタQ。+
Q+を同一形状、同一プロセスで構成することにより精
度良く設定できる。
PNP transistor pair Q as threshold switching transistors. , Ql, and the transistor Q. A current mirror circuit consisting of transistors Q, , Q, is added for driving. The operating voltage at each point with respect to the input VIN is the fifth
As shown in the figure. Also, the threshold value can be set by changing -VEE in equation (3) (41) to +VCC.Similarly, transistor Q.+
By configuring Q+ with the same shape and the same process, it is possible to set it accurately.

第6図はカレントミラー用トランジスタQ3+ Q4+
Q、、 Q、を用いずにコンパレータOPIを構成する
場合の一例である。
Figure 6 shows current mirror transistor Q3+ Q4+
This is an example of a case where the comparator OPI is configured without using Q,,Q,.

(発明の効果) 以上説明したように閾値切替え用としてトランジスタペ
アを設けることにより従来の閾値切替え時の低基準電圧
使用時の設定誤差を、従来構成の10チ程度から1係以
下の誤差にすることが可能である。
(Effects of the Invention) As explained above, by providing a transistor pair for threshold switching, the setting error when using a low reference voltage during threshold switching can be reduced from about 10 in the conventional configuration to an error of 1 factor or less. Is possible.

従ってヒステリシスを有する検出回路において閾値に精
度を要しかつ使用基準電源電圧が低い所で使用する検出
回路に使用して効果が大きい。
Therefore, the present invention is highly effective when used in detection circuits having hysteresis that require high accuracy in threshold values and are used in locations where the reference power supply voltage used is low.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図の各都電圧波形を示す図、第4図は本発明の別の
実施例を示す図、第5図は第4図の回路の電圧波形を示
す図、第6図は第4図のコンバレー0PIL%IYrk
L プ切lτ算す図、第7図は従来のヒステリシス回路の例
、第8図は第7図で用いられるコンパレータの例である
。 OPl;コンパレータ V工N;入力端子 VOut z出力端子
FIG. 4 is a diagram showing another embodiment of the present invention; FIG. 5 is a diagram showing voltage waveforms of the circuit in FIG. 4; FIG. 6 is a diagram showing voltage waveforms in the circuit shown in FIG. 4. Combare 0PIL%IYrk
7 is an example of a conventional hysteresis circuit, and FIG. 8 is an example of a comparator used in FIG. 7. OPl; Comparator V; Input terminal VOut z output terminal

Claims (1)

【特許請求の範囲】[Claims] 入力信号と、基準電圧のスイッチにより切替え可能な抵
抗分割により与えられる閾値とを比較し、比較結果を出
力するヒステリシス特性を有する信号検出回路において
、前記スイッチがベースを相互に接続したトランジスタ
ペアであり、該トランジスタペアの一方のトランジスタ
のエミッタが前記抵抗分割を与える抵抗に接続され、該
トランジスタペアの他方のトランジスタのエミッタは基
準電位に接続されベースとコレクタは相互に接続されて
信号検出回路の出力に従って制御されることを特徴とす
る閾値切替え回路。
In a signal detection circuit having a hysteresis characteristic that compares an input signal with a threshold value given by a resistance divider switchable by a switch of a reference voltage and outputs a comparison result, the switch is a pair of transistors whose bases are connected to each other. , the emitter of one transistor of the transistor pair is connected to the resistor providing the resistance division, the emitter of the other transistor of the transistor pair is connected to a reference potential, and the base and collector are connected to each other to provide an output of the signal detection circuit. A threshold switching circuit characterized in that it is controlled according to the following.
JP59274278A 1984-12-28 1984-12-28 Threshold value switching circuit Granted JPS61156915A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59274278A JPS61156915A (en) 1984-12-28 1984-12-28 Threshold value switching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59274278A JPS61156915A (en) 1984-12-28 1984-12-28 Threshold value switching circuit

Publications (2)

Publication Number Publication Date
JPS61156915A true JPS61156915A (en) 1986-07-16
JPH0588566B2 JPH0588566B2 (en) 1993-12-22

Family

ID=17539424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59274278A Granted JPS61156915A (en) 1984-12-28 1984-12-28 Threshold value switching circuit

Country Status (1)

Country Link
JP (1) JPS61156915A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01188016A (en) * 1988-01-22 1989-07-27 Hitachi Ltd Hysteresis comparator
US5092880A (en) * 1988-10-21 1992-03-03 Genjiro Ohmi Method of determining the astigmatic power and the power for an intraocular lens, for a toric intraocular lens

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5726922A (en) * 1980-07-24 1982-02-13 Nec Corp Voltage comparator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5726922A (en) * 1980-07-24 1982-02-13 Nec Corp Voltage comparator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01188016A (en) * 1988-01-22 1989-07-27 Hitachi Ltd Hysteresis comparator
US5092880A (en) * 1988-10-21 1992-03-03 Genjiro Ohmi Method of determining the astigmatic power and the power for an intraocular lens, for a toric intraocular lens

Also Published As

Publication number Publication date
JPH0588566B2 (en) 1993-12-22

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