JPH01215034A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01215034A
JPH01215034A JP63041336A JP4133688A JPH01215034A JP H01215034 A JPH01215034 A JP H01215034A JP 63041336 A JP63041336 A JP 63041336A JP 4133688 A JP4133688 A JP 4133688A JP H01215034 A JPH01215034 A JP H01215034A
Authority
JP
Japan
Prior art keywords
electrodes
electrode
chip
continuity
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63041336A
Other languages
Japanese (ja)
Inventor
Tsuneharu Katada
片田 恒春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63041336A priority Critical patent/JPH01215034A/en
Publication of JPH01215034A publication Critical patent/JPH01215034A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Abstract

PURPOSE:To detect the positional deviation of mounting easily and to enable mounting at low cost, by respectively dividing electrodes at a plurality of two ore more of positions in electrodes for joining on a semiconductor mounting substrate into the plural or installing positional-displacement detecting electrodes around each junction electrode. CONSTITUTION:Junction electrodes at two positions positioned at the opposite angles of an IC chip 3 in electrodes 2 for joining formed onto a substrate 1 are divided into four of electrodes 2a, 2b, 2c, 2d and 2e, 2f, 2g, 2h respectively while test pins 9 are connected to the junction electrodes 2a-2h on the substrate 1, a checker 8 deciding mutual continuity or non-continuity among each electrode is connected, and sections among respective electrode are checked at all times. When the position of a bump electrode 4 is displaced, sections among the electrodes 2a-2b-2c are decided to be continuity, 2d is decided to be non- continuity, and positional deviation is determined. Accordingly, the IC chip 3 is fixed under the state, in which the continuity of sections among the electrodes 2a-2d and sections among the electrodes 2e-2h is decided, in the adjustment of the location of the IC chip 3.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は電子機器に使用される集積回路素子(以下IC
と呼ぶ。)の実装基板に関するものであって、具体的に
はICチップを直接基板に実装するフリップチップ実装
工法における実装基板に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to integrated circuit elements (hereinafter referred to as IC) used in electronic equipment.
It is called. ), and specifically relates to a mounting board in a flip-chip mounting method in which an IC chip is directly mounted on a board.

従来の技術 近年、電子機器のIC実装技術においてはめざましい進
歩があり、特にICチップの直接実装工法が使用されて
来ている。
BACKGROUND OF THE INVENTION In recent years, there has been remarkable progress in IC mounting technology for electronic devices, and in particular, direct mounting methods for IC chips have been used.

以下図面を参照しながら、上述した従来の半導体装置に
ついて説明する。
The conventional semiconductor device described above will be described below with reference to the drawings.

第4図は従来の半導体装基板へのICチップ実装状態を
示す断面図、第6図は電極配置の平面図、第6図は実装
時におけるモデル図である。
FIG. 4 is a cross-sectional view showing a state in which an IC chip is mounted on a conventional semiconductor board, FIG. 6 is a plan view of electrode arrangement, and FIG. 6 is a model diagram at the time of mounting.

第4図において、1は基板、2は基板上の接合用電極ζ
はICチップ、4はICチップのバンプ電極である。
In Fig. 4, 1 is the substrate, 2 is the bonding electrode ζ on the substrate.
is an IC chip, and 4 is a bump electrode of the IC chip.

ICテップ3には、金やはんだ等の材料による接合用の
バンプ電極が形成されている。一方、基板1にはその表
面に接合用電極2が形成され、その配置は第6図に示す
如(ICチップ3のバンプ電極に対応している。
The IC tip 3 is formed with bonding bump electrodes made of a material such as gold or solder. On the other hand, bonding electrodes 2 are formed on the surface of the substrate 1, and the arrangement thereof is as shown in FIG. 6 (corresponding to the bump electrodes of the IC chip 3).

以上のように構成された半導体装基板について、以下そ
の実装方法について説明する。
A mounting method for the semiconductor board configured as described above will be described below.

まず、準備されたICチップ3は装着用のコレット5に
よって吸着された後、装着すべき基板1の接合電極付近
に運はれる。次にバンプ電極4と基板の接合電極2との
位置合せを行なうが、第6図に示すようにミラー6を介
して人間の目(あるいはテレビカメラ)7によってこの
位置を確認し、合わせを行なう。その後、コレット6を
押し下げてICチップ3を基板1に固着し、バンプ電極
4と接合用電極4とを接合していた。(この時、通常は
加圧、加熱、超音波振動を加えて電極を接合する。)発
明が解決しようとする課題 しかしながら上記のような構成では、ICチップ3の位
置合わせにおいて、バンプ電極3の高さは、わずか10
0ミフロン〜10ミクロン程度であるため、ミラー6を
介して側面よりの監視は非常にむつかしい。このため、
従来は複数方向からの監視や周辺に位置合わせマーク等
を併用し1位置合わせを行なっていたが精度が非常に悪
く、第7図に示すような位置ズレを生じることが多かっ
た。この様に位置ズレを生じるとショートやオープンと
いった不良を起こしたり、電極間の間隙が小さくなるこ
とから信頼性を損なうことにもなっていた。また位置合
わせの精度を上げようとすると多大の工数がかかり、コ
スト上昇になったり、バンプ電極3の高密度化に対応し
きれないというような多くの問題点を有していた。
First, the prepared IC chip 3 is attracted by the collet 5 for mounting, and is then carried to the vicinity of the bonding electrode of the substrate 1 to be mounted. Next, the bump electrode 4 and the bonding electrode 2 of the substrate are aligned, but as shown in FIG. 6, this position is confirmed with the human eye (or a television camera) 7 through a mirror 6, and the alignment is performed. . Thereafter, the collet 6 was pushed down to fix the IC chip 3 to the substrate 1, and the bump electrodes 4 and the bonding electrodes 4 were bonded. (At this time, the electrodes are usually bonded by applying pressure, heating, or ultrasonic vibration.) Problems to be Solved by the Invention However, in the above configuration, when aligning the IC chip 3, the bump electrodes 3 are The height is only 10
Since the diameter is about 0 to 10 microns, it is very difficult to monitor from the side through the mirror 6. For this reason,
Conventionally, single positioning has been performed by monitoring from multiple directions and using positioning marks on the periphery, but the accuracy is very poor and positional deviations as shown in FIG. 7 often occur. Such misalignment can cause defects such as short circuits and opens, and can also reduce reliability because the gap between the electrodes becomes smaller. In addition, when trying to improve the accuracy of alignment, it requires a large number of man-hours, resulting in an increase in cost, and there are many problems such as the inability to cope with the increase in the density of the bump electrodes 3.

本発明は上記問題点に鑑み、簡単な構成で容易に位置合
わせができる半導体装基板を提供するものである。
In view of the above-mentioned problems, the present invention provides a semiconductor mounting substrate that has a simple structure and can be easily aligned.

課題を解決するための手段 上記問題点を解決するために本発明の半導体装基板は、
バンプ電極に対応する接合用電極の内、少なくとも2つ
以上の個所において、その接合用電極パターンを少なく
とも2つ以上に分割する構成、あるいは接合用電極の周
囲に各々第2の電極を配置した構成を備えたものである
Means for Solving the Problems In order to solve the above-mentioned problems, the semiconductor mounting substrate of the present invention has the following features:
A configuration in which the bonding electrode pattern is divided into at least two parts at at least two or more locations among the bonding electrodes corresponding to the bump electrodes, or a configuration in which a second electrode is arranged around each bonding electrode. It is equipped with the following.

作  用 本発明は上記した構成によって、分割された同一個所の
電極相互間の電気的通電、非導通を監視しながら位置合
わせを行なうことができ、バッグ電極が分割された接合
用電極間にがさなった状態、あるいは特定条件の重なり
をした状態を正位置として検出でき、位置ズレ防止でき
る。また、接合電極の周囲に第2の電極を配置した場合
は、この第2の電極を位置ズレ検出電極として使用し、
接合用電極との電気的導通、非導通を監視しながら位置
合わせを行なうことができ、バンプ電極が接合用電極と
検出用の第2の電極間にまたがった状態を位置ズレとし
て検出することができることから位置ズレを防止できる
Effect: With the above-described configuration, the present invention can perform positioning while monitoring electrical conduction and non-conduction between the divided electrodes at the same location, and the bag electrode can be aligned between the divided bonding electrodes. It is possible to detect as the correct position a state in which the position is incorrect, or a state in which specific conditions overlap, thereby preventing positional deviation. In addition, when a second electrode is placed around the bonding electrode, this second electrode is used as a positional deviation detection electrode,
Positioning can be performed while monitoring electrical conduction or non-continuity with the bonding electrode, and a state in which the bump electrode straddles between the bonding electrode and the second detection electrode can be detected as a positional deviation. This allows you to prevent misalignment.

実施例 以下、本発明の一実施例の半導体装置につりて、図面を
参照しながら説明する。
Embodiment Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

第1図(、)は本発明の第1の実施例における半導体装
基板の平面図を示すものである。第1図(−)において
2a、2b、2c、2dは第1の接合電極を4分割した
電極、2@ 、2f 、2q 、2hは第2の接合電極
を4分割した電極である。1は基板、2は他の接合用電
極、3はICチップ、4はバンプ電極であり、これらは
従来と同じ構成である。
FIG. 1(,) shows a plan view of a semiconductor packaging substrate in a first embodiment of the present invention. In FIG. 1 (-), 2a, 2b, 2c, and 2d are electrodes obtained by dividing the first bonding electrode into four, and 2@, 2f, 2q, and 2h are electrodes obtained by dividing the second bonding electrode into four. 1 is a substrate, 2 is another bonding electrode, 3 is an IC chip, and 4 is a bump electrode, which have the same structure as the conventional one.

以上のように構成された半導体装基板について、以下第
1図(、) 、 (b)、第2図及び第3図を用いてそ
の動作を説明する。
The operation of the semiconductor substrate constructed as described above will be explained below with reference to FIGS.

第1図(、)は基板1に形成された接合用電極2のうち
、ICチップ3の対角に位置する2個所の接合電極を4
分割にした状態を示し、バンプ電極4がそれぞれの電極
2a、2b、20,2d、及び2・、2f、2g、2h
に重なった状態である。
FIG. 1 (,) shows two bonding electrodes located diagonally of the IC chip 3 among the bonding electrodes 2 formed on the substrate 1.
The bump electrode 4 is shown divided into the respective electrodes 2a, 2b, 20, 2d, 2., 2f, 2g, 2h.
It is in a state of overlapping.

ICチップ3の実装方法は第3図に示すようにICチッ
プ装着用コレット6にICチップ3を吸着した後、基板
1に運ばれる。一方、基板1の接合電極2a〜2hには
テストピン9が接続されており。
The method for mounting the IC chip 3 is as shown in FIG. 3, in which the IC chip 3 is attracted to an IC chip mounting collet 6 and then transferred to the substrate 1. On the other hand, test pins 9 are connected to the bonding electrodes 2a to 2h of the substrate 1.

このテストピンは各電極間相互の導通働非導通を判定す
るチエッカ−8が結線され、常時各電極間のチエツクを
行なっている。今、第1図(ロ)に示す様にバンプ電極
が位置ズレを生じている時は、電極2a−2b−2c間
は導通と判定されるが、2dは非導通と判定され、位置
ズレであることが判明する。従ってICチップ3の位置
調整においては、との導通チエッカ−の判定を確認し、
電極2a〜2d間、及び20〜2h間が導通判定された
状態でICチップ3を固着すること−によって位置ずれ
を生じることなく、実装できることになる。
A checker 8 is connected to this test pin to determine whether the electrodes are mutually conductive or non-conductive, and constantly checks between the electrodes. Now, when the bump electrodes are misaligned as shown in FIG. Something turns out to be true. Therefore, when adjusting the position of the IC chip 3, check the continuity checker's judgment with the
By fixing the IC chip 3 in a state where conductivity is determined between the electrodes 2a to 2d and between the electrodes 20 to 2h, it is possible to mount the IC chip 3 without causing positional deviation.

以上のように本実施例によれば、接合電極の2個所の電
極を分割し、各々の電極間の導通・非導通をチエツクす
ることにより、ICチップ装着の位置ズレを容易に検出
でき、位置ズレを生じることなく実装することができる
。また、位置ズレ検出が電気的に行なえることから、I
Cチップ装着装置の位置制御が容易に行なえ、従来に比
較し著しく低コストの装着装置が実現できるという効果
がある。(従来の位置制御はテレビカメラ等の映像情報
で行なっており、装置コストが多大なものであった。) 以下本発明の第2の実施例について図面を参照しながら
説明する。
As described above, according to this embodiment, by dividing the two electrodes of the bonding electrode and checking the conduction/non-continuity between each electrode, it is possible to easily detect the misalignment of the IC chip mounting position. It can be implemented without causing any misalignment. In addition, since positional deviation detection can be performed electrically, I
The position of the C-chip mounting device can be easily controlled, and the cost of mounting the C-chip mounting device is significantly lower than that of the conventional method. (Conventional position control was performed using video information from a television camera or the like, and the cost of the device was considerable.) A second embodiment of the present invention will be described below with reference to the drawings.

第2図は本発明の第2の実施例を示す半導体装基板の平
面図である。同図において、10a。
FIG. 2 is a plan view of a semiconductor substrate showing a second embodiment of the present invention. In the figure, 10a.

10bは接合用電極2の周囲に設けた第2の検出電極で
ある。尚、他の接合用電極は省略しである。
10b is a second detection electrode provided around the bonding electrode 2. Note that other bonding electrodes are omitted.

上記のように構成された半導体装基板について、以下そ
の動作を説明する。
The operation of the semiconductor substrate configured as described above will be described below.

ICチップ3の実装方法は前記第1の実施例(第3図)
で述べたものと同様であるが、位置ズレの検出が異なる
。まず、テストピン9は接合用電極2と検出電極10 
a及び1ob間に設けられ、導通・非導通チエッカ−8
に接続されている。今、ICチップ3が位置ズレを生じ
ている場合はバンプ電極4が接合用W、極2と検出電極
10a、あるいは10bに重なる為、チエッカ−8は接
合用電極〜検出電極間の導通を判定し、位置ズレが生じ
ていることを認識することになる。
The method of mounting the IC chip 3 is the same as that of the first embodiment (Fig. 3).
This method is similar to that described above, but the detection of positional deviation is different. First, the test pin 9 is connected to the bonding electrode 2 and the detection electrode 10.
Continuity/non-continuity checker 8 provided between a and 1ob
It is connected to the. If the IC chip 3 is misaligned, the bump electrode 4 overlaps the bonding W, pole 2, and detection electrode 10a or 10b, so the checker 8 determines continuity between the bonding electrode and the detection electrode. However, it is recognized that a positional shift has occurred.

以上のように、接合電極の周囲に第2の電極を設けたこ
とにより、この第2の電極を位置ズレ検出電極として利
用でき、ICチップの装着位置ズレを容易に判定できる
As described above, by providing the second electrode around the bonding electrode, this second electrode can be used as a positional deviation detection electrode, and the mounting positional deviation of the IC chip can be easily determined.

なお、第1の実施例、第2の実施例とも対角位置の接合
用電極を分割したり、周囲に検出電極を設けたりしたが
、別の位置や更に数を増やしたり、複数の検出電極を設
けても、効果は同様に得られるものである。
In addition, in both the first and second embodiments, the bonding electrodes at diagonal positions were divided and detection electrodes were provided around them. Even if it is provided, the same effect can be obtained.

発明の効果 以上のように本発明は、半導体装基板上の接合用電極の
内、少なくとも、2個所以上の電極を各々2つ以上に分
割、あるいは各々の接合電極の周囲に第2の位置ズレ検
出電極を設けることにより、ICチップの実装時(フリ
ップチップ実装)における装着位置ズレを容易に検出で
きるものであり、更にはテレビカメラ等の光学系装置を
必要としないで装着−散を構成できることから、著しく
低コストで装着装置が実現でき、電子機器の実装に使用
した時に低コスト実装を可能にするものである。
Effects of the Invention As described above, the present invention has the advantage of dividing at least two or more of the bonding electrodes on a semiconductor substrate into two or more electrodes, or by creating a second positional shift around each bonding electrode. By providing a detection electrode, it is possible to easily detect a mounting position shift during IC chip mounting (flip chip mounting), and furthermore, mounting and dispersion can be configured without the need for an optical system device such as a television camera. Therefore, a mounting device can be realized at extremely low cost, and when used for mounting electronic equipment, low cost mounting is possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(−)は本発明の第1の実施例における半導体装
置の平面図、第1図(b)は第1図(a)の接合電極部
の拡大図、第2図は本発明の第2の実施例における半導
体装置の平面図、第3図は同装置への実装時におけるモ
デル図、第4図は従来のICチップ実装状態の断面図、
第5図は第4図の平面図、第6図は従来のICチップ実
装時における構成図、第7図は従来の半導体装基板への
装着ズレを示す平面図である。 1・・・・・・基板、2・・・・・・接合用電極、2a
〜2h・・・・・・分割された接合用電極、3・・・・
・・ICチップ、4・・・・・・バンプ電極、5・・・
・・・ICチップ装着用コレット、e・・・・・・ミラ
ー等、7・・・・・・人間の目あるいはテレビカメラ、
8・・・・・・導通・非導通チエッカ−19・・・・・
・テストピン。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名あ−
J2h−・−分物ユ粁砕合71震黛3−・−r(す、/
7゛ (”               2      4
−−7L ′デ<掻(b) 6・−くラー 第6図     7.−え間。Bhbu+□>pe6A
f写−一」 4″       − 派     派
FIG. 1(-) is a plan view of a semiconductor device according to a first embodiment of the present invention, FIG. 1(b) is an enlarged view of the junction electrode portion of FIG. 1(a), and FIG. A plan view of the semiconductor device in the second embodiment, FIG. 3 is a model diagram when mounted on the same device, FIG. 4 is a sectional view of a conventional IC chip mounted state,
FIG. 5 is a plan view of FIG. 4, FIG. 6 is a configuration diagram during conventional IC chip mounting, and FIG. 7 is a plan view showing a conventional mounting misalignment on a semiconductor device board. 1... Substrate, 2... Bonding electrode, 2a
~2h... Divided bonding electrode, 3...
...IC chip, 4...bump electrode, 5...
...Collet for IC chip mounting, e...mirror, etc., 7...human eye or television camera,
8...Continuity/non-continuity checker-19...
・Test pin. Name of agent: Patent attorney Toshio Nakao and one other person
J2h--・-bunmonoyu kaikaai 71 shindai 3-・-r(su,/
7゛(” 2 4
--7L 'de<kaki (b) 6・-kura Figure 6 7. -Ema. Bhbu+□>pe6A
f photo-1"4" - sect

Claims (2)

【特許請求の範囲】[Claims] (1)接合用電極上にバンプ電極を形成したICチップ
を上記バンプ電極に対応した基板上の接合用電極に固着
して接続する半導体装置において、基板上に形成された
接合用電極のうち、少なくとも2個所以上の接合用電極
を各々少なくとも2つ以上に分割した電極にすると共に
、分割された接合用電極が、前記バンプ電極を固着する
ことによって相互接続される配置であることを特徴とす
る半導体装置。
(1) In a semiconductor device in which an IC chip having a bump electrode formed on a bonding electrode is firmly connected to a bonding electrode on a substrate corresponding to the bump electrode, among the bonding electrodes formed on the substrate, The bonding electrodes at at least two or more locations are each divided into at least two or more electrodes, and the divided bonding electrodes are arranged to be interconnected by fixing the bump electrodes. Semiconductor equipment.
(2)基板の接合用電極のうち、少なくとも2個所以上
の接合用電極の周囲に、各々第2の電極を配置したこと
を特徴とする特許請求の範囲第1項記載の半導体装置。
(2) The semiconductor device according to claim 1, wherein second electrodes are arranged around at least two bonding electrodes of the bonding electrodes of the substrate.
JP63041336A 1988-02-24 1988-02-24 Semiconductor device Pending JPH01215034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63041336A JPH01215034A (en) 1988-02-24 1988-02-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63041336A JPH01215034A (en) 1988-02-24 1988-02-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01215034A true JPH01215034A (en) 1989-08-29

Family

ID=12605678

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63041336A Pending JPH01215034A (en) 1988-02-24 1988-02-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01215034A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6111628A (en) * 1997-03-06 2000-08-29 Sharp Kabushiki Kaisha Liquid crystal display device including plural bump electrodes
US7707716B2 (en) 2006-05-10 2010-05-04 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing build-up printed circuit board
JP2010234553A (en) * 2009-03-30 2010-10-21 Brother Ind Ltd Driving unit and manufacturing method thereof
CN103380492A (en) * 2011-02-24 2013-10-30 株式会社村田制作所 Electronic-component-mounting structure
JP2014229664A (en) * 2013-05-20 2014-12-08 オリンパス株式会社 Semiconductor device and method and device for positioning semiconductor device
JP2015111061A (en) * 2013-12-06 2015-06-18 日本電信電話株式会社 Joining position inspection system and method, and circuit board

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4983860A (en) * 1972-12-22 1974-08-12
JPS6295838A (en) * 1985-10-23 1987-05-02 Hitachi Ltd Connection structure for ceramic substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4983860A (en) * 1972-12-22 1974-08-12
JPS6295838A (en) * 1985-10-23 1987-05-02 Hitachi Ltd Connection structure for ceramic substrate

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6111628A (en) * 1997-03-06 2000-08-29 Sharp Kabushiki Kaisha Liquid crystal display device including plural bump electrodes
US7707716B2 (en) 2006-05-10 2010-05-04 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing build-up printed circuit board
JP2010234553A (en) * 2009-03-30 2010-10-21 Brother Ind Ltd Driving unit and manufacturing method thereof
CN103380492A (en) * 2011-02-24 2013-10-30 株式会社村田制作所 Electronic-component-mounting structure
JP2014229664A (en) * 2013-05-20 2014-12-08 オリンパス株式会社 Semiconductor device and method and device for positioning semiconductor device
US10446501B2 (en) 2013-05-20 2019-10-15 Olympus Corporation Semiconductor device, method of positioning semiconductor device, and positioning apparatus for semiconductor device
JP2015111061A (en) * 2013-12-06 2015-06-18 日本電信電話株式会社 Joining position inspection system and method, and circuit board

Similar Documents

Publication Publication Date Title
TW512498B (en) Semiconductor device, method of manufacture thereof, circuit board, and electronic device
TWI618217B (en) Method for manufacturing semiconductor device
JPH08504036A (en) Area array wiring chip TAB test
US7960837B2 (en) Semiconductor package
KR20080037681A (en) Semiconductor chip, method of manufacturing semiconductor chip, and semiconductor device
US5616931A (en) Semiconductor device
JPH01215034A (en) Semiconductor device
US5138429A (en) Precisely aligned lead frame using registration traces and pads
JP3833124B2 (en) Display device
JP2692620B2 (en) Multi-chip module mounting structure
JP6348626B2 (en) Manufacturing method of semiconductor device
JP2833174B2 (en) Semiconductor device and mounting method thereof
JP3178784B2 (en) Inspection apparatus and inspection method for semiconductor package substrate
JPH07302821A (en) Integrated circuit testing device
JPH08340164A (en) Surface mounting structure of bga type package
JPH04215450A (en) Semiconductor integrated circuit device
JPH10123176A (en) Probe substrate for inspecting bare chip and bare chip inspection system
JPH09115949A (en) Electronic device with position deviation inspection pattern and its inspection method
JPH0829454A (en) Test card of semiconductor chip and testing method of semiconductor chip
JPH08153995A (en) Method for aligning semiconductor device
JPS6292342A (en) Semiconductor package for surface mounting
JP2704236B2 (en) Method of bonding semiconductor chip to film carrier
JPH01194430A (en) Tape carrier for tab
JPH09269351A (en) Electrical connection inspection device for circuit board
JP2002176125A (en) Semiconductor device, mounting method of semiconductor element, alignment method thereof