JPS6292342A - Semiconductor package for surface mounting - Google Patents
Semiconductor package for surface mountingInfo
- Publication number
- JPS6292342A JPS6292342A JP60232659A JP23265985A JPS6292342A JP S6292342 A JPS6292342 A JP S6292342A JP 60232659 A JP60232659 A JP 60232659A JP 23265985 A JP23265985 A JP 23265985A JP S6292342 A JPS6292342 A JP S6292342A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor package
- mounting
- board
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09072—Hole or recess under component or special relationship between hole and component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10568—Integral adaptations of a component or an auxiliary PCB for mounting, e.g. integral spacer element
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/167—Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は2例えばプリント基板のように表面に導体パ
ターンを有する基板の表面の所定位置に実装され、導体
パターンにリード線が接続される表面実装用半導体パッ
ケージに関する。[Detailed Description of the Invention] [Field of Industrial Application] This invention is mounted at a predetermined position on the surface of a substrate having a conductive pattern on the surface, such as a printed circuit board, and a surface to which a lead wire is connected to the conductive pattern. Regarding semiconductor packages for mounting.
従来の表面実装用半導体パッケージの一例である周知の
80F (8moll 0utput Line Pa
ckage )の外形図を第4図に示す。同図において
、(1)は半導体(図示せず)を封入しているモールド
で2例えばプラスチック等が使用される。(2)は上記
封入された半導体との信号の入出力を行ったり、該半は
上記リード線(2)に順番に番号をつけるための位置マ
ークである。The well-known 80F (8mol 0output Line Pa) is an example of a conventional surface mount semiconductor package.
Fig. 4 shows the outline of the ckage). In the figure, (1) is a mold that encapsulates a semiconductor (not shown), and (2) is made of, for example, plastic. (2) is a position mark for inputting and outputting signals with the encapsulated semiconductor, and the other half is a position mark for sequentially numbering the lead wires (2).
第5図は上記モールド+11. IJ−ド線(2)、
及び位置マーク(3)を有する表面実装用半導体パッケ
ージ(8)(以下単にパッケージと記す)の実装工程を
示す図であって、同図において、(4)は上記パッケー
ジ(8)を実装するための基板2例えばプリント基板で
あって、(6)はその基板(4)の表面に印刷された導
体パターン、(6)は上記パッケージ(8)を上記基板
(4)上に固定する接着剤、(7)は上記基板(4)上
の導体パターン(5)上に印刷されたクリーム半田であ
る。Figure 5 shows the above mold +11. IJ-do wire (2),
and a position mark (3) (hereinafter simply referred to as the package). The board 2 is, for example, a printed circuit board, and (6) is a conductor pattern printed on the surface of the board (4), (6) is an adhesive for fixing the package (8) on the board (4), (7) is cream solder printed on the conductor pattern (5) on the substrate (4).
次にこのようなパッケージ(8)の実装方法について説
明する。パッケージ(8)は基板(4)上の導体パター
ン(5)に合わせて実装される。この実装には人間が導
体パターン(5)を見て位置合わせをする方法と。Next, a method of mounting such a package (8) will be explained. The package (8) is mounted in alignment with the conductor pattern (5) on the substrate (4). This implementation involves a method in which humans align the positions by looking at the conductor pattern (5).
機械によって予め、この導体パターン(5)の位置を記
憶させておき、その記憶に合わせて自動的に実装する方
法がある。There is a method in which the position of the conductive pattern (5) is memorized in advance by a machine and the mounting is automatically performed according to the memorized information.
一方2表面実装用パッケージ(8)は次の2通勺の方法
によって第5図(a)に示す基板(4)に固定される。On the other hand, the second surface mount package (8) is fixed to the substrate (4) shown in FIG. 5(a) by the following two methods.
その一方法は第5図(bl)(cl)に示すように、接
着剤(6)を用いた方法で、基板(4)上に、パッケー
ジ(8)のモールド(1)の下に位置してまず接着剤を
つけ。One method is to use an adhesive (6), which is placed on the substrate (4) and under the mold (1) of the package (8), as shown in Figures 5 (bl) and (cl). First, apply the adhesive.
次にパッケージ(8)を基板(4)の所定位置に載置し
て基板(4)の所定位置にパッケージ(8)を固定して
おき。Next, the package (8) is placed on a predetermined position on the board (4), and the package (8) is fixed at a predetermined position on the board (4).
この後、各リード線(21(21・・・を導体パターン
(5)に半田付けする。他の方法は第5図(b2)(C
2)に示すようにクリーム半田(7)を用いた方法で、
プリント基板(4)表面の導体パターン(5)のリード
線(2)が接続される部分のみの上に、クリーム半田(
7)を印刷し。After this, each lead wire (21 (21...) is soldered to the conductor pattern (5).Another method is as shown in Fig. 5 (b2) (C
As shown in 2), by the method using cream solder (7),
Apply cream solder (
7) Print out.
その上にパッケージ(8)の各リード線(2)(2)・
・・を置き。On top of that, each lead wire (2) (2) of the package (8)
Place...
赤外線や熱蒸気等によシ加熱することによシ、導上にパ
ッケージ(8)を実装したものを上から見た図である。This is a top view of a package (8) mounted on a conductor by heating with infrared rays, hot steam, or the like.
従来の表面実装用半導体パッケージ(8)を用いた実装
方法だと、プリント基板(4)の表面実装用半導体パッ
ケージ(8)を実装する面は導体パターン(5)があっ
てもほぼ平らであるため1表面実装用半導体パッケージ
(8)を基板(4)上の所定位置に機械的に位置合わせ
をすることができず、また、自動装着装置等を用いて実
装しようとすれば位置合わせのために、極めて高い精度
の自動装置を開発する必要とする。また、半導体パッケ
ージ(8)を基板(4)の所定位置に載置した後も、半
田付けするまでは、半導体パッケージ(8)が基板(4
)に接着剤(6)等で接着されているとはいうものの小
さな振動でも位置ずれを起すなどの問題点があった。つ
まり、第5図(bl)(C1)から理解されるように、
基板(4)上に接着剤(6)を付けた後に、基板+41
に対し半導体パッケージ(8)を位置合わせするため、
接着剤としては遅乾性の接着剤を使用しなければならず
、従って、半田付けするまでの間は接着剤による強固な
接着はされておらず、小さな振動でも位置ずれを起すの
である。In the conventional mounting method using the surface mount semiconductor package (8), the surface of the printed circuit board (4) on which the surface mount semiconductor package (8) is mounted is almost flat even with the conductor pattern (5). Therefore, it is not possible to mechanically align the surface mount semiconductor package (8) to a predetermined position on the board (4), and if you try to mount it using an automatic mounting device, etc., it will be difficult to align it. This requires the development of extremely high-precision automatic equipment. Furthermore, even after the semiconductor package (8) is placed on the board (4), the semiconductor package (8) remains on the board (4) until it is soldered.
) is bonded with an adhesive (6) or the like, but there are problems in that even small vibrations can cause positional displacement. In other words, as understood from Figure 5 (bl) (C1),
After applying the adhesive (6) on the substrate (4), attach the substrate +41
In order to align the semiconductor package (8) against
A slow-drying adhesive must be used as the adhesive; therefore, the adhesive does not provide a strong bond until soldering, and even small vibrations can cause misalignment.
この発明は上述のような問題点を解消するためになされ
たもので2表面実装用半導体パッケージの基板に対する
位置合わせを容易にしかも確実にし、小さな振動でも位
置ずれを起こすことのないようにすることを目的とする
。This invention was made in order to solve the above-mentioned problems. 2. It is possible to easily and reliably align the surface mounting semiconductor package with respect to the substrate, and to prevent misalignment even with small vibrations. With the goal.
この発明に係る表面実装用半導体パッケージは。 A semiconductor package for surface mounting according to the present invention is a semiconductor package for surface mounting.
表面に導体パターンを有する基板の表面の所定位置に実
装され上記導体パターンにリード線が接続される表面実
装用半導体パッケージにおいて、上記基板に係合して上
記基板に対する上記所定位置への位置決め及び位置ずれ
防止をする突起をモールドの上記基板への実装面側に設
けたものである。In a surface mount semiconductor package that is mounted at a predetermined position on the surface of a substrate having a conductive pattern on the surface and has lead wires connected to the conductive pattern, the surface mounting semiconductor package is engaged with the substrate and positioned at the predetermined position with respect to the substrate. A protrusion for preventing displacement is provided on the mounting surface of the mold to the substrate.
この発明における表面実装用半導体パッケージ社、その
実装面側にある突起を、基板内に用意される位置合わせ
用の穴等に係合することによシ。The surface mount semiconductor package company of the present invention is made by engaging the protrusion on the mounting surface side with a positioning hole etc. prepared in the board.
基板上の導体パターンに対する表面実装用半導体パッケ
ージの位置合わせを容易且つ確実にするとともに、実装
後2表面実装用半導体パッケージのリード線を基板上の
導体パターンに接続するまでの間に生じ易い位置ずれを
防止する。Easily and reliably aligns the surface mount semiconductor package with the conductor pattern on the board, and eliminates misalignment that is likely to occur between the time when the lead wires of the two surface mount semiconductor packages are connected to the conductor pattern on the board after mounting. prevent.
以下、この発明の一実施例を第1図〜第3図によって説
明する。第1図は表面実装用半導体パッケージ(8)全
体の外観図で、(a)は平面図、(b)は正面図、(C
)は側面図であって、これら図において、(l)は半導
体を封入しているモールド、(2)は封入された半導体
との信号の入出力を行なったシ、上記封ている。(3)
は上記各リード線(2)に順番に番号をつけるための位
置マーク、(9)はモールド(1)に突設された突起で
、後述の第2図に示された基板(4)への実装面側に設
けられている。An embodiment of the present invention will be described below with reference to FIGS. 1 to 3. FIG. 1 is an external view of the entire surface mounting semiconductor package (8), in which (a) is a plan view, (b) is a front view, and (C
) is a side view; in these figures, (l) is the mold that encapsulates the semiconductor; (2) is the mold that inputs and outputs signals to and from the encapsulated semiconductor; (3)
(9) is a position mark for numbering each lead wire (2) in order, and (9) is a protrusion provided on the mold (1) to attach to the substrate (4) shown in Fig. 2, which will be described later. Provided on the mounting surface side.
第2図は、プリント基板等の基板(4)へ表面実装用半
導体パッケージ(8)を取り付けた状態を示す拡大断面
図、第3図は基板(4)の平面図であって、これらの図
において、(4)は上記半導体パッケージ(8)を実装
するための基板で1例えばプリント基板である。(5)
はこの基板(4)上に印刷された導体パターン、Olは
プリント基板(4)に穿設された位置合わせ用の穴であ
る。FIG. 2 is an enlarged sectional view showing the surface mounting semiconductor package (8) attached to a substrate (4) such as a printed circuit board, and FIG. 3 is a plan view of the substrate (4). , (4) is a substrate for mounting the semiconductor package (8), for example, a printed circuit board. (5)
is a conductor pattern printed on this board (4), and O1 is a hole for alignment drilled in the printed board (4).
第1図(、)(b)(0)に示された表面実装用半導体
パッケージは、第3図に示す基板に、第2図に示すよう
に実装される。基板(4)上に印刷された導体パターン
(5)に2表面実装用半導体パッケージ(8)の各リー
ド線(2)が接続される。基板(4)にあけられた位置
合わせ用の穴α1には2表面実装用の半導体パッケージ
(8)の突起(9)が嵌まる。表面実装用半導体パッケ
ージ(8)を基板(4)に実装するときには、先ず基板
(4)の穴a1がガイドとなり、半導体パッケージ(8
)は基板(4)上の正しい位置に実装され位置決めされ
る。The surface mount semiconductor package shown in FIGS. 1(,)(b)(0) is mounted on the substrate shown in FIG. 3 as shown in FIG. 2. Each lead wire (2) of the two surface-mount semiconductor packages (8) is connected to a conductor pattern (5) printed on the substrate (4). The protrusion (9) of the two-surface mounting semiconductor package (8) fits into the positioning hole α1 drilled in the substrate (4). When mounting the surface mounting semiconductor package (8) on the substrate (4), first, the hole a1 of the substrate (4) serves as a guide and the semiconductor package (8) is mounted on the substrate (4).
) is mounted and positioned at the correct position on the substrate (4).
このように−変圧しい位置に実装されると、多少の振動
では、半導体パッケージ(8)の基板(4)に対する位
置ずれは生じない。If the semiconductor package (8) is mounted in a stable position in this manner, even slight vibrations will not cause the semiconductor package (8) to shift relative to the substrate (4).
なお、上記実施例では突起(9)の位置はモールド+1
1の平面的に見た中心に設けたものを示したが。In the above embodiment, the position of the protrusion (9) is mold +1.
The one provided at the center of 1 when viewed from above is shown.
中心に設ける必要はなく、モールド(1)の基板(4)
への実装面側であればどの位置に設けてもよい。また、
上記実施例では、突起(9)の形状が円すい形のものを
例示したが、突起(9)の形状は円錐形である必要はな
く2円柱形や、三角錐等、所謂突起であればよい。また
上記実施例では、突起(9)はモールド(1)の実装面
側に1個所だけ設けたものを示したが、1個所だけでな
く、複数個所に設けてもよい。It is not necessary to provide it in the center, but on the substrate (4) of the mold (1).
It may be provided at any position on the mounting surface side. Also,
In the above embodiment, the shape of the protrusion (9) is conical, but the shape of the protrusion (9) does not have to be conical, but may be a so-called protrusion such as a bicylindrical shape or a triangular pyramid. . Further, in the above embodiment, the protrusion (9) is provided at only one location on the mounting surface side of the mold (1), but it may be provided at a plurality of locations instead of only at one location.
以上のように、この発明は9表面に導体パターンを有す
る基板の表面の所定位置に実装され上記導体パターンに
リード線が接続される表面実装用半導体パッケージにお
いて、上記基板に係合して上記基板に対する上記所定位
置への位置決め及び位置ずれ防止をする突起をモールド
の上記基板への実装面側に設けたので2表面実装用半導
体パッケージの基板への実装時の位置合わせを容易且つ
確実にでき、しかも2位置合わせ後、半導体パッケージ
のリード線を基板の導体パターンに接続するまでの間に
多少の振動が作用しても、その振動による半導体パッケ
ージの位置ずれが生じず、従って半導体パッケージの各
リード線と基板の導体パターンとの接続が良好に行なわ
れ、更に、半導体パッケージの基板への装着に自動装着
機等を使用する場合にも、上述のように、半導体パッケ
ージの基板への位置決めが容易且つ正確に行なわれるの
で、自動装着機自体に位置決めのための高価な機能装置
を特別に設ける必要がなく、安価な自動装着機で半導体
パッケージを基板上の所定位置に正確に位置させ、半導
体パッケージのリード線を基板の導体パターンに正確に
確実に接続できる等の効果がある。As described above, the present invention provides a surface mount semiconductor package that is mounted at a predetermined position on the surface of a substrate having a conductive pattern on its surface and has lead wires connected to the conductive pattern. Since a protrusion for positioning the semiconductor package at the predetermined position and preventing displacement is provided on the surface of the mold to be mounted on the substrate, the positioning of the semiconductor package for surface mounting on the substrate can be easily and reliably performed. Moreover, even if some vibration occurs after the two positions are aligned and before the lead wires of the semiconductor package are connected to the conductor pattern of the board, the semiconductor package will not be misaligned due to the vibration, and each lead of the semiconductor package will not be misaligned. The connection between the wire and the conductor pattern on the board is good, and furthermore, when using an automatic mounting machine etc. to mount the semiconductor package on the board, it is easy to position the semiconductor package on the board as described above. In addition, since it is performed accurately, there is no need to specially equip the automatic mounting machine itself with an expensive function device for positioning, and the semiconductor package can be accurately positioned at a predetermined position on the board using an inexpensive automatic mounting machine. This has advantages such as being able to accurately and reliably connect the lead wires to the conductor pattern on the board.
第1図〜第3図はこの発明の一実施例を示す図で、第1
図は外観図であり、(a)は平面図、(b)は正面図、
(C)は側面図、第2図は表面実装用半導体パッケージ
を基板に取り付けた状態を示す拡大断面図、第3図は基
板の平面図である。第4図は従来の表面実装用半導体パ
ッケージ例の外観図で、(a)は平面図、(b)は正面
図、(C)は側面図、第5図は従来の表面実装用半導体
パッケージの基板への実装・接続工程を示す図で、(a
)は半導体パッケージを実装する前の基板の側面図、
(bl)は基板へ接着剤を付けた状態を示す側面図、
(cl)は接着剤によって半導体パッケージを基板の所
定位置に実装した状態を示す側面図、 (b2)は基板
の導体パターン上にクリーム半田を付けた状態を示す側
面図、 (c2)は基板の導体パターン上にクリーム半
田を介して半導体パッケージのリード線を接続した状態
を示す側面図、(d)は半導体パッケージを基板に実装
・接続した状態を部分的に示す平面図である。
図において、(1)はそ−ルド、(2)はリード線、(
4)は基板、(5)は導体パターン、(8)は表面実装
用半導体パッケージ、(9)は突起、帥は穴である。
なお図中同一符号は同−又は相当部分を示す。Figures 1 to 3 are diagrams showing one embodiment of the present invention.
The figure is an external view, (a) is a plan view, (b) is a front view,
2(C) is a side view, FIG. 2 is an enlarged sectional view showing the surface mounting semiconductor package attached to the board, and FIG. 3 is a plan view of the board. Fig. 4 is an external view of an example of a conventional surface mount semiconductor package, in which (a) is a plan view, (b) is a front view, (C) is a side view, and Fig. 5 is an example of a conventional surface mount semiconductor package. This is a diagram showing the process of mounting and connecting to the board. (a
) is a side view of the board before mounting the semiconductor package,
(bl) is a side view showing the state in which adhesive is applied to the board;
(cl) is a side view showing the semiconductor package mounted in a predetermined position on the board with adhesive, (b2) is a side view showing cream solder applied to the conductor pattern of the board, and (c2) is the side view of the board. FIG. 3(d) is a side view showing a state in which lead wires of a semiconductor package are connected to a conductor pattern via cream solder; FIG. In the figure, (1) is a solder wire, (2) is a lead wire, (
4) is a substrate, (5) is a conductor pattern, (8) is a surface mounting semiconductor package, (9) is a protrusion, and 3 is a hole. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
装され上記導体パターンにリード線が接続される表面実
装用半導体パッケージにおいて、上記基板に係合して上
記基板に対する上記所定位置への位置決め及び位置ずれ
防止をする突起をモールドの上記基板への実装面側に設
けたことを特徴とする表面実装用半導体パッケージ。In a surface mount semiconductor package that is mounted at a predetermined position on the surface of a substrate having a conductive pattern on the surface and has lead wires connected to the conductive pattern, the surface mounting semiconductor package is engaged with the substrate and positioned at the predetermined position with respect to the substrate. A semiconductor package for surface mounting, characterized in that a protrusion for preventing displacement is provided on the mounting surface side of the mold to the substrate.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60232659A JPS6292342A (en) | 1985-10-17 | 1985-10-17 | Semiconductor package for surface mounting |
KR1019860006340A KR870004506A (en) | 1985-10-17 | 1986-07-31 | Semiconductor Package for Surface Packaging |
DE19863635154 DE3635154A1 (en) | 1985-10-17 | 1986-10-13 | Device having a semiconductor component mounted on a substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60232659A JPS6292342A (en) | 1985-10-17 | 1985-10-17 | Semiconductor package for surface mounting |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6292342A true JPS6292342A (en) | 1987-04-27 |
Family
ID=16942773
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60232659A Pending JPS6292342A (en) | 1985-10-17 | 1985-10-17 | Semiconductor package for surface mounting |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPS6292342A (en) |
KR (1) | KR870004506A (en) |
DE (1) | DE3635154A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8641460B2 (en) | 2010-01-29 | 2014-02-04 | Omron Corporation | Mounting component, electronic device, and mounting method |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE68925922T2 (en) * | 1988-05-30 | 1996-09-05 | Canon Kk | Electrical circuit apparatus |
DE10031762A1 (en) * | 2000-06-29 | 2002-01-10 | Bosch Gmbh Robert | Electronic component |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE7322421U (en) * | 1973-06-15 | 1973-12-13 | Doehler P | SOCKET FOR INTEGRATED CIRCUIT COMPONENTS WITH A HOUSING, FROM WHICH TWO PARALLEL ROWS OF CONTACT PLUG PINS EXTRACT |
FR2538166A1 (en) * | 1982-12-17 | 1984-06-22 | Thomson Csf | ENCAPSULATION MICROBOITIER FOR AN ELECTRONIC COMPONENT HAVING A PLURALITY OF REPLICATED CONNECTIONS |
-
1985
- 1985-10-17 JP JP60232659A patent/JPS6292342A/en active Pending
-
1986
- 1986-07-31 KR KR1019860006340A patent/KR870004506A/en not_active Application Discontinuation
- 1986-10-13 DE DE19863635154 patent/DE3635154A1/en not_active Ceased
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8641460B2 (en) | 2010-01-29 | 2014-02-04 | Omron Corporation | Mounting component, electronic device, and mounting method |
Also Published As
Publication number | Publication date |
---|---|
KR870004506A (en) | 1987-05-09 |
DE3635154A1 (en) | 1987-04-23 |
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