JPH08153995A - Method for aligning semiconductor device - Google Patents
Method for aligning semiconductor deviceInfo
- Publication number
- JPH08153995A JPH08153995A JP6292466A JP29246694A JPH08153995A JP H08153995 A JPH08153995 A JP H08153995A JP 6292466 A JP6292466 A JP 6292466A JP 29246694 A JP29246694 A JP 29246694A JP H08153995 A JPH08153995 A JP H08153995A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- line
- semiconductor element
- wiring board
- aligning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半田バンプの付いた半
導体装置の搭載基板上への位置合わせ方法の技術に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for aligning a semiconductor device having solder bumps on a mounting substrate.
【０００２】[0002]
【従来の技術】従来、このような分野の技術としては、
例えば、以下に示すようなものがあった。図３はかかる
従来の第１の半田バンプの付いた半導体素子の位置合わ
せ方法の説明図である。2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there were the following. FIG. 3 is an explanatory view of such a conventional alignment method for a semiconductor element having a first solder bump.
【０００３】図３（ａ）に示すように、搭載基板３と半
導体素子１との間に、搭載基板側と半導体素子側を同時
に写すことのできるカメラ２を入れる。カメラ２で搭載
基板３上のパッド４と半導体素子１側のバンプ５を同時
に写し、１つの画面上に合成して映し出す。人間または
機械が、パッド４と対応するバンプ５が一致するように
搭載基板３又は半導体素子１を動かして調整する。As shown in FIG. 3A, a camera 2 capable of simultaneously photographing the mounting substrate side and the semiconductor element side is inserted between the mounting substrate 3 and the semiconductor element 1. The pads 4 on the mounting substrate 3 and the bumps 5 on the semiconductor element 1 side are simultaneously imaged by the camera 2 and are combined and displayed on one screen. A human or machine moves and adjusts the mounting substrate 3 or the semiconductor element 1 so that the pads 4 and the corresponding bumps 5 are aligned with each other.
【０００４】両者が一致したら、図３（ｂ）に示すよう
に、カメラ２を引き抜き、半導体素子１を搭載基板３に
搭載する。また、図４は従来の第２の半田バンプの付い
た半導体素子の位置合わせ方法の説明図である。図４
（ａ）に示すように、予め搭載基板２の半導体素子搭載
予定位置に半導体素子１の形状と同一の、または形状が
分かるような線６を引いておく。その後、図４（ｂ）に
示すように、半導体素子１を予め引かれた線６に合うよ
うに搭載する。If the two match, the camera 2 is pulled out and the semiconductor element 1 is mounted on the mounting substrate 3, as shown in FIG. In addition, FIG. 4 is an explanatory diagram of a conventional method for aligning a semiconductor element having a second solder bump. FIG.
As shown in (a), a line 6 that is the same as the shape of the semiconductor element 1 or the shape of which can be understood is drawn in advance at the position where the semiconductor element is to be mounted on the mounting substrate 2. After that, as shown in FIG. 4B, the semiconductor element 1 is mounted so as to be aligned with the previously drawn line 6.
【０００５】このように、従来、半田バンプの付いた半
導体素子の基板への搭載位置合わせは、上記第１及び第
２の方法が採られていた。As described above, conventionally, the above-mentioned first and second methods have been adopted for the mounting alignment of the semiconductor element having the solder bump on the substrate.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記し
た従来の半田バンプの付いた半導体素子の基板への搭載
位置合わせ方法では、以下の問題がある。 （１）第１の方法（図３参照）によると、ほぼ確実に半
導体素子のバンプをパッド上に搭載することができる
が、２方向を同時に写すことのできるカメラが必要にな
り、製造設備が高価になってしまう。However, the above-described conventional method for mounting and mounting a semiconductor element having solder bumps on a substrate has the following problems. (1) According to the first method (see FIG. 3), the bumps of the semiconductor element can be almost certainly mounted on the pad, but a camera capable of simultaneously capturing two directions is required, and the manufacturing equipment is required. It becomes expensive.
【０００７】（２）第２の方法（図４参照）によると、
チップの外形で位置合わせをすることになり、チップの
ダイシングの精度が悪いと、半導体素子のバンプをパッ
ド上に正確に搭載することが困難である。本発明は、上
記問題点を除去し、半導体装置の裏面に予めバンプの配
列に合わせて線を引いておき、一方、配線基板上にも予
めパッドの配列に合わせて線を引いておき、搭載時に上
方から見てそれらの線を合わせることにより、配線基板
上に、半導体装置を簡単かつ確実に搭載することができ
る半導体装置の位置合わせ方法を提供することを目的と
する。(2) According to the second method (see FIG. 4),
Positioning is performed by the outer shape of the chip, and if the dicing accuracy of the chip is poor, it is difficult to accurately mount the bump of the semiconductor element on the pad. The present invention eliminates the above problems and draws a line on the back surface of a semiconductor device in advance according to the arrangement of bumps, while drawing a line on the wiring board in advance according to the arrangement of pads. An object of the present invention is to provide a method for aligning a semiconductor device that can easily and surely mount the semiconductor device on a wiring board by aligning those lines when viewed from above.
【０００８】[0008]
【課題を解決するための手段】本発明は、上記目的を達
成するために、 （１）配線基板への半田バンプの付いた半導体装置の位
置合わせ方法において、半田バンプの付いた半導体装置
をＸ線で透過し、この半導体装置の裏面にレーザーで半
田バンプ配列に合わせた第１の線を付す工程と、前記半
導体装置が搭載される配線基板の裏面にパッド配列に合
わせた第２の線を付す工程と、前記半導体装置の裏面側
に位置する撮像装置により前記第２の線に前記第１の線
を合わせ前記配線基板のパッドに前記半導体装置の半田
バンプを接続する工程とを施すようにしたものである。In order to achieve the above object, the present invention provides: (1) In a method of aligning a semiconductor device having solder bumps on a wiring board, a semiconductor device having solder bumps A step of attaching a first line aligned with the solder bump array to the back surface of the semiconductor device with a laser, and a second line aligned with the pad array on the back surface of the wiring board on which the semiconductor device is mounted. And a step of aligning the first line with the second line by an image pickup device located on the back side of the semiconductor device and connecting a solder bump of the semiconductor device to a pad of the wiring board. It was done.
【０００９】（２）上記（１）記載の半導体装置の位置
合わせ方法において、前記半導体装置は半導体素子であ
り、配線基板は半導体素子のパッケージである。(2) In the method of aligning a semiconductor device described in (1) above, the semiconductor device is a semiconductor element, and the wiring board is a package of the semiconductor element.
【００１０】[0010]
【作用】本発明によれば、上記したように、半導体バン
プの付いた半導体装置の裏面にバンプ配列に合わせて第
１の線を引いておき、一方、配線基板上には予めパッド
配線に合わせて第２の線を引いておく。そこで、半導体
装置の第１の線を配線基板の第２の線に合わせて、配線
基板のパッドに半導体素子の半田バンプを接続する。According to the present invention, as described above, the first line is drawn on the back surface of the semiconductor device having the semiconductor bumps in accordance with the bump arrangement, and on the other hand, the wiring is preliminarily aligned with the pad wiring. And draw the second line. Therefore, the first wire of the semiconductor device is aligned with the second wire of the wiring board, and the solder bumps of the semiconductor element are connected to the pads of the wiring board.
【００１１】なお、ここで、半導体装置（フリップチッ
プ）の表面とは、回路形成面、つまり、半田バンプの付
いている面を言い、半導体装置（フリップチップ）の裏
面とは、回路形成面の反対側の面、つまり、半田バンプ
の付いていない面を言う。Here, the front surface of the semiconductor device (flip chip) means a circuit forming surface, that is, a surface having solder bumps, and the back surface of the semiconductor device (flip chip) means a circuit forming surface. The opposite surface, that is, the surface without solder bumps.
【００１２】[0012]
【実施例】以下、本発明の実施例について図を用いて説
明する。図１は本発明の第１実施例を示す半導体素子の
位置合わせ方法の説明図である。まず、本発明の第１実
施例を図１を参照しながら説明する。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory diagram of a semiconductor element alignment method showing a first embodiment of the present invention. First, a first embodiment of the present invention will be described with reference to FIG.
【００１３】（１）まず、図１（ａ）に示すように、半
田バンプ１１付きの半導体素子１０を用意する。ここ
で、半導体素子１０は所謂フリップチップとよばれるも
ので、この半導体素子１０の表面には、直径１００μｍ
程度の半田バンプ１１がメッキ等で形成されている。な
お、半導体装置（フリップチップ）の表面とは、回路形
成面、つまり、半田バンプの付いている面を言い、半導
体装置（フリップチップ）の裏面とは、回路形成面の反
対側の面、つまり、半田バンプの付いていない面を言
う。(1) First, as shown in FIG. 1A, a semiconductor element 10 with solder bumps 11 is prepared. Here, the semiconductor element 10 is a so-called flip chip, and the surface of the semiconductor element 10 has a diameter of 100 μm.
Some solder bumps 11 are formed by plating or the like. The front surface of the semiconductor device (flip chip) means a circuit formation surface, that is, a surface having solder bumps, and the back surface of the semiconductor device (flip chip) means a surface opposite to the circuit formation surface, that is, , The surface without solder bumps.
【００１４】（２）次に、図１（ｂ）に示すように、そ
の半田バンプ１１付きの半導体素子１０を、表面を下側
に向けてＸ線装置（図示なし）に入れ、透過しながら半
田バンプ１１の配列に合わせて半導体素子１０の裏面１
０ａにレーザーで第１の線１２を書き込む。ここで、第
１の線１２はバンプの配列全てについて描いてもよい
し、また後で位置合わせができる程度の本数でもよい。(2) Next, as shown in FIG. 1 (b), the semiconductor element 10 with the solder bumps 11 is put into an X-ray device (not shown) with the surface facing downward, and while passing through. The back surface 1 of the semiconductor element 10 according to the arrangement of the solder bumps 11.
The first line 12 is written with a laser on 0a. Here, the first line 12 may be drawn for the entire bump array, or the number may be such that alignment can be performed later.
【００１５】（３）図１（ｃ）に示すように、配線基板
２０側も同様に、パッド２１の配列に合わせて予め第２
の線２２を引くが、これもパッド２１の配列全てについ
て描いてもよいし、また後で位置合わせができる程度の
本数でもよい。ただし、第１の線１２と第２の線２２は
それぞれ対応するように形成する。ここで、配線基板２
０とは、主にＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａ
ｇｅ）、ＰＧＡ（Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ）、Ｂ
ＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）などのパッケ
ージの基板を指している。(3) As shown in FIG. 1 (c), the wiring board 20 side is also secondly preliminarily arranged in accordance with the arrangement of the pads 21.
Line 22 is drawn, but this may also be drawn for the entire arrangement of the pads 21, or the number may be such that alignment is possible later. However, the first line 12 and the second line 22 are formed so as to correspond to each other. Here, the wiring board 2
0 is mainly QFP (Quad Flat Packa).
ge), PGA (Pin Grid Array), B
It refers to a substrate of a package such as GA (Ball Grid Array).
【００１６】（４）図１（ｄ）に示すように、予めこの
第１の線１２の引かれた半導体素子１０を、機械によっ
て配線基板２０から上方に離して設置する。 （５）次いで、半導体素子１０上に垂直に設置された撮
像装置としてのカメラ（図示なし）によって、図１
（ｅ）に示すように、第１の線１２と第２の線２２を画
面上に映し出す。機械もしくは人間が画面上で第１の線
１２と第２の線２２が一致するように調整し、その後、
半導体素子１０を降下させて配線基板２０上に搭載す
る。(4) As shown in FIG. 1 (d), the semiconductor element 10 with the first line 12 drawn in advance is installed by a machine so as to be separated upward from the wiring board 20. (5) Next, by using a camera (not shown) as an image pickup device installed vertically on the semiconductor element 10, FIG.
As shown in (e), the first line 12 and the second line 22 are projected on the screen. A machine or human makes adjustments so that the first line 12 and the second line 22 match on the screen, and then
The semiconductor element 10 is lowered and mounted on the wiring board 20.
【００１７】（６）このようにして、図１（ｆ）に示す
ように、配線基板２０のパッド２１に、半導体素子１０
の半田バンプ１１を正確に位置合わせすることによっ
て、正しく接続することができる。次に、本発明の第２
実施例を図２を参照しながら説明する。この実施例で
は、本発明をＢＧＡパッケージに適用した例を示す。(6) In this way, as shown in FIG. 1F, the semiconductor element 10 is attached to the pad 21 of the wiring board 20.
By accurately aligning the solder bumps 11 of 1, the correct connection can be achieved. Next, the second aspect of the present invention
An embodiment will be described with reference to FIG. This embodiment shows an example in which the present invention is applied to a BGA package.
【００１８】（１）まず、図２（ａ）に示すように、半
田バンプ３１付きのＢＧＡパッケージ３０を用意する。
ここで、ＢＧＡパッケージ３０の裏面には直径５００〜
１０００μｍ程度の半田バンプ３１が半田ボール搭載、
印刷等の方法で形成されている。 （２）次に、図２（ｂ）に示すように、その半田バンプ
３１付きのＢＧＡパッケージ３０の表面には、例えば、
ＩＣ等を封止したキャップ３３が存在し、また、既にＢ
ＧＡパッケージ３０の位置決めのための第１の線３４が
書き込まれている。つまり、線３４はＢＧＡパッケージ
３０の作製時にパターンとして予め形成されるものとす
る。(1) First, as shown in FIG. 2A, a BGA package 30 with solder bumps 31 is prepared.
Here, on the back surface of the BGA package 30, a diameter of 500 to
Solder balls 31 with solder bumps 31 of about 1000 μm mounted,
It is formed by a method such as printing. (2) Next, as shown in FIG. 2B, on the surface of the BGA package 30 with the solder bumps 31, for example,
There is a cap 33 that seals the IC, etc.
A first line 34 for positioning the GA package 30 is written. That is, the line 34 is preliminarily formed as a pattern when the BGA package 30 is manufactured.
【００１９】（３）一方、図２（ｃ）に示すように、マ
ザーボード４０側も同様に、パッド４１の配列に合わせ
て予め第２の線４２を引くが、これはパッド４１の配列
全てについて描いてもよいし、また後で位置合わせがで
きる程度の本数でもよい。ただし、第２の線４２と第１
の線３４はそれぞれ対応するように形成する。 （４）図２（ｄ）に示すように、この予め第１の線３４
が引かれたＢＧＡパッケージ３０を、機械によってマザ
ーボード４０から上方に離して設置する。(3) On the other hand, as shown in FIG. 2C, the second line 42 is also drawn in advance on the motherboard 40 side in accordance with the arrangement of the pads 41. This is for all the arrangements of the pads 41. It may be drawn, or the number may be such that it can be aligned later. However, the second line 42 and the first
The lines 34 of are formed so as to correspond to each other. (4) As shown in FIG. 2D, the first line 34 is previously formed.
The BGA package 30 in which is pulled is installed by a machine away from the motherboard 40 upward.
【００２０】（５）次に、ＢＧＡパッケージ３０上に垂
直に設置された撮像装置としてのカメラ（図示なし）に
よって、図２（ｅ）に示すように、ＢＧＡパッケージ３
０の第１の線３４と、マザーボード４０上の第２の線４
２を画面上に映し出す。機械もしくは人間が画面上で第
１の線３４と第２の線４２が一致するように調整し、そ
の後、ＢＧＡパッケージ３０を降下させてマザーボード
４０上に搭載する。(5) Next, as shown in FIG. 2E, the BGA package 3 is mounted on the BGA package 30 by a camera (not shown) vertically installed on the BGA package 30.
0 first line 34 and second line 4 on motherboard 40
Project 2 on the screen. A machine or a person adjusts the first line 34 and the second line 42 on the screen so that they coincide with each other, and then the BGA package 30 is lowered and mounted on the motherboard 40.
【００２１】（６）このようにして、図２（ｆ）に示す
ように、マザーボード４０のパッド４１に、ＢＧＡパッ
ケージ３０の半田バンプ３１を、正確に位置合わせする
ことによって、正しく接続される。このように、ＢＧＡ
パッケージにも適用が可能である。なお、本発明は上記
実施例に限定されるものではなく、本発明の趣旨に基づ
き種々の変形が可能であり、それらを本発明の範囲から
排除するものではない。(6) In this way, as shown in FIG. 2F, the solder bumps 31 of the BGA package 30 are correctly aligned with the pads 41 of the mother board 40 so that they are correctly connected. Thus, BGA
It can also be applied to packages. It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.
【００２２】[0022]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、半田バンプの付いた半導体装置の裏面にバンプ
配列に合わせて第１の線を、配線基板上には予めパッド
配線に合わせて第２の線を引いておくことにより、予め
パッド配線に合わせて線の引いてある配線基板上に、半
導体装置を簡単かつ確実に搭載することができる。As described above in detail, according to the present invention, the first line is formed on the back surface of the semiconductor device having the solder bumps in accordance with the bump arrangement, and the pad wiring is previously formed on the wiring board. By drawing the second line together, the semiconductor device can be mounted easily and surely on the wiring board in which the line is drawn in advance according to the pad wiring.
【００２３】特に、微細な寸法に配置された半導体素子
の半田バンプと、微細な寸法に配置された配線基板とし
てのパッケージのパッドとを正確に位置合わせして、確
実に接続することができる。In particular, it is possible to accurately align the solder bumps of the semiconductor element arranged in the fine dimension with the pads of the package as the wiring board arranged in the fine dimension to ensure reliable connection.
【図１】本発明の第１実施例を示す半導体素子の位置合
わせ方法の説明図である。FIG. 1 is an explanatory diagram of a semiconductor element alignment method according to a first embodiment of the present invention.
【図２】本発明の第２実施例を示す半導体素子の位置合
わせ方法の説明図である。FIG. 2 is an explanatory diagram of a semiconductor element alignment method showing a second embodiment of the present invention.
【図３】従来の第１の半田バンプの付いた半導体素子の
位置合わせ方法の説明図である。FIG. 3 is an explanatory diagram of a conventional alignment method for a semiconductor element having a first solder bump.
【図４】従来の第２の半田バンプの付いた半導体素子の
位置合わせ方法の説明図である。FIG. 4 is an explanatory diagram of a conventional method for aligning a semiconductor element having a second solder bump.
１０ 半導体素子 １０ａ 半導体素子の表面 １１，３１ 半田バンプ １２，３４ 第１の線 ２０ 配線基板 ２１，４１ パッド ２２，４２ 第２の線 ３０ ＢＧＡパッケージ ３３ ＩＣチップ ４０ マザーボード 10 semiconductor element 10a surface of semiconductor element 11,31 solder bump 12,34 first line 20 wiring board 21,41 pad 22,42 second line 30 BGA package 33 IC chip 40 motherboard
Claims (2)
装置の位置合わせ方法において、 （ａ）半田バンプの付いた半導体装置をＸ線で透過し、
該半導体装置の裏面にレーザーで半田バンプ配列に合わ
せた第１の線を付す工程と、 （ｂ）前記半導体装置が搭載される配線基板の裏面にパ
ッド配列に合わせた第２の線を付す工程と、 （ｃ）前記半導体装置の裏面側に位置する撮像装置によ
り前記第２の線に前記第１の線を合わせ前記配線基板の
パッドに前記半導体装置の半田バンプを接続する工程と
を施すことを特徴とする半導体装置の位置合わせ方法。1. A method of aligning a semiconductor device having a solder bump on a wiring board, comprising: (a) transmitting a semiconductor device having a solder bump with X-rays;
A step of attaching a first line aligned with the solder bump arrangement to the back surface of the semiconductor device with a laser; and (b) a step of attaching a second line aligned with the pad array on the back surface of the wiring board on which the semiconductor device is mounted. And (c) aligning the first line with the second line by an imaging device located on the back side of the semiconductor device and connecting the solder bumps of the semiconductor device to the pads of the wiring board. A method for aligning a semiconductor device, comprising:
方法において、前記半導体装置は半導体素子であり、配
線基板は半導体素子のパッケージである半導体装置の位
置合わせ方法。2. The method of aligning a semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor element, and the wiring board is a package of the semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6292466A JPH08153995A (en) | 1994-11-28 | 1994-11-28 | Method for aligning semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6292466A JPH08153995A (en) | 1994-11-28 | 1994-11-28 | Method for aligning semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08153995A true JPH08153995A (en) | 1996-06-11 |
Family
ID=17782180
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6292466A Pending JPH08153995A (en) | 1994-11-28 | 1994-11-28 | Method for aligning semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08153995A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006118018A1 (en) * | 2005-04-28 | 2006-11-09 | Toray Engineering Co., Ltd. | Flip chip mounting shift inspecting method and mounting apparatus |
| JP2018082096A (en) * | 2016-11-17 | 2018-05-24 | ハンファテクウィン株式会社Ｈａｎｗｈａ Ｔｅｃｈｗｉｎ Ｃｏ．，Ｌｔｄ． | Electronic component mounting system and electronic component mounting method |
| JP2018082097A (en) * | 2016-11-17 | 2018-05-24 | ハンファテクウィン株式会社Ｈａｎｗｈａ Ｔｅｃｈｗｉｎ Ｃｏ．，Ｌｔｄ． | Electronic component mounting system and electronic component mounting method |
-
1994
- 1994-11-28 JP JP6292466A patent/JPH08153995A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006118018A1 (en) * | 2005-04-28 | 2006-11-09 | Toray Engineering Co., Ltd. | Flip chip mounting shift inspecting method and mounting apparatus |
| JP2018082096A (en) * | 2016-11-17 | 2018-05-24 | ハンファテクウィン株式会社Ｈａｎｗｈａ Ｔｅｃｈｗｉｎ Ｃｏ．，Ｌｔｄ． | Electronic component mounting system and electronic component mounting method |
| JP2018082097A (en) * | 2016-11-17 | 2018-05-24 | ハンファテクウィン株式会社Ｈａｎｗｈａ Ｔｅｃｈｗｉｎ Ｃｏ．，Ｌｔｄ． | Electronic component mounting system and electronic component mounting method |
| KR20180055675A (en) * | 2016-11-17 | 2018-05-25 | 한화에어로스페이스 주식회사 | An electronic device mounting system and method for mounting electronic device |
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