JPH01214009A - Semiconductor chip for integrated circuit - Google Patents

Semiconductor chip for integrated circuit

Info

Publication number
JPH01214009A
JPH01214009A JP63039311A JP3931188A JPH01214009A JP H01214009 A JPH01214009 A JP H01214009A JP 63039311 A JP63039311 A JP 63039311A JP 3931188 A JP3931188 A JP 3931188A JP H01214009 A JPH01214009 A JP H01214009A
Authority
JP
Japan
Prior art keywords
semiconductor chip
active element
integrated circuit
bonding material
die bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63039311A
Other languages
Japanese (ja)
Inventor
Tadashi Matsushita
忠司 松下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP63039311A priority Critical patent/JPH01214009A/en
Publication of JPH01214009A publication Critical patent/JPH01214009A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To stabilize an electrical characteristic and to prevent the destruction of an active element and the like formed on an active element formation region by a method wherein the region is formed into a circular shape or a polygonal shape with five sides or more by setting a semiconductor chip as the center. CONSTITUTION:In a semiconductor chip 5 for integrated circuit use, an active element formation region 5a is formed into a circular shape or a polygonal shape with five sides or more by setting the semiconductor chip 5 as the center. For example, while the active element formation region 5a of the semiconductor chip 5 is formed to be circular-shaped, a circuit which is not used during the operation of an integrated circuit or a dummy circuit for process condition confirmation use or for inspection use which is used during the manufacture of the integrated circuit is formed at a peripheral part 5b of the active element formation region 5a. By this setup, a die bonding material 6 creeps to the whole of the lower part of the formation part 5a of an active element which generates heat; the heat generated by the active element formed on the semiconductor chip 5 can be dissipated efficiently.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集積回路用半導体チップに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor chips for integrated circuits.

〔従来技術〕[Prior art]

近年、集積回路の高速度化がすすみ、それにともない、
半導体チップ上の集積回路の発熱が問題となってきてい
る。
In recent years, the speed of integrated circuits has increased, and as a result,
Heat generation from integrated circuits on semiconductor chips has become a problem.

このような集積回路は、通常、Si単結晶の基板(以下
ウェーハという。)又はGaAs基板上に、フォトリソ
グラフィ技術や薄膜形成技術を用いて形成される。その
形成においては、第2(a)図に示すように、複数の集
積回路をウェーハ上に形成し、この複数の集積回路をダ
イシング等により矩形状の半導体チップ2に分割してい
た。そして、この分割された半導体チップ2を、ダイボ
ンディング用基体にダイボンディングし、その後、ワイ
ヤボンディング等を行い半導体集積回路装置を完成して
いる。そして、このダイボンディングの状態を第2(b
)図、第2(C)図及び第2(d)図に示す。まず、ダ
イボンディング材4をダイボンディング用基体3に滴下
し、その上に半導体チップ2をボンディングしていた。
Such an integrated circuit is usually formed on a Si single crystal substrate (hereinafter referred to as a wafer) or a GaAs substrate using photolithography technology or thin film formation technology. In its formation, as shown in FIG. 2(a), a plurality of integrated circuits are formed on a wafer, and the plurality of integrated circuits are divided into rectangular semiconductor chips 2 by dicing or the like. Then, the divided semiconductor chip 2 is die-bonded to a die-bonding base, and then wire bonding or the like is performed to complete a semiconductor integrated circuit device. Then, this die bonding state is changed to the second (b) state.
), FIG. 2(C), and FIG. 2(d). First, the die bonding material 4 was dropped onto the die bonding base 3, and the semiconductor chip 2 was bonded thereon.

この矩形状の半導体チップ2には、そこに組み込まれる
能動素子の集積度を上げるため第2(b)図に示す点線
2aで囲む領域内に能動素子を形成し゛ていた。
In this rectangular semiconductor chip 2, active elements were formed in a region surrounded by a dotted line 2a shown in FIG. 2(b) in order to increase the degree of integration of active elements incorporated therein.

〔本発明の解決すでき課題〕[Problems to be solved by the present invention]

半導体集積回路では、能動素子をその中に集積して設け
ているため、動作時の発熱が問題へなる。
In semiconductor integrated circuits, since active elements are integrated therein, heat generation during operation becomes a problem.

そして、動作時に能動素子等から発生した熱は、半導体
チップ基板、ボンディング材及びダイボンディング用基
体を通って、放熱されていた。特に、この放熱の問題は
、集積回路の動作速度が早くなればなるほど大きな問題
となっている。
Heat generated from active elements and the like during operation is radiated through the semiconductor chip substrate, the bonding material, and the die bonding base. In particular, this heat dissipation problem becomes more serious as the operating speed of integrated circuits becomes faster.

しかし、第2(d)図に示すような、従来の半導体チッ
プ素子では、半導体チップ2の周辺角部2bの下側には
、ボンディング材が十分回り込まず、この角部領域2c
に形成された能動素子等で発生した熱は、ボンディング
材を介しては放熱されない。そのため、能動素子等の放
熱にムラが生じていた。そして、この放熱のムラにより
、集積回路の電気特性が安定しなかったりし、その周辺
角部2bに形成された能動素子等が破壊されたりした。
However, in the conventional semiconductor chip element as shown in FIG. 2(d), the bonding material does not sufficiently wrap around the lower side of the peripheral corner 2b of the semiconductor chip 2, and this corner region 2c
The heat generated by the active elements formed in the bonding material is not radiated through the bonding material. As a result, heat dissipation from active elements and the like has been uneven. Due to this unevenness in heat dissipation, the electrical characteristics of the integrated circuit may become unstable, and the active elements formed at the peripheral corner portion 2b may be destroyed.

また、この周辺角部2bの下側まで、十分にボンディン
グ材を周り込まずため、ダイボンディング材の量を増や
すと、第2(e)図に示すように、ダイボンディング材
が半導体チップの上面にかぶさりワイヤポンディングパ
ッドに付着してしまい、ワイヤボンディングの際、問題
が生じる。また、更に、このようにボンディング材の量
を増やすためには、ボンディング材を数回滴下しなけれ
ばならい。それにより、半導体チップの裏面とダイボン
ディング材との間に気泡が生じ、その気泡部分での放熱
が十分に行われず、先に説明したような問題が生じる恐
れもあった。
Furthermore, if the amount of die bonding material is increased because the bonding material is not sufficiently wrapped around the lower side of the peripheral corner 2b, as shown in FIG. The overlying wire adheres to the bonding pad, causing problems during wire bonding. Furthermore, in order to increase the amount of bonding material in this manner, the bonding material must be dropped several times. As a result, air bubbles are generated between the back surface of the semiconductor chip and the die bonding material, and heat dissipation in the air bubbles is not sufficient, which may cause the problems described above.

本発明は上記問題点を解決し、電気特性が安定し、また
、その上に形成された能動素子等が破壊されない集積回
路用半導体チップを提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a semiconductor chip for an integrated circuit that has stable electrical characteristics and that does not destroy active elements formed thereon.

〔課題を解決するための手段〕[Means to solve the problem]

本発明では、上記課題を解決するため、集積回路用の半
導体チップにおいて、能動素子形成領域を半導体チップ
を中心として円形または5角形以上の多角形の形状にし
ている。
In order to solve the above-mentioned problems, in the present invention, in a semiconductor chip for an integrated circuit, an active element forming region is formed into a circular shape or a polygonal shape of pentagon or more with the semiconductor chip as the center.

〔゛作用〕[゛effect]

本発明の半導体チップでは、そのチップの裏面がダイボ
ンデング材に接触する領域内の半導体チップ表面に能動
素子等を形成し、十分な放熱を可能にしている。
In the semiconductor chip of the present invention, active elements and the like are formed on the surface of the semiconductor chip in a region where the back surface of the chip contacts the die bonding material, thereby enabling sufficient heat dissipation.

−〔実施例〕 以下図面を参照しつつ本発明に従う実施例について説明
する。
- [Examples] Examples according to the present invention will be described below with reference to the drawings.

同一符号を付した要素は同一機能を有するため重複する
説明は省略する。
Elements with the same reference numerals have the same functions, so duplicate explanations will be omitted.

第1図は本発明に従う実施例の半導体チップをダイボン
ディング用基体、いわゆる、リードフレームのベツド部
にボンディングした状態を示している。第1(a)図は
上面図、第1(b)図は第1(a)図の矢印X方向から
見た図及び第1(c)図は第(a)図の矢印Y方向より
見た図である。
FIG. 1 shows a state in which a semiconductor chip according to an embodiment of the present invention is bonded to a die bonding substrate, ie, the bed portion of a lead frame. Figure 1(a) is a top view, Figure 1(b) is a view viewed from the direction of arrow X in Figure 1(a), and Figure 1(c) is viewed from the direction of arrow Y in Figure 1(a). This is a diagram.

この第1(a)図に示すように、半導体チップ5の能動
素子形成領域5aは円形状にしである。この様な形状を
採用したのは、以下の理由による。
As shown in FIG. 1(a), the active element forming region 5a of the semiconductor chip 5 has a circular shape. The reason why such a shape was adopted is as follows.

半導体チップ5をダイボンディング用基体7にダイボン
ディングする際、ダイボンディング材6をダイボンディ
ング用基体7に塗布し、このダイボンディング材7を介
してボンディングしている。
When the semiconductor chip 5 is die-bonded to the die-bonding base 7, a die-bonding material 6 is applied to the die-bonding base 7, and bonding is performed via the die-bonding material 7.

このダイボンディング材6は塗布したとき円形状に拡が
る。ここで、この半導体チップ5の上面には、能動素子
等を形成するが、この能動素子形成領域の下側全面にボ
ンディング材が回り込むようにしなければならない。そ
して、ダイボンディング材6は先に説明したように、円
形形状に拡がり、これに一致させるため、能動素子形成
領域5aを円形形状にしている。
This die bonding material 6 spreads into a circular shape when applied. Here, active elements and the like are formed on the upper surface of the semiconductor chip 5, but the bonding material must wrap around the entire lower side of the active element formation region. As described above, the die bonding material 6 spreads into a circular shape, and in order to match this, the active element forming region 5a is formed into a circular shape.

そして、この能動素子領域5aの周辺部5bには、集積
回路の動作時には使用しない回路、例えば、集積回路製
作の際に使用するプロセス条件確認用、または検査用ダ
ミー回路等を形成する。すなわち、この周辺部5bの下
側にはダイボンディング材6が存在しにくいため、集積
回路の動作時に使用せず発熱しないような素子を形成す
る。
Then, in the peripheral portion 5b of the active element region 5a, a circuit that is not used during the operation of the integrated circuit, such as a dummy circuit for checking process conditions or testing used during the manufacture of the integrated circuit, is formed. That is, since it is difficult for die bonding material 6 to exist below this peripheral portion 5b, an element that is not used during operation of the integrated circuit and does not generate heat is formed.

この能動素子等の形成及びダミー回路の形成は、フォト
リソグラフィ技術及び薄膜形成技術等で行うことができ
、この技術は、従来より知られているため、本明細書で
は省略する。
The formation of the active elements and the dummy circuit can be performed using photolithography technology, thin film formation technology, etc., and since this technology is conventionally known, it will be omitted in this specification.

なお、このように、能動素子形成領域5aを限定して半
導体チップ5上に形成することは、製造工程を変えるこ
となく、単にフォトリソグラフィ工程で使用するフォト
マスクのパターンを変更するだけで容易に行うことがで
きる。
Note that forming the active element forming region 5a in a limited manner on the semiconductor chip 5 in this way can be easily done by simply changing the pattern of the photomask used in the photolithography process, without changing the manufacturing process. It can be carried out.

この半導体チップ5をダイボンディング用基体7にダイ
ボンディングする方法について説明する。
A method of die bonding this semiconductor chip 5 to the die bonding base 7 will be explained.

まず、ダイボンディング用基体7にダイボンディング材
6を塗布する。この塗布の方法は、ダイボンディング材
を滴下することにより行う。次に、このダイボンディン
グ用基体7を円形状に移動させ、ダイボンディング材を
伸ばす。次に、この伸ばされたダイボンディング材の上
に半導体チップをボンディングする。
First, the die bonding material 6 is applied to the die bonding substrate 7. This application method is performed by dropping the die bonding material. Next, this die bonding base 7 is moved in a circular shape to stretch the die bonding material. Next, a semiconductor chip is bonded onto this stretched die bonding material.

円形状の能動素子領域を有する半導体チップを用い、上
記方法でダイボンディングすることにより、半導体チッ
プの能動素子領域の下側全部に隙間なくダイボンディン
グ材を設けることができる。
By performing die bonding using the above method using a semiconductor chip having a circular active element area, the die bonding material can be provided completely below the active element area of the semiconductor chip without any gaps.

本発明は上記実施例に限定されるものでなく、種々の変
形例が考えられ得る。
The present invention is not limited to the above embodiments, and various modifications may be made.

具体的には、上記実施例では、半導体チップの能動素子
形成領域を半導体チップの中心を中心とする円形状にし
ているが、これに限定されるものでなく、五角形以上の
多角形でも、ダイボンディング材は半導体チップの裏面
に十分回り込む。
Specifically, in the above embodiment, the active element forming area of the semiconductor chip is formed into a circular shape centered on the center of the semiconductor chip, but the shape is not limited to this, and even a polygon of pentagon or more can be formed on the die. The bonding material sufficiently wraps around the back surface of the semiconductor chip.

また更に、上記実施例では、単導体チップをダイボンデ
ィング用基体にボンディングする際、ダイボンディング
材を基体に塗布しているが、この代わりに半導体チップ
側にダイボンディング材を塗布してもよい。この場合に
は、半導体チップの裏面の中心にダイボンディング材を
滴下し、この半導体チップをダイボンディング用基体に
押し付け、伸ばしボンディングする。
Furthermore, in the above embodiment, when bonding the single conductor chip to the die bonding substrate, the die bonding material is applied to the substrate, but the die bonding material may be applied to the semiconductor chip side instead. In this case, the die bonding material is dropped onto the center of the back surface of the semiconductor chip, the semiconductor chip is pressed against the die bonding base, and the semiconductor chip is stretched and bonded.

〔発明の効果〕〔Effect of the invention〕

本発明の半導体チップでは、その能動素子形成領域を、
チップを中心とした円形または五角形以上の多角形とす
ることにより、発熱する能動素子の形成部の下側全体に
ダイボンディング材が回り込み、半導体チップ上に形成
された能動素子が発生した熱を効率よく放熱することが
できる。そのため、この様な形状の半導体チップを採用
することにより、特に高速度デバイスにおいては、発熱
の問題が容易に解決できる。
In the semiconductor chip of the present invention, the active element forming region is
By forming a circle or a polygon of pentagon or larger with the chip at the center, the die bonding material wraps around the entire lower side of the active element formation area that generates heat, making it possible to efficiently dissipate the heat generated by the active elements formed on the semiconductor chip. It can dissipate heat well. Therefore, by employing a semiconductor chip having such a shape, the problem of heat generation can be easily solved, especially in high-speed devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に従う半導体チップをダイボンディング
した状態を示す図、及び第2図は従来例を説明する図で
ある。 1・・・ウェーハ、2.5・・・半導体チップ、2a・
・・能動素子形成領域、2c・・・半導体チップ周辺角
部、3.7・・・ダイボンディング用基体、4.6・・
・ダイボンディング材、5a・・・能動素子形成領域、
5c・・・ダミー回路形成領域。 特許出願人  住友電気工業株式会社 代理人弁理士   長谷用  芳  樹間      
   寺   嶋   史   朗第1図 =2a (b) 、  従来例 第2図 (C) (d) ゝ3 (e)
FIG. 1 is a diagram showing a state in which a semiconductor chip according to the present invention is die-bonded, and FIG. 2 is a diagram illustrating a conventional example. 1... Wafer, 2.5... Semiconductor chip, 2a.
...Active element formation area, 2c...Semiconductor chip peripheral corner, 3.7...Die bonding base, 4.6...
・Die bonding material, 5a...active element formation area,
5c...Dummy circuit formation area. Patent applicant: Sumitomo Electric Industries, Ltd. Representative patent attorney Yoshiki Hase
Fumiaki Terashima Figure 1 = 2a (b), Conventional example Figure 2 (C) (d) ゝ3 (e)

Claims (1)

【特許請求の範囲】[Claims]  集積回路用の半導体チップにおいて、能動素子形成領
域が半導体チップを中心として円形または5角形以上の
多角形の形状であることを特徴とする集積回路用半導体
チップ。
1. A semiconductor chip for an integrated circuit, characterized in that an active element formation region has a circular shape or a polygonal shape of pentagon or more with the semiconductor chip at the center.
JP63039311A 1988-02-22 1988-02-22 Semiconductor chip for integrated circuit Pending JPH01214009A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63039311A JPH01214009A (en) 1988-02-22 1988-02-22 Semiconductor chip for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63039311A JPH01214009A (en) 1988-02-22 1988-02-22 Semiconductor chip for integrated circuit

Publications (1)

Publication Number Publication Date
JPH01214009A true JPH01214009A (en) 1989-08-28

Family

ID=12549566

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63039311A Pending JPH01214009A (en) 1988-02-22 1988-02-22 Semiconductor chip for integrated circuit

Country Status (1)

Country Link
JP (1) JPH01214009A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7114797B2 (en) 2002-05-13 2006-10-03 Seiko Epson Corporation Actuator device, liquid ejection head, and method of inspecting the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7114797B2 (en) 2002-05-13 2006-10-03 Seiko Epson Corporation Actuator device, liquid ejection head, and method of inspecting the same
US7207664B2 (en) 2002-05-13 2007-04-24 Seiko Epson Corporation Actuator device, liquid ejection head, and method of inspecting the same
US7210770B2 (en) 2002-05-13 2007-05-01 Seiko Epson Corporation Actuator device, liquid ejection head, and method of inspecting the same

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