JP2002319558A - Manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely and economically make a semiconductor chip thin by polishing its reverse surface. SOLUTION: A chip tray 10 is manufactured by forming many storage grooves 12 each having a vacuum suction hole 13 and an escape groove 14 in a tray substrate 11 formed of a semiconductor wafer together by photolithography at a time with high precision; and semiconductor chips 20 having been diced are put in the respective storage grooves 12 of the chip tray 10, which is mounted on a wafer holding jig 32 of a wafer grinding device 30 instead of the wafer, so that the reverse surfaces of the semiconductor chips 20 are ground together. The escape grooves 14 eliminate variance in grinding pressure due to projections of bump electrodes 21 of the semiconductor chips 20 and thickness control by the reverse-surface grinding under uniform, and high- precision machining size control can be exercised over the semiconductor chips 20 stored in the chip tray 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly, to the application of a semiconductor chip having an uneven surface such as a bump electrode formed on an element forming surface in a wafer state by a wafer bumping technique or the like. Effective technology.

[0002]

2. Description of the Related Art For example, in a flip-chip mounting technique for directly mounting on a target object by bump electrodes or the like formed on a semiconductor chip along with miniaturization of a mounting target device, a wafer state before dicing is required. In some cases, a wafer bumping technique for forming bump electrodes on a plurality of semiconductor chips at once is used.

On the other hand, in response to a demand for a thinner mounting object, a semiconductor chip mounted on the mounting object is also required to be thinner.

In order to reduce the thickness of a semiconductor chip, the back surface opposite to the element forming surface is ground in a wafer state before dicing to obtain the thickness of the wafer (ie, the thickness of the semiconductor chip).
Can be reduced.

[0005]

However, when grinding the back surface of a semiconductor wafer having bump electrodes formed on the element forming surface side by a wafer bumping technique or the like, a semiconductor chip located at the peripheral portion of the semiconductor wafer has bumps on the outside thereof. Since there is no electrode (adjacent semiconductor chip), the supporting pressure from the element forming surface side during grinding becomes non-uniform, and the variation in the thickness dimension after grinding is larger than that of the semiconductor chip located at the center of the wafer or the like. Technical problem.

If a semiconductor chip having such a large variation in the thickness dimension is mounted by pressure bonding as it is, the application of pressure becomes non-uniform, which causes poor pressure bonding and poor connection (non-conduction), and a defective product in the mounting process. Increase.

Such a technical problem also occurs, for example, in a system LSI or the like in which a memory, a logic, and the like are mounted. In other words, since the memory and logic have different numbers of laminated films in the manufacturing process, and the thickness dimensions at respective portions of the memory and logic in the completed process are different, when the back surface is ground in the wafer state, the same as described above. Technical issues arise.

An object of the present invention is to provide a semiconductor device manufacturing technique capable of accurately reducing the thickness of a semiconductor chip by grinding the back surface.

Another object of the present invention is to provide a semiconductor device manufacturing technique capable of accurately reducing the thickness of a semiconductor chip by grinding its back surface without being restricted by a wafer diameter or the like in a wafer process. It is in.

Another object of the present invention is to make it possible to accurately reduce the thickness of a semiconductor chip by grinding its back surface at low cost by using the existing equipment such as a wafer grinding device without any modification. An object of the present invention is to provide a semiconductor device manufacturing technique.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

The present invention provides a semiconductor device manufacturing technique which includes a step of accommodating a plurality of semiconductor chips in a holding jig and simultaneously performing a grinding process on a back surface of the semiconductor chip opposite to an element forming surface. .

More specifically, as one example, a vacuum suction hole and a bump on the element forming surface side of the semiconductor chip are formed on one main surface of a storage jig made of a semiconductor wafer used for manufacturing a semiconductor chip by photolithography or the like. A plurality of storage grooves in which escape grooves for electrodes and the like are formed are collectively formed, and the semiconductor chips after dicing are arranged inside the respective storage grooves in a state where the back side is exposed. Is mounted on a wafer holding jig in a wafer grinding apparatus, whereby the backside grinding of a large number of semiconductor chips is performed collectively by the same equipment as the wafer grinding.

In this case, the semiconductor wafer as the storage jig can be used repeatedly by setting the depth dimension of the storage groove to be substantially equal to the finished dimension of the back side grinding of the semiconductor chip. .

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a plan view showing an example of the configuration of a storage jig used in a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. FIG. 3 is a cross-sectional view illustrating an example of the configuration of a wafer grinding apparatus that implements the method of manufacturing a semiconductor device according to the present embodiment. FIG. 3 is a flowchart illustrating an example of the operation of the method of manufacturing a semiconductor device according to the present embodiment. 4A to 4C are cross-sectional views illustrating an example of a method for manufacturing the storage jig according to the present embodiment in the order of steps.

First, in a wafer process, semiconductor chips having a desired function are collectively formed on a semiconductor wafer (not shown) (step 101), and collective bumps are formed on the element forming surface side of the semiconductor wafer by a wafer bumping technique. After the formation of the electrodes 21 (Step 102), the semiconductor wafer is divided into a plurality of semiconductor chips 20 each having the bump electrode 21 by dicing (Step 10).
3).

On the other hand, in parallel with steps 101 to 103, a tray substrate 11 made of a semiconductor wafer or the like is prepared (step 104), and the tray surface is processed by photolithography as follows. Then, the chip tray 10 is manufactured (step 105).

That is, as illustrated in FIG. 1, a chip tray 10 which is a storage jig of the present embodiment stores individual semiconductor chips 20 on one main surface of a tray substrate 11 made of, for example, a semiconductor wafer. Are formed in a row.

Since the semiconductor wafer used as the tray substrate 11 is used as a jig utilizing a contour or the like, it is necessary to use an expensive non-defective wafer used in the manufacturing process of the semiconductor device such as the semiconductor chip 20. Inexpensive and defective semiconductor wafers that have been rejected for the manufacture of semiconductor chips 20 and that have an external shape such as contour shape and thickness that can be used as a material for chip tray 10 should be used as they are. Can be.

Each of the storage grooves 12 has a rectangular outline shape in which the semiconductor chip 20 is just fitted. Inside the storage groove 12, a plurality of vacuum suctions for sucking and fixing the semiconductor chip 20 in the storage groove 12 are provided. Hole 13 and semiconductor chip 2
An escape groove 14 is formed for the bump electrode 21 which is formed to have irregularities in 0.

Here, an example of a method of forming the storage groove 12 having the above-described structure in the chip tray 10 is illustrated in FIG.

That is, a photoresist film 15 is formed so as to have an opening 15a at a position where a vacuum suction hole 13 is formed with respect to one main surface of a tray substrate 11 made of a semiconductor wafer (FIG. 4A). 4), a vacuum suction hole 13 penetrating the tray substrate 11 is formed by etching (FIG. 4B).

Next, a photoresist film 16 is formed so as to have an opening 16a at a position where the escape groove 14 is formed (FIG. 4B), and etching is performed to reduce the depth of the storage groove 12 described later. A deep escape groove 14 is formed (FIG. 4).
(C)) After removing the photoresist film 16 (FIG. 4D), a photoresist film 17 having an opening 17a in the shape of the storage groove 12 is formed (FIG. 4E), and the semiconductor chip is formed. Etching is performed to a depth set according to the thickness dimension of 20 and the size of the grinding allowance, etc.
After the formation of No. 2, the photoresist film 17 is removed (FIG. 4F).

As described above, by using the photolithography technique in the wafer process, the plurality of storage grooves 12 can be formed.
In addition, the vacuum suction holes 13 and the relief grooves 14 associated with each of them can be formed according to the thickness of the semiconductor chip 20, the height of the bump electrodes 21, the contour dimensions, and the like, and by precise depth control. It is.

After the semiconductor chip 20 and the chip tray 10 are prepared as described above, the semiconductor chip 20 and the chip tray 10 are mounted on, for example, a wafer grinding apparatus 30 as illustrated in FIG. 2 (step 106). The thickness is reduced by back grinding (step 107).

That is, the wafer grinding apparatus 30 has a grinding tool surface 31a on the surface and the rotating base plate 31
, A pressure plate 33 having a wafer holding jig 32 on the facing surface and rotating with respect to the base plate 31, and a drive mechanism (not shown) for driving the pressure plate 33.

The opening 32a of the wafer holding jig 32
, A vacuum suction groove (not shown) formed in the pressure plate 33 located on the back side is exposed.

The semiconductor wafer used for manufacturing the above-mentioned chip tray 10 has an opening 32 of a wafer holding jig 32.
The one having the same contour shape as the contour shape of a is used.

Then, the chip tray 10 is loaded with the semiconductor chips 20 in each of the plurality of storage grooves 12.
The semiconductor chip 20 is loaded into the opening 32 a of the wafer holding jig 32 with the storage surface of the semiconductor chip 20 facing the base plate 31. At this time, a vacuum suction groove (not shown) formed in the pressure plate 33 communicates with the vacuum suction hole 13 of the chip tray 10, and the chip tray 10 and the semiconductor chip 20 are connected to the back surface of the semiconductor chip (the bump electrode 21).
With the other side facing the base plate 31 side,
The wafer is stably held by the wafer holding jig 32 by vacuum suction.

Then, the back surface of the semiconductor chip 20 stored in the chip tray 10 is pressed against the grinding tool surface 31a of the base plate 31 by the pressing force from behind by the pressure plate 33, and the base plate 31 and the pressure plate are pressed. Grinding of the back surface of the semiconductor chip 20 is performed by relatively rotating 33.

At this time, since the pressing force does not act on the projections such as the bump electrodes 21 due to the escape grooves 14 in the storage grooves 12 of the chip tray 10, the plurality of semiconductor chips 20 held in the storage grooves 12 are applied to each of the plurality of semiconductor chips 20. The uniform pressing force acts, and the back surface of the semiconductor chip 20 can be ground with high uniformity regardless of the storage position in the chip tray 10.

The semiconductor chip 20 whose thickness has been reduced by grinding the back surface is subjected to an assembly process such as packaging and a mounting process such as flip chip bonding (step 108).

As described above, according to the present embodiment, by grinding the back surface in a state where the semiconductor chip 20 is loaded on the chip tray 10, the variation in the thickness of the semiconductor chip 20 is substantially reduced. Although it depends on the processing accuracy of the tray 10, as illustrated in FIG. 4 and the like described above, a semiconductor wafer is used as the tray substrate 11, and the processing accuracy equivalent to the wafer process in the manufacturing process of the semiconductor chip 20 is obtained. By processing the storage groove 12 and the like by photolithography, the variation can be controlled in sub-μm units, and the thickness dimension control by grinding the back surface of the semiconductor chip 20 can be controlled with high accuracy and high uniformity. It is possible to do.

For example, the semiconductor chip 20 after back grinding
When the finished dimension of the wafer is 400 μm, 50 μm at the center and the periphery in the backside grinding in the wafer state as in the prior art.
In the case where a plurality of semiconductor chips 20 are collectively back-ground in a chip state by using the chip tray 10 as in the present embodiment, the back-surface grinding has a variation in finished thickness of m or more. It has been found that the variation in the finished dimensions of the semiconductor chip 20 can be controlled to 20 μm or less.

Further, since the back surface is ground by mounting the semiconductor chip 20 after dicing on the chip tray 10, regardless of the diameter of the semiconductor wafer used in the wafer process in manufacturing the semiconductor chip 20, 10 common wafer grinding apparatus 30 capable of loading
, The back surface of the semiconductor chip 20 can be ground, and the efficiency of the manufacturing process can be improved.

Further, if the depth dimension of the storage groove 12 of the chip tray 10 is set to be equal to the finished dimension of the back surface grinding of the semiconductor chip 20, the chip tray 10 is moved to the grinding tool surface 31a in a state where the back surface grinding is completed. , It is possible to use the same chip tray 10 repeatedly, and the economic efficiency is improved.

In the grinding machine illustrated in FIG. 2, the chip tray 1 on the pressure plate 33 or the like is used.
The unevenness opposite to that of the semiconductor wafer to be ground is formed on the suction surface of 0 so that the pressing force from the pressure plate 33 to the semiconductor wafer to be ground acts uniformly without being affected by the unevenness of the semiconductor wafer. Thus, uniform back grinding may be performed in a wafer state.

Further, by forming irregularities opposite to the irregularities of the semiconductor wafer to be ground and vacuum suction holes on a semiconductor wafer having the same contour dimensions as the semiconductor wafer to be ground and using the same as a pressing jig, the irregularities of the semiconductor wafer can be improved. It is also possible to perform uniform back surface grinding in the wafer state by acting uniformly without being affected by the above. Also in this case, the semiconductor wafer used as the pressing jig does not need to be a non-defective product for the wafer process, and it is sufficient that the external shape such as the contour and the thickness dimension can be used as the pressing jig.

Next, an example of mounting the semiconductor chip 20 obtained by grinding the back surface of the present embodiment on an actual device will be described.

FIG. 5 shows a configuration in which, for example, the semiconductor chip 20 having a function as a liquid crystal driver IC is subjected to the back grinding according to the present embodiment, and then sealed in a tape carrier package 40 and mounted on a liquid crystal panel 50. FIG. 6 is a cross-sectional view showing one example, and FIG. 6 is a plan view thereof.

That is, the tape carrier package 40
A plurality of lead patterns 43 are formed substantially radially around an opening 42 at the center of the insulating tape 41, and an inner end 43 a protruding into the opening 42 of the lead pattern 43 is provided with a bump of the semiconductor chip 20. It is electrically connected to the electrode 21. The opening 42 is filled with a sealing resin 44, and the inner end 43 a of the lead pattern 43 and the bump electrode 2 are filled.
1 is sealed.

Such a tape carrier package 40
The outer end 43b of some of the lead patterns 43 in
The liquid crystal panel 50 is electrically connected to a transparent electrode 51 such as ITO exposed on the periphery of the liquid crystal panel 50, and the outer end 43c on the opposite side is connected to an external circuit (not shown).
Of each of the plurality of pixels constituting the pixel.

Here, with the miniaturization and cost reduction of the device using the liquid crystal panel 50, the demand for the liquid crystal panel 50 to be thinner and to reduce the manufacturing cost has become stronger.
It is necessary to reduce the thickness t1 of the liquid crystal panel 50 at low cost. For example, when the thickness t1 is reduced to about several hundred μm or less, it is necessary to reduce the thickness t2 of the semiconductor chip 20 of the tape carrier package 40 arranged in the peripheral part on the same order.

According to the back surface grinding of the present embodiment as described above, the reduction of the thickness t2 of the semiconductor chip 20 to about several hundreds μm or less can be achieved at a low cost and with high precision as described above. Therefore, the liquid crystal panel 50 including the semiconductor chip 20 as the liquid crystal driver IC can be reduced in thickness and cost.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof. Needless to say, there is.

For example, in the above description, the bump electrodes 21 have been described as an example of the unevenness in the semiconductor chip 20. However, in order to integrate the memory and logic into one chip, the surface of the semiconductor chip 20 (element formation) is formed. Surface) can be widely applied to products having large irregularities.

[0049]

According to the present invention, a process for accommodating a plurality of semiconductor chips in a holding jig and simultaneously performing the grinding of the back surface of the semiconductor chip on the side opposite to the element forming surface can accurately reduce the thickness of the semiconductor chip by grinding the back surface. It is possible to do well.

The process of accommodating a plurality of semiconductor chips in a holding jig and simultaneously performing the grinding of the back surface of the semiconductor chip opposite to the element forming surface is restricted by a wafer diameter in a wafer process. Therefore, it is possible to accurately reduce the thickness of the semiconductor chip by grinding the back surface.

The process of accommodating a plurality of semiconductor chips in a holding jig made of a semiconductor wafer and simultaneously performing the grinding of the back surface of the semiconductor chip on the side opposite to the element forming surface is performed by using a facility such as an existing wafer grinding apparatus. By directly using the semiconductor chip without modifying it, it is possible to accurately reduce the thickness of the semiconductor chip by grinding the back surface at low cost.

[Brief description of the drawings]

FIG. 1 is a plan view showing an example of a configuration of a storage jig used in a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating an example of a configuration of a wafer grinding apparatus that performs a method of manufacturing a semiconductor device according to one embodiment of the present invention using a storage jig according to one embodiment of the present invention.

FIG. 3 is a flowchart illustrating an example of an operation of a method of manufacturing a semiconductor device according to an embodiment of the present invention;

FIGS. 4A to 4F are cross-sectional views illustrating an example of a method of manufacturing a storage jig according to an embodiment of the present invention in the order of steps.

FIG. 5 is a cross-sectional view showing an example of mounting a semiconductor chip obtained by a method of manufacturing a semiconductor device according to an embodiment of the present invention on a liquid crystal panel.

FIG. 6 is a plan view showing an example of mounting a semiconductor chip obtained by a method of manufacturing a semiconductor device according to an embodiment of the present invention on a liquid crystal panel.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Chip tray 11 Tray substrate 12 Storage groove 13 Vacuum suction hole 14 Escape groove 15 Photoresist film 15a Opening 16 Photoresist film 16a Opening 17 Photoresist film 17a Opening 20 Semiconductor chip 21 Bump electrode 30 Wafer grinding device 31 Base plate 31a Grinding tool surface 32 Wafer holding jig 32a Opening 33 Pressure plate 40 Tape carrier package 41 Insulating tape 42 Opening 43 Lead pattern 43a Inner end 43b Outer end 43c Outer end 44 Sealing resin 50 Liquid crystal panel 51 Transparent electrode

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device, comprising the steps of: accommodating a plurality of semiconductor chips in a holding jig and simultaneously performing grinding of a back surface of the semiconductor chip opposite to an element forming surface. . 2. The method of manufacturing a semiconductor device according to claim 1, wherein the holding jig is formed with a plurality of storage grooves in which each of the plurality of semiconductor chips is stored. A method of manufacturing a semiconductor device, comprising: a clearance groove for an uneven portion of the element forming surface of the semiconductor chip; and a vacuum suction hole for holding the semiconductor chip in the storage groove by vacuum suction. . 3. The method of manufacturing a semiconductor device according to claim 1, wherein said holding jig has the same contour as a semiconductor wafer used in a wafer process for manufacturing said semiconductor chip. A method for manufacturing a semiconductor device, wherein a plurality of the semiconductor chips are collectively ground by directly mounting them on a grinding device used for grinding. 4. The method of manufacturing a semiconductor device according to claim 2, wherein said holding jig is made of a semiconductor wafer used in a wafer process for manufacturing said semiconductor chip, and said holding jig is formed on one main surface of said semiconductor wafer. By lithography, a plurality of the accommodating grooves each having the relief groove and the vacuum suction hole are collectively formed, and the holding jig in which the semiconductor chip is accommodated in each of the retaining grooves is provided to a wafer grinding apparatus. A method of manufacturing a semiconductor device, wherein a plurality of the semiconductor chips are collectively back-ground ground by being loaded. 5. The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor chip includes a bump electrode on said element forming surface.