JPH01212443A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01212443A JPH01212443A JP3805788A JP3805788A JPH01212443A JP H01212443 A JPH01212443 A JP H01212443A JP 3805788 A JP3805788 A JP 3805788A JP 3805788 A JP3805788 A JP 3805788A JP H01212443 A JPH01212443 A JP H01212443A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- thickness
- implantation
- deposited
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 6
- 238000000137 annealing Methods 0.000 claims abstract description 3
- 150000002500 ions Chemical class 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 claims 2
- 239000012535 impurity Substances 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 6
- 230000008021 deposition Effects 0.000 abstract description 5
- 238000002513 implantation Methods 0.000 abstract description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 3
- 239000000470 constituent Substances 0.000 abstract description 3
- 238000010884 ion-beam technique Methods 0.000 abstract description 3
- 238000002347 injection Methods 0.000 description 13
- 239000007924 injection Substances 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 4
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000005465 channeling Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004969 ion scattering spectroscopy Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229910001338 liquidmetal Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
この発明は、半絶縁性G、A、基板に堆積される絶縁膜
の膜厚分布の均一性を高められる化合物半導体デバイス
の製造方法に関するものである。Detailed Description of the Invention (Industrial Application Field) This invention relates to a method for manufacturing a compound semiconductor device that can improve the uniformity of the thickness distribution of an insulating film deposited on a semi-insulating G, A, or substrate. It is.
(従来の技術)
GaAsJCを構成するFETの駆動能力の向上、並び
に形成されたFETの均一性、特にV。(Prior Art) Improving the driving ability of FETs constituting GaAsJC and uniformity of the formed FETs, especially V.
(しきい値電圧)の精密制御は、LSIレベルのデジタ
ルICを実用化する上で最も重要な技術課題である。Precise control of (threshold voltage) is the most important technical issue in putting LSI-level digital ICs into practical use.
FETの動作層形成は通常イオン注入で行なわれるがキ
ャリア濃度のピーク値の深さ、すなわち、動作層の厚み
を薄(シて相互コンダクタンス(gap)を向上させる
には数100人の薄い絶縁膜を介してイオン注入を行な
うスルー注入法が効果的であることは良く知られている
。The active layer of a FET is usually formed by ion implantation, but in order to reduce the depth of the peak value of carrier concentration, that is, the thickness of the active layer (and improve the mutual conductance (gap)), it is necessary to make several hundred thin insulating films. It is well known that the through implantation method, in which ions are implanted through the ion implantation method, is effective.
絶縁膜としては、S五lN4.S! Ox、S五O,N
。As the insulating film, S51N4. S! Ox,S5O,N
.
(0/N〜0.6)などが用いられている。(0/N to 0.6), etc. are used.
絶縁膜の形成方法は、CVD法とスパッタリング法に大
別されるが、低温成膜が可能で、膜自身の安定性にも優
れたプラズマCVD方がしばしば採用されている。Methods for forming insulating films are broadly classified into CVD methods and sputtering methods, but plasma CVD is often employed because it allows low-temperature film formation and has excellent stability of the film itself.
絶縁膜を通してのスルー注入法のメリットとしては、既
に述べた高g■化の効果の他に、絶縁膜内でのイオンの
散乱による面チャネリン、グ効果の緩和が上げられる。The merits of the through-injection method through the insulating film include, in addition to the already mentioned effect of increasing g, it also alleviates the planar channeling effect caused by ion scattering within the insulating film.
しかし、その反面、絶縁膜の厚みのバラツキがイオン注
入により形成される動作層の厚みに直接影響を及ぼすと
いう大きな問題を有している。この動作層厚みのバラツ
キはFETしきい値電圧(Vい)制御上致命的である。However, on the other hand, there is a major problem in that variations in the thickness of the insulating film directly affect the thickness of the active layer formed by ion implantation. This variation in the thickness of the active layer is fatal for controlling the FET threshold voltage (V).
第2図(al〜(幻はスルー注入法を用いた従来のFE
T形成工程の一例を示す断面図である。(a)は半絶縁
性Ga As基板(1)へプラズマCVD法でスルー注
入用絶縁膜(2)を堆積した状態を示す、(b)はフォ
トレジスト(3)を塗布後、写真製版を行って動作層(
n層)パターンの開口部を形成し、Sムイオン(4a)
を選択的に注入している状態を示す、(C1は動作層(
n層)(5)を生じ、スルー注入用絶縁膜(2a)、フ
ォトレジスト+3)を除去した状態を示す。Figure 2 (al~ (The illusion is a conventional FE using the through injection method.
It is a sectional view showing an example of a T formation process. (a) shows the insulating film (2) for through injection deposited on a semi-insulating GaAs substrate (1) by plasma CVD method, (b) shows photolithography after coating the photoresist (3). The operating layer (
n layer) pattern openings are formed, and Smu ions (4a) are formed.
(C1 is the active layer (
The state is shown in which the through-injection insulating film (2a) and the photoresist +3) have been removed.
(alは高融点ゲート電極(例えばWSt)+61を反
応性イオンエツチング(RI E)法で加工した状態を
示す0次いで(alに示すようにn0層(7)形成用の
第2のスルー注入絶縁膜(2b)を堆積し、写真製版。(al indicates the state in which the high melting point gate electrode (for example WSt) +61 is processed by the reactive ion etching (RIE) method.) Next, as shown in (al), the second through-implanted insulation for forming the n0 layer (7) is applied. Deposit film (2b) and photolithography.
反応性イオンエツチング(RI E)法でn9注入用の
開口部形成後、Sムイオン(4b)を高濃度に注入する
。そして(f)のように、注入イオンを活性化するため
に、例えば800℃前後のA s Hs雰囲気中で所定
の熱処理を行う、最後に、(8)の如く、オーミック電
極(8)を形成すればFETは完成する。After forming an opening for n9 implantation by reactive ion etching (RIE), S ions (4b) are implanted at a high concentration. Then, as shown in (f), a predetermined heat treatment is performed in an A s Hs atmosphere at around 800°C to activate the implanted ions.Finally, as shown in (8), an ohmic electrode (8) is formed. Then the FET is completed.
(発明が解決しようとする!!la)
第2図で詳細に述べた従来例に依った場合、動作層(n
層)の厚みの制御は極めて困難である。(What the invention attempts to solve!! la) When relying on the conventional example described in detail in FIG.
It is extremely difficult to control the thickness of the layer).
なぜならば、動作層の厚みを一義的に規定するプラズマ
CVD膜の膜厚は複雑な変動パラメータ(CVDIIR
の堆積される基板の比抵抗、基板の温度分布原料ガスの
流れの揺らぎ、プラズマの安定性、ガス組成比の微小変
動など)に支配されているからである。その中でも特に
高い比抵抗の基板は膜の堆積速度が非常に不安定である
。そのため、膜厚変動を±lθ%して内に抑えるのが技
術的限界と考えられている。しかし、プロセス方式によ
っては動作層形成におけるスルー注入用絶縁膜の膜厚が
目標値に対し約3%逸脱すればαvtt+は約10mV
シフトすると言われており、現状の±10%という変動
幅は側底満足できるものではなく、あらゆる対策を講じ
て膜厚変動を極限まで抑えることは、G、A、LSI実
用化の上で心遣の課題である。This is because the thickness of the plasma CVD film, which uniquely defines the thickness of the active layer, is subject to complex variation parameters (CVDIIR).
This is because it is controlled by the resistivity of the substrate on which it is deposited, the temperature distribution of the substrate, fluctuations in the flow of the source gas, stability of the plasma, minute fluctuations in the gas composition ratio, etc. Among these, substrates with particularly high resistivity have a very unstable film deposition rate. Therefore, it is considered that the technical limit is to suppress the film thickness variation within ±lθ%. However, depending on the process method, if the thickness of the through injection insulating film in active layer formation deviates by about 3% from the target value, αvtt+ will be about 10 mV.
It is said that the current fluctuation range of ±10% is not satisfactory, and it is important to take every possible measure to suppress film thickness fluctuations to the utmost when putting G, A, and LSI into practical use. This is an issue for the government.
この発明は、上記のような問題点を解決するためになさ
れたもので、絶縁膜の堆積速度を安定にすることができ
、動作層の厚さを精度良く制御可詣にすることを目的と
する。This invention was made to solve the above-mentioned problems, and aims to stabilize the deposition rate of the insulating film and enable precise control of the thickness of the active layer. do.
この発明に係る半導体装置の製造方法は化合物半導体デ
バイス、特にG、A、FETの動作層厚みの再現性を高
め、αVt1kを低減すべく局所的にデバイス構成要素
以外の導電層を形成したものである。The method for manufacturing a semiconductor device according to the present invention improves the reproducibility of the active layer thickness of a compound semiconductor device, particularly G, A, FET, and locally forms a conductive layer other than the device constituent elements in order to reduce αVt1k. be.
(作用)
この発明における半導体装置の製造方法は、プラズマC
VD法によりスルー注入用絶縁膜を堆積する前に局所的
にデバイス構成要素以外の導電層を予め形成する。(Function) The method for manufacturing a semiconductor device according to the present invention includes plasma C
Before depositing the through injection insulating film by the VD method, a conductive layer other than the device constituent elements is locally formed in advance.
以下、本発明による半導体装置の製造方法の一実施例を
図によって説明する。第1図1a)〜10)は製造工程
のうち、スルー注入用絶縁膜の形成に至るまでの工程を
示す断面図である0図において1alは、半絶縁性Ga
As基板(1)の特定領域(9)へ、集束イオンビー
ムOR(F I B ;Focused Ion B@
avn)によりマスクレスイオン注入を行っている状態
を示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings. 1a) to 10) are cross-sectional views showing the steps up to the formation of an insulating film for through injection in the manufacturing process.
A focused ion beam OR (FIB; Focused Ion B@
avn) shows a state in which maskless ion implantation is being performed.
注入本オン種としては、Siが良いであろう、液体金属
イオン源には、1−31 sあるいはA。Si may be a good choice for the injection source; 1-31 s or A for the liquid metal ion source.
−3,−B、などの共晶合金が融点の点で使い易い。Eutectic alloys such as -3 and -B are easy to use due to their melting points.
次いで山)に示すように、SL注入された領域のみ選択
的にレーザ光Iを照射してアニールを行い導電′層(2
)を形成する。さらに(01のように、スルー注入用w
Am膜(2c)を堆積する。第1図のla) 〜(C)
i!FET形成プロセスの初期ステップであり、以降
の工程は、従来方法を説明している第2図(b)〜(g
lと同様のステップをたどるので説明を省略する。Then, as shown in Fig. 2, the conductive layer (2) is annealed by selectively irradiating the SL implanted region with laser light I.
) to form. Furthermore (like 01, for through injection w
Deposit an Am film (2c). Figure 1 la) ~ (C)
i! This is the initial step of the FET formation process, and the subsequent steps are shown in Figures 2(b) to (g), which explain the conventional method.
Since the steps are similar to those in step 1, the explanation will be omitted.
次に作用について説明する。上記の手段によりスルー注
入用絶縁Il!(2c)を堆積すると膜厚バラツキは大
幅に低減し、ウェハ間、ロフト間の均一性は格段に向上
する。Next, the effect will be explained. Through-injection insulation Il! by the above means! When (2c) is deposited, the film thickness variation is significantly reduced, and the uniformity between wafers and between lofts is significantly improved.
素子の高集積度化を阻害しないよう、マスクレスイオン
注入を行なう領域としてはICチップの内部ではなく、
例えば、ダイシングラインなどが都合と考えられる。In order not to impede the high integration of devices, the area for maskless ion implantation is not inside the IC chip.
For example, a dicing line may be convenient.
なお、上記実施例では半絶縁性の半導体基板としてGa
Asを例にとり説明したが、1.Pであっても同様の
効果が得られる。また、ビームアニール用の熱源として
、レーザ光を用いて説明しているが、電子線を用いても
良いことは言うまでもない。Note that in the above embodiment, Ga is used as the semi-insulating semiconductor substrate.
Although the explanation was given using As as an example, 1. Similar effects can be obtained even with P. Furthermore, although a laser beam is used in the description as a heat source for beam annealing, it goes without saying that an electron beam may also be used.
以上のように、この発明によれば、プラズマCVD法に
よりスルー注入用絶縁膜を堆積する前に、半絶縁性基板
主面へ、導電層を選択的に形成したので、゛前記絶縁膜
の堆積速度を安定でき、FETの動作層厚みを精密制御
できる効果がある。As described above, according to the present invention, a conductive layer is selectively formed on the main surface of a semi-insulating substrate before depositing an insulating film for through injection by plasma CVD, so that ``the deposition of the insulating film This has the effect of stabilizing the speed and precisely controlling the thickness of the active layer of the FET.
第1図は本発明の一実施例による半導体装置の製造方法
のうち、スルー注入用絶縁膜形成に至るまでの工程を示
す断面図、第2図は従来の半導体装置の製造方法の工程
を示す断面図で、その中山)〜(幻はこの発明における
製造方法にも用いる。
図において、(11は半絶縁性Ga As基板、(2a
) 。
(2b) 、 (2c)はスルー注入用絶縁膜、(3)
はフォトレジスト、(4a) 、 (4b)はSt−イ
オン1.15)は動作層、(6)は高融点ゲート電極、
(7)はn′″層、(8)はオーミック電極、(9)は
特定領域、Q・は集束イオンビーム、aDはレーザ光、
(2)は導電層である。
なお、図中、同一符号は同一、又は相当部分を示す。
代理人 大 岩 増 雄
第1図
第2図
第2図
手続補正書(自発)
μへ5F427I3
2、発明の名称
半導体装置の製造方法
3、補正をする者
代表者志岐守哉
4、代理人
5、補正の対象
6、補正の内容
−2二FIG. 1 is a cross-sectional view showing steps up to formation of an insulating film for through injection in a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 shows steps in a conventional method for manufacturing a semiconductor device. In the cross-sectional view, (11 is a semi-insulating GaAs substrate, (2a) is also used for the manufacturing method in this invention.
). (2b) and (2c) are insulating films for through injection, (3)
are photoresists, (4a) and (4b) are St- ions 1.15) are active layers, (6) are high melting point gate electrodes,
(7) is an n''' layer, (8) is an ohmic electrode, (9) is a specific area, Q is a focused ion beam, aD is a laser beam,
(2) is a conductive layer. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 2 Procedural amendment (voluntary) to μ 5F427I3 2, Title of invention Method for manufacturing semiconductor devices 3, Person making the amendment Representative Moriya Shiki 4, Agent 5 , Target of correction 6, Contents of correction-22
Claims (1)
基板主面に、プラズマCVD(ChemicalVap
orDeposition)法で絶縁膜を堆積する工程
において、上記絶縁膜の堆積前に、上記半導体基板主面
の特定領域にのみ所望の導伝型を付与する不純物イオン
を選択的に注入するとともに、当該領域のみ選択的にビ
ームアニールを行い、導電層を形成することを特徴とし
た半導体装置の製造方法。Plasma CVD (chemical vapor deposition) is applied to the main surface of a semi-insulating semiconductor substrate on which no conductive thin film is formed.
In the step of depositing an insulating film by a method (orDeposition), before depositing the insulating film, impurity ions that impart a desired conductivity type only to a specific region of the main surface of the semiconductor substrate are selectively implanted, and A method of manufacturing a semiconductor device, characterized in that a conductive layer is formed by selectively performing beam annealing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3805788A JPH01212443A (en) | 1988-02-19 | 1988-02-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3805788A JPH01212443A (en) | 1988-02-19 | 1988-02-19 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01212443A true JPH01212443A (en) | 1989-08-25 |
Family
ID=12514881
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3805788A Pending JPH01212443A (en) | 1988-02-19 | 1988-02-19 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01212443A (en) |
-
1988
- 1988-02-19 JP JP3805788A patent/JPH01212443A/en active Pending
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