JPH01211984A - Superconducting field effect transistor - Google Patents

Abstract

PURPOSE:To stabilize the operation at a low temperature, by making impurity concentration in a channel of semiconductor low, arranging thereunder a semiconductor part of high impurity concentration of conductivity inverse to the channel part, and making it contain impurity by which the amount carrier is not frozen at a temperature of the device operation. CONSTITUTION:For a channel 2, semiconductor 7 of low concentration is used, under which a semiconductor part 6 of high impurity concentration of conductivity inverse to the channel part 2. The semiconductor part 6 is made to contain impurity by the amount of which carrier is not frozen at a temperature of device operation. Thereby it can be prevented for the height of a potential barrier between a source 3a and a drain 3b to decrease on account of freeze-out of carrier, so that the generation of punch through phenomena can be prevented and the operation is stabilized.

Description

[Detailed Description of the Invention] [Uses of the Invention] The present invention relates to a superconducting device constructed by combining a superconductor and a semiconductor, and particularly to a structure of a superconducting field effect transistor device that is stable in operation and easy to manufacture. and materials.

[Background of the invention]

Regarding superconducting field effect 1-transistor devices that combine semiconductors and superconductors, see Journal of Applied Physics, Volume 51, 1980, page 2736.
ics, Vol, 5 L, l 980+ pages
, 2736). Further, in this transistor device, a structure in which an impurity concentration distribution is provided in a semiconductor portion is disclosed in Japanese Patent Laid-Open No. 190990/1983.

[Problem to be solved by the invention]

In the former of the above conventional technologies, either a high concentration of impurity is introduced into the semiconductor channel portion to prevent carriers from freezing, or even if the channel portion has a low impurity concentration, the underlying semiconductor substrate portion The impurity concentration is not high enough to prevent carrier freezing. Furthermore, in the latter of the above-mentioned conventional techniques, it is disclosed as an example that a layered portion having a higher impurity concentration than the semiconductor channel portion is provided, but the dimensions or impurity concentration,
Furthermore, there were no clear limitations on the types of impurities. Therefore, let's talk about the prior art! ? Although consideration has been given to the gain of the device, consideration has not always been given to the stable operation of the device at extremely low temperatures. In other words, at extremely low temperatures, when the impurity concentration in the semiconductor channel decreases, carriers freeze out. The so-called punch-through phenomenon occurs because the electrostatic potential between
It has been newly discovered that a problem arises in which the device cannot operate stably.

In order to prevent this, it is effective to provide a portion with high impurity concentration at the bottom of the channel, but in this case as well,
Great effects could be obtained when the shape satisfied special conditions. This is a novel effect that had not been foreseen in the prior art, and moreover, conventional known techniques alone were insufficient to achieve this effect.

An object of the present invention is to solve the problems of the prior art and provide a superconducting field effect transistor that operates stably at low temperatures.

[Means to solve the problem]

The purpose of the above is to lower the impurity concentration in the channel of the semiconductor, and to provide a semiconductor part with a high impurity concentration below which has conductivity opposite to that of the channel part, and also to lower the impurity concentration in the semiconductor channel. This is achieved by containing impurities to the extent that the carrier does not freeze at the temperature at which the device is used.

Furthermore, as a preferred embodiment of the present invention, the relationship between the distance X between the semiconductor portion with high impurity concentration and the channel and the distance ML between the source and drain is selected such that L/X is larger than 4/π. This is very important.

[Effect]

Using a semiconductor with a low impurity concentration for the channel causes carriers to freeze in the semiconductor in the channel section at temperatures at which the superconducting field effect transistor can operate, but because there are few impurities in the semiconductor, carrier mobility is reduced. This makes it possible to increase the processing dimensions of the device necessary for the superconducting field effect transistor to operate, i.e., the distance between the source and drain superconducting electrodes. Therefore, it is possible to improve the precision of processing dimensions during device manufacturing, and to improve the uniformity and reproducibility of device characteristics.

However, in addition to the above-mentioned advantages, the use of a semiconductor with a low impurity concentration brings about the problem of the punch-through phenomenon as described above. To solve this problem, a highly impurity-concentrated semiconductor part with conductivity opposite to that of the channel part is provided below the channel, and the highly impurity-concentrated semiconductor part is doped with impurities to the extent that the carriers do not freeze at the operating temperature of the device. Since the potential barrier between the source and the drain is included, it is possible to prevent the height of the potential barrier between the source and the drain from being lowered due to freeze-out of carriers, and therefore, the occurrence of bunch-through phenomenon can be prevented. If the relationship between the distance X between the high impurity concentration semiconductor part and the channel and the distance between the source and drain is selected so that L/X is greater than 4/π, the bunch-through phenomenon can be prevented. The protective effect can be greatly increased. When L/X is 47π or less, there is almost no effect of preventing the bunch-through phenomenon by providing the above-mentioned high impurity concentration semiconductor portion. The reason for this is determined as follows.1 Even if the electrostatic potential inside the superconducting field effect transistor of the present invention is treated as a two-dimensional problem, it can be analyzed with sufficient accuracy.

Considering a region with two-dimensional width and height X, the upper end of this region is the channel portion, and the lower end is the semiconductor portion with the high impurity concentration. Therefore, a source and a drain exist at the left and right ends, respectively. Drain voltage VD
Then, the potential ψ8 at the center of the above two-dimensional region is as follows, where m is a positive odd number.

If L/X is equal to or greater than 4/π, the value in parentheses following 5ach is greater than 2.

The sum of this series is dominated by the term m=1. At this time, the value of ma8 is the sum of approximately half the value of the potential vP of the semiconductor region with high impurity concentration.

It can be written as 2 Mei 2x. In general, VPT is applied with a specific sign as Ma8 is increased, and Vri is applied with a specific sign as Ma8 is decreased. Therefore, vpT and■.

The two act as if they cancel each other out. (2) As /X becomes smaller, the second term on the right side of equation (2) increases exponentially. -VPT is used at a value of about Vr), then from equation (2), ψ8>0, and in order to prevent the bunch-through phenomenon from occurring, is the value of L/X equal to 4/π?

It needs to be larger than this, and only in this case can the bunch-through phenomenon be prevented and a superconducting field effect transistor with stable operation possible.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples. 1st
A first embodiment of the present invention will be described with reference to the drawings. A high impurity concentration P+ substrate 6 containing boron as an impurity at a concentration of Ix1019C11-3 is heated to a temperature of about 650°C.
A low impurity epitaxial layer 7 containing sb as an impurity is grown in an ultra-high vacuum in a molecular beam epitaxy apparatus. At this time, sb of low impurity epitaxial M7
The concentration is 1×101°clI-3, and the thickness is about 0.
It is set to 4 μm. then by thermal oxidation in an oxygen atmosphere.

Gate oxide film 5 with a thickness of about 15 nm made of S x O2
form. Next, polycrystalline silicon containing phosphorus as an impurity with a thickness of about 150 nm is formed by chemical vapor deposition (CVD), followed by SiO2 with a thickness of about 1100 nm.
After growing two films by chemical vapor deposition (CVI), this is processed by dry etching using a photoresist as a mask to form an n+ doped polycrystalline silicon gate. Next, 5j with a thickness of about 150 nm
A 5i02 film is formed by chemical vapor deposition (CCVD) and then vertically removed by dry etching to form an oxide spacer 8 made of 5i02.

As+ ions were lightly IXed at an acceleration voltage of 15 KeV.
The implantation is performed to a density of iO"cn+-" followed by annealing in nitrogen at about 850 DEG C. for 20 minutes.

As a result, a high impurity concentration semiconductor source 3a and a high impurity concentration semiconductor drain 3b can be formed. Here the distance between the two #
The value of liL is 0.6 μm. Next, Nb was deposited to a thickness of approximately 200 nm by electron beam evaporation in an ultra-high vacuum, and then, using the electron beam resist pattern as a mask, reactive ion etching was performed using CF'4 gas. By processing and forming a superconducting source electrode 1a and a superconducting drain electrode 1b, a superconducting field effect transistor of the present invention can be manufactured.

In this embodiment, the P+ substrate 6 with a high impurity concentration acts as a semiconductor portion with a high impurity concentration, and the relationship between the distance between this and the channel -X and the length L of the channel is I,
/X = 0.610.4 = 1.5, but this value should be selected so that L / can be fully reached.

Next, a second embodiment of the present invention will be described using FIG. In this embodiment, after forming the n+ doped polycrystalline silicon gate 4, in the first embodiment, StO□
An example is shown in which 513N4 is used instead of the one that used . Other manufacturing steps may be the same as those in the first embodiment of the present invention.

Are you skilled in the above examples? In the above, an n-type semiconductor was used for the source and drain (3a, 3b) of the semiconductor, and a p-type semiconductor was used for the channel and the semiconductor portion with high impurity concentration. You can use it by replacing it. Furthermore, although Nb was used as the superconducting material, it goes without saying that Nb compounds such as NbN, Pb alloys, and even oxide superconductors may be used in place of Nb. Also, Si may be used as the semiconductor material. InAs, InSb, InP, GaP, GaAs,
It goes without saying that a material such as Ge may also be used.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize a superconducting field effect transistor which is easy to manufacture and whose operation is stable.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a portion of a superconducting field effect transistor according to a first embodiment of the invention, and FIG. 2 is a sectional view showing a portion of a superconducting field effect transistor according to a second embodiment of the invention. 1a...Superconducting source electrode, 1b...
superconducting drain electrode, 2... semiconductor channel,
3a...High impurity concentration semiconductor source, 3b...
...High impurity concentration semiconductor drain, 4...
n+ doped polycrystalline silicon gate, 5...gate oxide film, 6...high impurity concentration P+ substrate, 7.
...Low impurity concentration epitaxial layer, 8...
...Oxide spacer, 9.Old...Silicon nitride spacer.

Claims (1)

[Claims] 1. A source and a drain consisting of a semiconductor and a plurality of superconductors provided thereon with ohmic contact; A channel through which a current can flow and into which a superconducting wave function can seep from the source and drain, and a channel between the superconductor on the semiconductor, and a voltage is applied thereto. and a control electrode that can change the concentration of mobile carriers in the channel, and the distance between the source and drain is such that the superconducting wave functions from both the source and drain superconductors overlap. In a superconducting field effect transistor, the control electrode is electrically insulated from the semiconductor, and the control electrode is electrically insulated from the semiconductor, and the control electrode is electrically insulated from the semiconductor, and the overlap is varied by changing the concentration of mobile carriers in the semiconductor channel. A high impurity concentration region containing an impurity at a concentration high enough to cause degeneration of at least one of the semiconductors is provided, and the high impurity concentration region is provided below the channel, and majority carriers in the channel are electrons. In order to strengthen the superconducting bond between the source and drain in this way, the conductivity of the high impurity concentration region is p-type, and the majority carriers are holes, so that the superconducting bond between the source and drain is strengthened. A superconducting field effect transistor characterized in that the conductivity of the high impurity concentration region is n-type when the coupling is to be strengthened. 2. In the superconducting field effect transistor device according to claim 1, a ratio L between the length L of the channel and the distance x between the channel and the high impurity concentration region;
A superconducting field effect transistor characterized in that /X is selected to be a value of 4/π or more. 3. A superconducting field effect transistor device according to claim 1 or 2, wherein the value of the distance X between the channel and the high impurity concentration region is 50 nm or more. . 4. In the superconducting field effect transistor according to claim 1, the material constituting the channel is silicon, and the impurity concentration is 1×10^1^6 impurities/c.
A superconducting field-effect transistor characterized in that it is less than m^2. 5. In the superconducting field effect transistor according to claim 1, the material constituting the channel is InA.
s, InSb, GaSb, InP, CaP, GaAs,
Or a superconducting field effect transistor characterized by being selected from Ge. 6. A source and a drain consisting of a semiconductor, a plurality of superconductors provided thereon with ohmic contact, and a source and drain in the semiconductor through which a current can flow between the source and drain. , and a channel into which the superconducting wave function can seep out from the source and drain, and a channel between the superconductors on the semiconductor, and the movable wave function in the channel is provided by applying a voltage. and a control electrode capable of changing the concentration of carriers, and the distance between the source and the drain is selected to such an extent that the superconducting wave functions from the superconductors of both the source and the drain overlap, and in a superconducting field effect transistor in which this overlap is changed by changing the concentration of mobile carriers in the semiconductor channel, that is, by applying a voltage to the control electrode, the control electrode is electrically insulated from the semiconductor, A high impurity concentration region containing an impurity at a concentration high enough to degenerate at least one of the semiconductors is provided in the semiconductor, and the high impurity concentration region is provided so as to surround the channel, and the high impurity concentration region is provided so as to surround the channel. When the majority carriers are electrons to strengthen the superconducting bond between the source and the drain, the conductivity of the high impurity concentration region is p-type, and the majority carriers are holes to strengthen the superconducting bond between the source and the drain. A superconducting field effect transistor characterized in that the conductivity of the high impurity concentration region is n-type when the superconducting bond between the drains is strengthened. 7. In the superconducting field effect transistor device according to claim 6, a ratio L between the length L of the channel and the distance X between the channel and the high impurity concentration region
A superconducting field effect transistor characterized in that /X is selected to be a value of 4/π or more. 8. A source and a drain consisting of a semiconductor, a plurality of superconductors provided thereon with ohmic contact, and a source and drain in the semiconductor through which a current can flow between the source and drain. , and a channel into which the superconducting wave function can seep out from the source and drain, and a channel between the superconductors on the semiconductor, and the movable wave function in the channel is provided by applying a voltage. and a control electrode capable of changing the concentration of carriers, and the distance between the source and the drain is selected to such an extent that the superconducting wave functions from the superconductors of both the source and the drain overlap, In a superconducting field effect transistor in which this overlap is changed by changing the concentration of mobile carriers in the semiconductor channel, that is, by applying a voltage to the control electrode, to the extent that at least one of the semiconductors degenerates in the semiconductor. When the superconducting coupling between the source and drain is strengthened by making the majority carriers in the high concentration channel electrons, the conductivity of the high impurity concentration region is p-type, and the majority carriers are holes. In order to strengthen the superconducting coupling between the source and the drain in a certain way, the conductivity of the high impurity concentration region may include at least a step of providing a high impurity concentration region containing an n-type impurity. A method for manufacturing a superconducting field effect transistor, characterized by: 9. An integrated circuit comprising at least the superconducting field effect transistor according to claim 1 or 6. 10. An electronic computer comprising at least the superconducting field effect transistor according to claim 1 or 6.