JPH01209765A - Thin film transistor - Google Patents

Abstract

PURPOSE:To remarkably improve high frequency characteristics by providing a step on an insulation substrate, forming a semiconductor film along the side of the step, and further respectively disposing a source electrode and a drain electrode on the lower and upper step faces of the substrate. CONSTITUTION:A step 13 made of an upper step face, a lower step face and a side for connecting them is formed on an insulation substrate 21 made of a glass substrate or the like, a source electrode 22 is formed on the lower step of the substrate 21, and a drain electrode 23 is formed on the upper step. First and second contact layers 24, 25 formed of phosphorus (P)-doped N<+> type amorphous silicon are formed, and a semiconductor film 26 made of an intrinsic amorphous silicon is so formed on the layer 24 along the side face of the step 13 of the substrate 21 and the side face of the laminated layer of the drain electrode 23 and the layer 25 as to electrically connect the layers 24, 25.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a thin film transistor, and more particularly to a vertical thin film transistor in which a channel region is formed in a superimposed direction with respect to a substrate.

[Prior art and its problems]

Since liquid crystal display devices used in liquid crystal televisions and the like require high contrast and high time-division driving, it has been proposed to use an active matrix method.

This active matrix type liquid crystal display device includes a substrate on which a plurality of transparent electrodes serving as pixels and switching elements connected to the transparent electrodes are arranged in a matrix, and another substrate that faces the plurality of transparent electrodes arranged on this substrate. It includes a substrate provided with a transparent electrode, and a liquid crystal sealed between these substrates. It has been proposed to use a thin film transistor as the switching element.

By the way, as described above, it is desirable for a thin film transistor (hereinafter referred to as TPT) used as a switching element of a liquid crystal display device to have a small element area and to allow a large current to flow.

However, when a TPT operates, the magnitude of the current flowing between the source and drain, that is, the magnitude of the on-current, depends on the channel length of the semiconductor film, and the shorter the channel length, the greater the on-current (but in the case of a VT-type TPT, Because there is a limit to the accuracy of vacuuming during the photolithography process used during the manufacturing process, the channel length cannot be shortened, the source and drain electrodes cannot be made large, and the device area is limited by the channel length. 1, and it has not been possible to reduce the device area because there is a limit to the etching accuracy in the process to shorten the channel length.To solve this problem, vertical TPT was devised.

In vertical TPT, the channel is formed in the thickness direction of the deposited semiconductor film, that is, in the direction perpendicular to the substrate. The length can be shortened and a large on-current can be obtained. Furthermore, since there is no need to consider the channel length when determining the element area on the substrate, miniaturization is the key. In this way, vertical TPTs can have extremely short channel widths (as compared to horizontal TPTs, the channel width can be made extremely short, large source and drain electrodes can be obtained, and the area on the substrate can also be made very small). Therefore, when a vertical TPT is used as a switching element in an active matrix liquid crystal display device, the aperture ratio of the transparent electrode that becomes a pixel is increased compared to when a horizontal TPT is used as a switching element. It is possible,
Image quality is improved.

FIG. 2 is a sectional view of a conventional vertical TPT.

As shown in the figure, chrome (
A source electrode 2 made of Cr) or the like is formed, and one end of the source electrode 2 is doped with phosphorus (P) or the like.
) first contact layer 3 made of amorphous silicon;
is formed.

Furthermore, a first insulator 11 made of silicon nitride (SiN) or the like is formed on one end of the laminated portion of the source electrode 2 and the first contact layer 3 and on a portion of the insulating substrate l where the source electrode 2 is not formed. 2! 4 is formed. On this first insulating film 4, a second contact layer 5 made of n+ amorphous silicon doped with phosphorus (1') or the like and a drain electrode Ff made of chromium (Cr) or the like are formed.
A6 is sequentially laminated and a portion where the first insulating film 4 on the first contact N3 is not formed;
and the first insulating film 4 and the second contact WI5
A semiconductor film 7 made of intrinsic amorphous silicon is formed to cover the laminated portion of the drain electrode 6 and the drain electrode 6. Furthermore, the surface of this semiconductor film 7 and part of the source electrode 2 and drain electrode 6 are covered with silicon nitride (S).
A second insulating film (gate insulating film) 8 made of
is formed. Further, on the second insulating film 8 above the semiconductor film 7, a gate electrode 9 made of aluminum (A7 or the like) is formed.
Since the respective electrodes and layers overlap as described above, there are gaps between the gate electrode i9 and the first contact layer 3, between the gate electrode 9 and the source electrode 2, and between the gate electrode 9 and the second contact layer 3.
Between contact number 1115, game! - A large parasitic capacitance is generated between the electrode 9 and the drain electrode 6 and between the first contact I-rrJ3 and the second contact layer 5 because the area is large.

For this reason, high frequency operation was not possible.

[Purpose of the invention]

SUMMARY OF THE INVENTION In view of the above conventional problems, an object of the present invention is to provide a thin film transistor capable of high frequency operation.

[Key points of the invention]

In order to achieve the above object, the present invention includes an insulating substrate having a stepped portion a, and a first electrode that is MIHed on the upper surface of the lower step of the insulating substrate along the side surface of the stepped portion of the insulating substrate. , a first contact I-N, a semiconductor film, a second electrode and a second contact 1-Pi which are laminated in sequence on the upper surface of the upper stage of the insulating substrate along the side surface of the semiconductor, a gate insulating film having a stepped portion covering the first contact layer, the second contact layer and the semiconductor film; It is characterized by having a gate electrode disposed along the side surface of the stepped portion of the L film.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1(h) is a sectional view of a vertical TPT according to an embodiment of the present invention. As shown in FIG. 6(h), the insulating substrate 21 made of a glass substrate or the like forms an rIt difference part 13 consisting of an upper surface, a lower surface, and a side surface connecting these surfaces. A source electrode 22 is formed on the lower surface of the Fi 21, and a drain electrode 23 is formed on the upper surface. source f
The f electrode 22 and the drain electrode 23 are made of, for example, chromium (Cr
), molybdenum (Mo), titanium (Ti), tungsten (W), etc. Furthermore, on the side of the stepped portion 13 on the source electrode 22 and on the side of the stepped portion 13 on the drain electrode 23, there are provided a first contact 1-u24 and a second contact made of n-to amorphous silicon doped with phosphorus (P) or the like, respectively.
contacts t·m25 are formed, and these 11th
A semiconductor film 26 made of intrinsic amorphous silicon that electrically connects the second contactors 1-1424 and 25.
However, the insulation J! It is formed on the first contact I-Ji 24 along the side surface of the stepped portion 13 of the i slope 21 and the side surface of the laminated portion of the drain electrode 23 and the second contact layer 25 . A gate insulating film 27 made of silicon nitride (SiN) or the like is formed to cover the first contact layer 24, the semiconductor film 26, and the second contact layer m25, and the side surface of the stepped portion of the gate insulating film 27 is formed. A gate electrode 28 made of aluminum (Aj, etc.) is formed along the line.

In this way, the vertical TPT of this example minimizes the overlamp of each electrode and layer, so it is different from the conventional vertical TPT.
There is no parasitic capacitance between the first contact layer 24 and the second contact 7!25 that occurred in This is significantly reduced compared to conventional vertical TPT. Therefore, the transfer characteristics are improved and high frequency operation becomes possible.

Next, the manufacturing method of this embodiment configured as described above will be explained as follows.
v! This will be explained with reference to J(+3) to (h).

First, as shown in FIG. 1(n), a photoresist pattern 12 is formed on an insulating substrate 21 made of a glass substrate or the like by a photolithography process, and then reactive ion etching (1?) using CF4 gas or the like is performed. active
The surface of the insulating substrate 21 on which the photoresist pattern 12 is not formed is etched several micrometers by the ion etching method. Etching by the zero-reactive ion etching method is anisotropic etching with strong directionality in the vertical direction with little side etching. Therefore, the insulating substrate 2
The side surface of step portion 13 of No. 1 is machined almost vertically.

Next, the surface of the insulating substrate 21 is coated with chromium (C
r), a metal film of molybdenum (Mo), titanium (Ti), tungsten (W), etc. is deposited to a thickness of, for example, about 2000 mm. ! ! By using the "4 film formation method with strong directivity in the vertical direction, almost no metal film is attached to the side surface of the stepped portion 13 of the insulating substrate 21. After that, the insulating group F
The i21 body is immersed in the metal film etching solution for a short time to completely remove the metal film attached to the side surface of the stepped portion 13 of the insulating substrate 21. As a result, as shown in FIG. 1(b), the source electrode 2 is placed on the lower surface of the I21 edge group Fi21.
2, a drain electrode 23 is formed on the upper surface.

Next, as shown in FIG. 1 (0), ECR plasma CVD
Deposit n÷14 amorphous silicon doped with phosphorus (P) or the like to a thickness of, for example, 500 μm using the cyclotron resonance plasma CVD method.EC
Since the R plasma CVD method has strong directionality in the vertical direction, the thickness of the amorphous silicon 14 that adheres to the side surface of the stepped portion 13 of the insulating substrate 21 is the same as that of the flat portion of the insulating substrate 21 (
It is extremely thin compared to the n+ amorphous silicon 14 attached to the upper and lower surfaces (for example, IIF and 11N O
By etching the entire surface of the insulating substrate 21 for a predetermined period of time using the mixed solution of No. 3, only the n4 amorphous silicon 14 attached to the side surface of the stepped portion 13 can be removed. Furthermore, the host resist pattern 15 is applied to the side surface of the stepped portion 13 of the laminated portion including the drain electrode F123 and the n+ amorphous silicon 14, including the side surface of the stepped portion 13 of the insulating substrate 21, the source TA electrode 22, and the n+ amorphous silicon 14. After m layers of silicon 14 are formed to cover part of the side surface side of the stepped portion 13, etching is performed to form the first contact layer 24 and the second contact layer 24, as shown in FIG. 1(d). A contact layer 25 is formed.

Subsequently, as shown in FIG. 1(d), a source electrode 22 is formed on the insulating substrate 21 by a plasma CVD method or the like.
Direct amorphous silicon 1 is formed covering the drain electrode 23, the first contact rf 24, and the second contact layer 25.
6 is deposited, for example, to a thickness of about 1000. Since the plasma CVD method has good step coverage, the Ω-type amorphous silicon 16 is formed to a sufficient thickness even on the side surfaces of the step portion 13. Then, as shown in FIG. 1(L), the entire surface of the intrinsic amorphous silicon 16 is etched using, for example, CF4 gas by a reactive ion etching method to form the semiconductor film 2.
As mentioned above, the 0-reactive ion error/fugu method for forming 6 has a strong vertical directionality (and strong anisotropy), leaving only the semiconductor film 2G formed on the side surface of the stepped portion 13. , (all the intrinsic amorphous silicon 16 of the film can be etched).

Furthermore, as shown in FIG. 1(f), an insulating film 27 made of silicon nitride (SiN) or the like is formed by a plasma CVD method or the like on the source electrode 22, drain electrode 23, first contact layer 24, etc.
The second contact layer 25 and the semiconductor film 26 are deposited on the entire surface of the insulating substrate 21 to a thickness of about 3,000 layers, and then aluminum (A1) is deposited on the insulating film 27 by sputtering or the like. Deposit a gold film for one day.

Both the insulating film 27 formed by the plasma CVD method and the gold fs film 18 formed by the sputtering method have good step coverage.
8 can be formed.

Subsequently, as shown in FIG. 1(a), the entire surface of the metal film 18 is etched using CCj14 gas or the like using a highly anisotropic reactive ion etching method, thereby forming a gate electrode along the stepped side surface of the insulating film 27. 28 and r
The insulating layer II is formed above the first contact layer 24, the second contact layer 25, and the semiconductor film 26 by a photolithography process. 2127, the other insulating film 27 is etched to form a vertical T as shown in FIG. 1(h).
F'r is obtained.

As described above, in this embodiment, since the overlamp of each electrode, layer, etc. is minimized, the parasitic capacitance generated between each electrode and layer is significantly reduced compared to the conventional vertical TPT. In addition, the specific values of the film thicknesses of the source electrode 22, drain electrode PfA 23, first contact layer 24, second contact layer 25, semiconductor film 26, and gate ff1lfi28 shown in the above example are as follows: Yes, but not limited to the above specific values.

Further, the semiconductor film 26 may be made of polycrystalline silicon, Cd5aSTa, etc. other than intrinsic amorphous silicon.

[Invention glue J fruit]

As explained above, according to the present invention, a stepped portion is provided on an insulating substrate, a semiconductor film is formed along the side surface of the stepped portion,
Furthermore, since the source electrode and drain electrode are arranged on the lower and upper surfaces of the insulating substrate, respectively, the parasitic capacitance is significantly reduced compared to the conventional vertical 1'FT. As a result, the high frequency characteristics have been significantly improved compared to the conventional model. In addition, since the present invention has a vertical structure, the on-current can be large, so it can be used for logic elements. Therefore, it is possible to manufacture logic ICs using TPT, and the carrier mobility is small. Even by using TPT, which uses amorphous silicon as a semiconductor film, it becomes possible to integrate the driving circuit of the liquid crystal display panel on the surface of the active matrix substrate.As a result, the productivity of the liquid crystal display panel can be improved and the It becomes possible to reduce costs

[Brief explanation of the drawing]

FIGS. 1(a) to (h) are cross-sectional views of an embodiment of the present invention and diagrams showing a manufacturing method, and FIG. 2 is a cross-sectional view of a conventional vertical TPT. 21... Insulating substrate, 22... Source electrode, 23... Drain electrode, 24... First contact layer, 25... Second contact layer, 26... Semiconductor film, 27 ...Gate insulating film, 28...Gate electrode. Patent applicant Casio Computer Co., Ltd. (a) (b) (C) (d) (e) (f) Figure 1

Claims (1)

[Claims] an insulating substrate having a stepped portion formed of an upper surface, a lower surface, and a side surface connecting these surfaces; a source electrode and a first layer sequentially stacked on one surface of the stepped portion along the edge of the stepped portion; a contact layer, a drain electrode and a second contact layer that are sequentially laminated on the other surface of the stepped portion along the edge of the stepped portion; and a drain electrode and a second contact layer that are formed along the side surface of the stepped portion; a semiconductor film connecting two contact layers; an insulating film covering the first contact layer, the semiconductor film, and the second contact layer; and a gate formed on the insulating film along the semiconductor film. A thin film transistor having an electrode.