JPH01206642A - Pattern and method for capacity measuring in semiconductor device - Google Patents

Abstract

PURPOSE:To find an accurate gate-source capacity and an accurate gate-drain capacity and to obtain the accurate characteristics of an equivalent circuit by a method wherein measurement of the capacities is conducted using two patterns of a first FET pattern, which is a FET pattern whose gate, source and drain are respectively isolated from one another, and a second FET pattern, which is a diode pattern whose source and drain are short-circuited between each other. CONSTITUTION:A capacity characteristic I obtainable by a first FET 12 before a pinch-off is both of a gate-source capacity Cgs and a gate-drain capacity Cgd and the characteristic I obtainable after the pinch-off is the Cgs only. A capacity characteristic II obtainable by a second FET 11 on one side before the pinch-off is the same as the characteristic I and the characteristic II obtainable after the pinch-off becomes of a value obtainable by adding the capacity Cgs to the characteristic I. A capacity Cgdf of a difference between the characteristics I and II after the pinch-off is the gate-drain capacity to hold an almost constant value regardless of the magnitude of a gate-source voltage Vgs and if the Cgdf is subtracted from the characteristic I or II before the pinch-off, the accurate capacity Cgs before the pinch-off is found.

Description

[Detailed Description of the Invention] [Summary] Regarding the capacitance measurement pattern and capacitance measurement method used to find the dynamic equivalent circuit of an FET, this paper aims to find an accurate value of the gate-source capacitance or the drain-to-drain capacitance. This FE, such as an FET whose purpose is to separate the goo 1 terminal, source terminal, and drain terminal, respectively.
The source terminal and the train terminal are short-circuited [:ET and T are formed adjacently on the same wafer.
[configuration, and using a capacitance measurement pattern that results in this configuration,
The gate-to-source voltage (V) vs. gate S and source-to-source voltage characteristics before and after pinch-off in each FEI- above were calculated, and
By finding the capacitance of the difference between the two gate-source capacitance W characteristics, and subtracting the capacitance of the eye difference from the gate-source capacitance characteristic of a5 before pinch-off,
゛... Find the capacitance between sources.

[Industrial Field of Application] The present invention relates to a capacitance measurement pattern and a capacitance measurement method used when determining a dynamic equivalent circuit of an F'ET.

To find the equivalent circuit of a FET, for example, in the circuit diagram shown in Fig. 4, it is necessary to find the capacitance (i.e., the capacitance Cg3 between the gate G and the source S, and the capacitance fflcgd between the gate G and the drain D). In this case, it is necessary to separate the gate-source capacitance C and the drain capacitance Cgd in the equivalent circuit.

(Prior art) Conventionally, the so-called FET pattern and the stored measurement patterns as shown in Fig. 5 have been used to measure the respective capacitances hi. Padded,
3 is a source pad, and 4 is a train pad. In this case, for example, to measure the gate-source capacitance Cg8, a needle is applied to the gate pad 2 and the source pad 3 to measure the capacitance between each pad. As shown in FIG. 1(B), the gate-source capacitance Cg is measured by varying the gate-source voltage Vg, and the characteristics shown by the solid line 2 are obtained. Here, vth is the voltage between the drain and the source at which the current flowing between the drain and the source becomes zero.

As shown in Figure 2 (△), before FEI- is pinched off (during the period when the gate-source voltage V is shallow and exceeds v1h9$), the active layer (hatched) is connected between the source and drain. , Needle to source S and goo L-G (
Even though you think you are measuring the gate-source capacitance by applying the gate-source open sound IC and the gate-drain open sound 1 cad (C(lsDI
10 (IS+)2+C(Idp1+Codp2+Cgs
d) is being measured. On the other hand, Fig. 2 (B)
As shown in Figure 2, after the FET is pinched off (S period in which the gate-source voltage V is deep and is below vth), the active layer (hatched) is separated between the source and drain, so the source is open to goo 1. Sound fB:cgs(0
g8,1→-cgsp2> has been measured.

- To - 1 4 - Therefore, a phenomenon in which the capacitance changes rapidly after vth is observed.

[Problem to be solved by the invention]

In the conventional example described above, before pinch-off, both the gate-source capacitance C and the goo1-drain open sound S are measured, but after the pinch-off, only the goo-source capacitance lC is measured. There was a problem with S that made it impossible to accurately measure the capacitance C between source and source.

SUMMARY OF THE INVENTION An object of the present invention is to provide a measurement pattern and a measurement method capable of determining an accurate value of source capacitance or gate-drain capacitance.

[Means for solving the problem] The above problem is solved by the first FET, which has its gate terminal, source terminal, and drain terminal separated from each other.
Using a capacitance measurement pattern formed on a second FE with the same size as T and whose source terminal and train terminal are short-circuited, each of the above-mentioned FETs is
The gate-source voltage (V, ,) vs. gate-source capacitance characteristics before and after pinch-off are determined, the difference in the two gate-source capacitance characteristics after pinch-off is determined, and the capacitance before pinch-off is determined. This problem is solved by a capacitance measurement method applied to a semiconductor device, which is characterized in that the gate-source capacitance before pinch-off is determined by subtracting the eye difference capacitance from the gate-source capacitance characteristic.

[Effect]

The acceptable characteristic I obtained by the first FET is both the gate-source capacitance IC and the gate-drain capacitance tC, d before pinch-off, and the gate-source capacitance tC, d after pinch-off.
Source question and answer icg8 only.

The capacitance characteristic ■ obtained by one of the second FEI- is
Before pinch-off, the characteristic is the same as ■, and after pinch-off, the value is the characteristic plus the gate-to-train capacitance Cgd (the source and drain terminals of the second FET are short-circuited, so after pinch-off Cgd will also be measured). Capacitance Cgd of difference between characteristics after pinch-off
f is the gate-drain capacitance that maintains a substantially constant value regardless of the magnitude of the gate-source voltage Vg, which is 1. If you subtract C from the characteristic ■ or ■ before pinch-off, you will get the exact game before pinch-off (
ldf-source question and answer icg8 is obtained.

〔Example〕

FIG. 1(A) shows a plan view of a pattern of the present invention.

In the figure, 10 is a wafer, and adjacent j on this wafer 10
Different capacitance measurement patterns are provided for the FETs 11 and 12, respectively. That is, FET 11 is substantially the fifth
Although the so-called [:ET pattern is the same as the conventional example shown in the figure, arm patterns 13a and 14a are provided on the source pad 13 and the drain pad 14, respectively, both pads are not connected and are separated from each other. There is. 18 is a gate bat. One hET is a so-called diode pattern, and a short circuit pattern 17 is provided on a source pad 15 and a drain pad 16, and both pads are connected to each other. 19 is a gate pad.

The present invention uses these two measurement patterns to obtain accurate values of gate-source capacitance aCg8 and gate-drain capacitance Cgd. t=
While arm patterns 13a and 14a shaped like the short circuit pattern 17 of E T 12 are provided, if both measurement patterns are provided at separate positions on the same wafer 10, the influence of wafer characteristic variations will occur, so this should be avoided. Therefore, both measurement patterns are provided adjacently.

It is also possible to provide only one measurement pattern and connect the drain and source using the wire A7, but in this method, the reliability of the data is lost due to the influence of the capacitance between the wire and the FET. This capacitance is undesirably large, and the capacitance changes depending on how the wires are connected.

In the present invention, first, the gate-source question and answer fficg are determined using the measurement pattern of the FET 11 (substantially the same FET pattern as in the conventional example). This is shown in Figure 2 (A),
Since this is exactly the same as explained in (B), the explanation thereof will be omitted. As a result of this measurement, the solid line ■ in Figure 1 (B)
obtain the characteristics of

Next, the gate-source capacitance C03 is determined using the measurement pattern (diode pattern) of the FET 12. Third
As shown in the figure (A>), the active layer is connected between the source and train before Vinciono, so the short circuit pattern 17
Even if a capacitor is provided, it is actually measuring the same capacitance as shown in Figure 2 (A), that is, both the gate-source capacitance Cg and the drain capacitance ICgd. It turns out.

As shown in FIG. 3(B), after the pinch-off, the active layer is separated between the source and drain. In this case, since the pattern 17 is provided, when the needle is applied to the pads 1 to 19 and the source pad 15, the gate-source capacitance Cg and the gate-drain capacitance icgd are measured. , = 1 n − Cgspl + Cgsp2 + Cgdpl 10 gd
This means that p2 is being measured. This is shown in Figure 2 (B)
When compared with , Cgdpi+C(]dp2 has been newly added. Therefore, the measured capacitance using the measurement pattern of FET12 is as shown by the broken line ■ in Figure 1 (B), and before the pinch-off, it is a solid line. The same value as I, after pinch-off, becomes the value of the solid line ■ plus the gate-drain capacitance ICgd.

Here, CQS-Cgspl + C(]SD2” q
cl=C(ldl)1+Cgdp2, and these values are mainly determined by the pattern itself, and hardly change regardless of the magnitude of the gate-source voltage Vos. On the other hand, in the depletion layer under the gate, 3.
varies greatly depending on the magnitude of the gate-source voltage Vg, and becomes zero at Vth. That is, if the area of each of the opposing electrodes is 81 and the distance between the opposing electrodes is t, then the capacitance C-
Since ε(S/l), the capacitance c gsd in the depletion layer under the gate is equal to the gate-source voltage V0. For example, the depletion layer can be changed to a small value by avoiding the change to a small value (thereby increasing the depletion layer).

Therefore, as shown in FIG. 1 (-A), area A is C'l;
1dpl+C(]dp2”' cgdr (that is,
Cgd is constant regardless of gate-source voltage Vg9)
, region B has Cg, d, which changes depending on the gate-source voltage Vg, and region C has Cgsp1+COsC05p2=
C (C0 is constant regardless of the gate-source voltage V)
Tona S Ru. Normally, the equivalent circuit of a circuit that handles microwaves is Cg between the gate and source, and Cgspl -1-Cgsp
20C, that is, the value of Cgsf-←Cgsd (Figure 1 (B
) gsd, − dotted chain line ■) is preferable, and one gate-drain space C0d is Cgdp1+C(]dp2, that is, the Cgsf value (surrounded by dashed lines ■ and ■ in Fig. 1 (8)). area).

Therefore, in the present invention, characteristic 1. Characteristics 1 after pinch-off using I. By finding the capacitance tC, df of the difference between II and subtracting the capacitance Cgdf from the characteristic before pinch-off (or II), we can find the exact gate-source distance C before pinch-off (JS=CQSf +Cgsd (Fig. 1) (B
) inside, − dot-dashed line ■). Note that the gate-drain capacitance is Cgdf.

In addition, if there is little variation in the characteristics of the same wafer, the first
As shown in Figure (A), one pair of FET pattern and one diode pattern may be provided on the same wafer, but if there are many variations, a plurality of such pairs may be provided on the same wafer.

〔Effect of the invention〕

As explained above, according to the present invention, two patterns are used: the first FET has a FET pattern in which the gate, source, and drain are separated, and the second FET has a diode pattern in which the source and train are short-circuited. Since the capacitance is measured using the conventional method, it is possible to obtain more accurate gate-source capacitance and drain capacitance than in the conventional example, and to obtain accurate equivalent circuit characteristics.

[Brief explanation of the drawing]

Fig. 1 is a pattern plan view of the present invention and a diagram explaining the capacitance measurement method; Fig. 2 is a schematic diagram of the measurement capacitance of conventional and inventive FET patterns; Fig. 3 is a diode pattern of the present invention. 4 is an equivalent circuit diagram of an FET, and FIG. 5 is a conventional capacitance measurement pattern. In the figure, 10 is a wafer, 11 is a diode pattern F'ET, and 12 is a FET. FE of the pattern, T. 13.15 is the source pad (source terminal), 13a, 1
4a is the arm pattern, 14.16 is the drain pad (drain terminal), 17 is the short circuit pattern, t, 8.19 is the gate pad (gate terminal), S is the source, D is the drain, G is the gate, C ( JSDl, Cgsp2 are gate-source capacitances, C
gc+pi, C1; 1dp2 indicates the capacitance between the gate 1 and the drain, and Cos 6 indicates the capacitance of the depletion layer under the gate. Patent applicant Fujitsu Co., Ltd. Agent Patent attorney Tadahiko Ito F.
In the 4th episode of Rei of ET, each figure is the 4th figure (wood capacity! 1) Konogu turn is the 5th figure

Claims (2)

[Claims] (1) FET (1) with separate gate terminal (18), source terminal (13), and drain terminal (14), respectively.
1), the same size as the FET (11), and the source terminal (15)
A capacitance measurement pattern in a semiconductor device, characterized in that a FET (12) whose drain terminal (16) is short-circuited is formed adjacently on the same wafer (10). (2) FET (1) with separate gate terminal (18), source terminal (13), and drain terminal (14), respectively.
1), the same size as the FET (11), and the source terminal (15)
Using a capacitance measurement pattern formed by forming adjacent FETs (12) whose drain terminals (16) are short-circuited on the same wafer (10), the gate and gate terminals of the FETs (11) before and after pinch-off are measured. Source-to-source voltage (V_
g_s) vs. gate-source capacitance characteristics (I), and
The gate-source voltage (V_g_s) before and after pinch-off in the above FET (12) vs. gate-source voltage (V_g_s)
Find the source-to-source capacitance characteristics (II), find the capacitance (C_g_d_f) of the difference between the above two gate-source capacitance characteristics (I) (II) after pinch-off, and calculate the gate-source capacitance characteristics (I) before pinch-off.
By subtracting the error capacitance (C_g_s_f) from II), the gate-source capacitance before pinch-off (
A method for measuring capacitance in a semiconductor device, characterized by determining C_g_s)(III).