JP3296315B2 - Method and apparatus for measuring overlap length and overlap capacity of MOSFET and recording medium - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overlap length and an overlap length that can accurately determine one of physically important device parameters when performing a circuit simulation of a MOSFET. The present invention relates to an overlap capacity measuring method, a measuring device, and a recording medium storing a program for causing a computer to execute the overlap length / overlap capacity measuring method.

[0002]

2. Description of the Related Art A conventional MOSFET overlap length measuring method (IEEE 1995 Int. Conference on Microelectro
nic Test Structures, vol8, March 1995 pp. 151-155)
Will be described with reference to FIGS. 27 and 28. As shown in FIG. 27, two types of devices having the same total gate area are prepared. FIG. 27A shows a MOSFET 50 having a plurality of gates 52a, 52b, 52c and a diffusion region 53 serving as a source or a drain formed on a P-type substrate 51, and FIG. The MOS capacitor 60 has a single gate 62 formed thereon. For these two types of devices, the gate-to-substrate capacitances Cgb and Cp of the above devices are measured by changing the gate voltage Vg applied between the gate and the substrate, that is, between the terminals 100-102 and the terminals 200-202. FIG. 28 shows the measurement results.

Next, the difference (= Cgb-Cp) between the gate-substrate capacitance Cgb of the MOSFET 50 and the gate-substrate capacitance Cp of the MOS capacitor 60 is taken, and a point Cdiff at which a peak appears in the characteristic curve (see FIG. 33). Ask for. Further, using the obtained Cdiff, M
Obtain the overlap length ΔL, which is the distance in the gate direction of the overlap region between the gate and the diffusion region in the OSFET 50.

ΔL = Cdiff · Lp / (Cp · Nf) (1)

Lp = Nf / L (2) where Lp is the gate length of the MOS capacitor 60 and Nf is M
The number L of gates of the OSFET 50 is L of one gate of the MOSFET 50.

[0004]

However, in the above-described conventional method for measuring the overlap length of a MOSFET, in the lithography step of forming a device, the total gate area of the gate patterns in the above two types of devices depends on the lithography conditions. They are not equal, causing an error. As a result, when no peak appears in the (Cgb-Cp) characteristic described above, there is a problem that the overlap length ΔL cannot be obtained. This is because the overlap capacitance is extracted from the difference between the shapes of the two types of devices described above, and the overlap length ΔL is calculated based on the overlap capacitance. This is because a peak may not appear in the (Cgb-Cp) characteristic.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has been developed in consideration of the above circumstances.
An object of the present invention is to provide a method and a device for measuring an overlap length and an overlap capacity of an FET and a recording medium storing a program for causing a computer to execute the overlap length and the overlap capacity measurement method.

[0006]

In order to achieve the above object, an overlap length of a MOSFET according to claim 1 is required.
The overlap capacitance measuring method includes applying a DC bias voltage Vg and an AC voltage between a gate and a source / drain for a plurality of MOSFETs having different gate lengths formed in a surface portion of a semiconductor substrate or a well in the surface portion,
The DC bias voltage Vg as a gate voltage is varied to measure the current flowing between the gate, source and drain, and a plurality of values indicating the relationship between the gate-source-drain capacitance Cgc and the gate voltage Vg based on the measurement result Cg of
a first process for obtaining a c-Vg characteristic;
The value Vx of the gate voltage Vg at which the dependency on the gate length Lg appears in the -Vg characteristic is obtained, and the Cgc-V
a second process of obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the g characteristic, and a gate voltage Vg at which the gate-source-drain capacitance Cgc is saturated in the plurality of Cgc-Vg characteristics. From the Cgc axis intercept of the Cgc-Lg characteristic obtained by the third process of obtaining and plotting the gate-source-drain capacitance Cgc with respect to each gate length Lg in the above. Fringe capacity Cf
And the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain based on the fringe capacitance Cf from the point where Cgc = Cx in the Cgc-Lg characteristic. And a fifth process for obtaining an overlap length ΔL and an overlap capacitance Cov formed between the gate and the diffusion region in the overlap region.

According to the first aspect of the present invention, the search for the value Cx of the gate-source-drain capacitance Cgc for obtaining the overlap length ΔL is performed by a plurality of Cgc-V
In g characteristics, gate-source-drain capacitance Cgc
Is determined from the branch point where the dependence on the gate length Lg appears, so that the overlap length ΔL can be accurately obtained even in a short-channel MOSFET. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

According to a second aspect of the present invention, there is provided a method of measuring an overlap length and an overlap capacitance of a MOSFET according to the first aspect of the present invention, wherein the second processing is performed instead of the second processing. In the plurality of Cgc-Vg characteristics, the difference between the gate-source-drain capacitances Cgc at any two gate lengths Lm and Ln (m ≠ n) is calculated, and the difference is a value of a certain ratio with respect to the maximum value. The gate voltage Vg of the plurality of Cgc-Vg characteristics, the gate voltage value Vx exhibiting a dependency on the gate length Lg, and the Cgc
From the -Vg characteristic, the gate-source at the gate voltage value Vx
There is provided a sixth processing for obtaining a value Cx of the capacitance Cgc between the drains.

According to a third aspect of the present invention, there is provided a method of measuring an overlap length and an overlap capacitance of a MOSFET according to the first aspect of the present invention, wherein the second processing is performed instead of the second processing. ∂Cgc / ∂Vg and gate voltage Vg obtained by differentiating gate-source-drain capacitance Cgc with gate voltage Vg in the plurality of Cgc-Vg characteristics obtained in the first processing.
A seventh process for obtaining a plurality of ∂Cgc / ∂Vg-Vg characteristics indicating the relationship between the plurality of ∂Cgc / ∂Vg-Vg.
A plurality of ΔCgc / ΔV is obtained by calculating a rising point of the characteristic.
The value of the gate voltage Vg at which the dependence on the gate length Lg appears in the g-Vg characteristic is Vx, and the Cgc-
An eighth process of obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Vg characteristic.

According to a fourth aspect of the present invention, there is provided a method of measuring an overlap length and an overlap capacitance of a MOSFET according to the first aspect of the present invention, wherein the second processing is performed instead of the second processing. The gate-source-drain capacitance Cgc of the Cgc-Vg characteristic obtained in the first process is differentiated by the gate voltage Vg, and the differentiated gate-source-drain capacitance Cg
c is further differentiated by the gate length Lg, ∂ / ∂Lg (∂Cg
c / ∂Vg) and the relationship between the gate voltage Vg and ∂ / ∂L
g (９Cgc / ∂Vg) -Vg characteristic, a ninth process, and a rising point of the ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic, and a gate length in the plurality of Cgc-Vg characteristics. The gate voltage V that shows a dependency on Lg
g as Vx, and the gate-source-drain capacitance Cg at the gate voltage Vx from the Cgc-Vg characteristic.
and a tenth process for calculating the value Cx of c.

According to a fifth aspect of the present invention, in the method for measuring the overlap length and the overlap capacitance of the MOSFET according to the first aspect, instead of the second processing,
The gate-source-drain capacitance Cgc of the Cgc-Vg characteristic obtained in the first processing is differentiated by the gate voltage Vg, and the differentiated gate-source-drain capacitance Cgc is further differentiated by the gate length Lg. ∂Lg (∂Cgc / ∂
Vg) and the gate voltage Vg, ∂ / ∂Lg (∂
A ninth process for obtaining the Cgc / 求 め る Vg) -Vg characteristic, a gate voltage value Vp at which a peak occurs in the ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic, and the ∂ / ∂Lg
(∂Cgc / ∂Vg) −The half-value width in the Vg characteristic is V
w, a constant k (1.0 <k <1.5), and Vx = Vp−k ·
The gate voltage value Vx obtained as Vw is calculated by the plurality of Cgc values.
An eleventh process of obtaining a gate voltage value Vx at which dependency on the gate length Lg appears in the -Vg characteristic, and obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Cgc-Vg characteristic. It is characterized by having.

According to the second to fifth aspects of the present invention, the search for the value Cx of the gate-source-drain capacitance Cgc for obtaining the overlap length ΔL is performed by a plurality of Cg.
Since the c-Vg characteristic is obtained from the branch point where the dependence of the gate-source-drain capacitance Cgc on the gate length Lg appears, the overlap length ΔL can be accurately obtained even in a short-channel MOSFET. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

According to a sixth aspect of the present invention, there is provided a method for measuring an overlap length of a MOSFET, wherein a CV characteristic indicating a relationship between a DC bias voltage Vg applied between a gate electrode of a MOS capacitance pattern and a substrate and a capacitance C is obtained. A first process of obtaining a flat band capacitance CFB per unit area of a gate electrode at a point where the DC bias voltage Vg becomes equal to the flat band voltage VFB from the CV characteristics, and a surface portion of the semiconductor substrate or the surface portion thereof. A DC bias voltage VSUB is applied to the substrate for a plurality of MOSFETs formed in the well of which the overlap length LSD and the gate width W are constant and the gate lengths Lg are different.
A second process in which a DC bias voltage Vg, a DC bias voltage VSUB, and an AC voltage are applied between the drains, and a gate-substrate capacitance CGSUB at Vg = VSUB + VFB is measured while changing the DC bias voltage VSUB. A third process for obtaining a built-in potential Vbi between the source and the drain, and a regression line obtained by plotting the gate-substrate capacitance CGSUB against √ (Vbi-VSUB);
Since the value of the intercept of the UB axis is CFB · (Lg−2LSD) · W, the overlap length LSD which is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain is obtained. 4 processing.

According to the sixth aspect of the present invention, since the DC bias voltage VSUB applied to the substrate is measured in a forward direction until the source / drain is forward-biased, the source is measured in the capacitance measurement.・ Drain
The effect of the depletion layer formed between the substrates can be suppressed,
The accuracy of evaluation of the PN junction position between the drain and the substrate can be improved.

Further, since the bias is set (Vg = VSUB + VFB) so that the energy band of the region for which the capacitance of the MOSFET is measured becomes flat, the depletion layer formed between the source / drain and the substrate becomes a PN junction. And the disturbance to the PN junction position determination is reduced. Therefore, the overlap length close to the metallurgical bonding position can be obtained.

According to a seventh aspect of the present invention, there is provided a method for measuring the overlap length of a MOSFET, wherein C- is a relation between a DC bias voltage Vg applied between the gate electrode of the MOS capacitor pattern on the diffusion layer and the diffusion layer and the capacitance C. Find the V characteristic,
A first process of obtaining a diffusion band flat band capacitance CFB ′ per unit area of the gate electrode at a point where the DC bias voltage Vg becomes equal to the flat band voltage VFB from the −V characteristic, and a surface portion of the semiconductor substrate or the surface thereof. A plurality of MOSs formed in the wells of which the overlap length LSD and the gate width W are constant and have different gate lengths Lg
For the FET, a DC bias voltage Vg and an AC voltage are applied between the gate and the source and the drain, and the DC bias voltage Vg as a gate voltage is changed to change the gate voltage.
A second process of measuring a current flowing between the source and the drain, and obtaining a plurality of Cgc-Vg characteristics indicating a relationship between a gate-source-drain capacitance Cgc and a gate voltage Vg based on the measurement result; The Cgc-Lg characteristic is obtained by obtaining and plotting the gate-source-drain capacitance Cgc with respect to each gate length Lg at the gate voltage Vg at which the gate-source-drain capacitance Cgc is saturated in the Cgc-Vg characteristic of FIG. Processing, a fourth processing for obtaining a gate fringe capacitance CFL on one side from an intercept of the Cgc axis of the Cgc-Lg characteristic,
Fifth process of measuring the gate-source-drain capacitance CGSD when the gate voltage Vg is Vg = 0 while changing the DC bias voltage VSUB applied to the substrate, and the built-in potential Vbi between the substrate, source and drain by simulation. And the gate-source-drain capacitance CGSD is set to √ (Vbi-VSUB)
CGSD- (Vbi-VSUB) characteristic is obtained, and the minimum value of the gate-source-drain capacitance CGSD in the CGSD-√ (Vbi-VSUB) characteristic is CFB ′ · LSD.
A seventh process for obtaining an overlap length LSD which is a length in a gate length direction in an overlap region between a gate and a diffusion region serving as a source or a drain because of W + 2CFL.

According to the seventh aspect of the present invention, the DC bias voltage VSUB applied to the substrate is measured in such a manner that it is driven in the forward direction up to the limit at which the MOSFET is turned on. -The effect of a depletion layer formed between the substrates can be suppressed, and the accuracy of evaluating the PN junction position between the source / drain and the substrate can be improved. Also, since the bias is set (Vg = 0 V) so that the energy band of the region where the capacitance of the MOSFET is measured becomes flat, the depletion layer formed between the source / drain and the substrate is parallel to the PN junction. And the disturbance to the PN junction position determination is reduced. Therefore, the overlap length close to the metallurgical bonding position can be obtained.

According to another aspect of the present invention, there is provided an apparatus for measuring an overlap length and an overlap capacity of a MOSFET, comprising:
A measuring means for applying a DC bias voltage Vg and an AC voltage between a source and a drain, changing the DC bias voltage Vg as a gate voltage to measure a current flowing between a gate, a source and a drain, and measuring the measuring means A first process of obtaining a plurality of Cgc-Vg characteristics indicating a relationship between a gate-source-drain capacitance Cgc and a gate voltage Vg based on the result; and a dependence of the plurality of Cgc-Vg characteristics on a gate length Lg. Appearing gate voltage V
g, and the gate-source-drain capacitance Cg at the gate voltage Vx from the Cgc-Vg characteristic.
a second process for calculating the value Cx of c, and the plurality of Cgc−
In the Vg characteristic, the gate-source-drain capacitance Cg
The third is to obtain the Cgc-Lg characteristic by obtaining and plotting the gate-source-drain capacitance Cgc with respect to each gate length Lg at the gate voltage Vg at which c is saturated.
, A fourth process for obtaining the fringe capacitance Cf from the Cgc axis intercept of the Cgc-Lg characteristic obtained by the third process, and The overlap length Δ which is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain.
L and a processing means for performing a fifth process for obtaining an overlap capacitance Cov formed between the gate and the diffusion region in the overlap region.

According to the eighth aspect of the present invention, the gate for obtaining the overlap length ΔL by the processing means is provided.
The search for the value Cx of the source-drain capacitance Cgc is
Since the dependence on the gate length Lg of the gate-source-drain capacitance Cgc in a plurality of Cgc-Vg characteristics is determined from a branch point, the short-channel MOS
Also in the FET, the overlap length ΔL can be accurately obtained. At the same time, the overlap capacity Cov
And fringe capacity can be determined.

In a ninth aspect of the present invention, the apparatus for measuring the overlap length and the overlap capacitance of the MOSFET according to the eighth aspect is the apparatus for measuring the overlap length and the overlap capacitance of the MOSFET according to the eighth aspect. In the above-mentioned plurality of Cgc-Vg characteristics, the difference between the gate-source-drain capacitances Cgc at any two gate lengths Lm and Ln (m ≠ n) is calculated. A value of the gate voltage Vg at a certain ratio is defined as a gate voltage value Vx at which the dependency on the gate length Lg appears in the plurality of Cgc-Vg characteristics, and the gate-source at the gate voltage value Vx is obtained from the Cgc-Vg characteristics. (6) The sixth process for obtaining the value Cx of the capacitance Cgc between drains is performed.

According to a tenth aspect of the present invention, in the apparatus for measuring the overlap length and the overlap capacitance of the MOSFET according to the eighth aspect, the processing means includes the second processing means. Is obtained by differentiating the gate-source-drain capacitance Cgc with the gate voltage Vg in the plurality of Cgc-Vg characteristics obtained in the first process.
g indicating the relationship between g and the gate voltage Vg.
A seventh process for obtaining a Vg-Vg characteristic;
The rising point of the gc / ∂Vg-Vg characteristic is obtained to determine the gate length Lg in the plurality of ∂Cgc / ∂Vg-Vg characteristics.
And the eighth process for obtaining the value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Cgc-Vg characteristic, wherein Vx is the value of the gate voltage Vg exhibiting the dependence on And

The apparatus for measuring the overlap length and the overlap capacitance of a MOSFET according to claim 11 is the apparatus for measuring the overlap length and the overlap capacitance of a MOSFET according to claim 8, wherein the processing means comprises: In place of the processing of Cgc-V obtained in the first processing.
The gate-source-drain capacitance Cgc of the g characteristic is differentiated by the gate voltage Vg, and the differentiated gate-source-drain capacitance Cgc is further differentiated by the gate length Lg.
A ninth process for obtaining a ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic indicating a relationship between / ∂Lg (∂Cgc / ∂Vg) and the gate voltage Vg, and the ∂ / ∂Lg (∂Cgc / ∂V
g) Finding the rising point of the -Vg characteristic
The value of the gate voltage Vg at which the dependence on the gate length Lg appears in the c-Vg characteristic is Vx, and the Cgc-
And a tenth process for obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Vg characteristic.

The apparatus for measuring the overlap length and the overlap capacitance of a MOSFET according to the twelfth aspect of the present invention is the apparatus for measuring the overlap length and the overlap capacitance of a MOSFET according to the eighth aspect of the present invention. In place of the processing of Cgc-V obtained in the first processing.
The gate-source-drain capacitance Cgc of the g characteristic is differentiated by the gate voltage Vg, and the differentiated gate-source-drain capacitance Cgc is further differentiated by the gate length Lg.
A ninth process for obtaining a ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic indicating a relationship between / ∂Lg (∂Cgc / ∂Vg) and the gate voltage Vg, and the ∂ / ∂Lg (∂Cgc / ∂V
g) The value of the gate voltage Vp at which a peak occurs in the -Vg characteristic, the half-value width in the ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic is Vw, and the constant is k (1.0 <k <1.5), Vx = Gate voltage value V obtained as Vp-kVw
x is the gate length Lg in the plurality of Cgc-Vg characteristics.
And the gate voltage at the gate voltage Vx from the Cgc-Vg characteristic.
Eleventh calculation of the value Cx of the source-drain capacitance Cgc
And the above-mentioned processing is performed.

According to the ninth to twelfth aspects of the invention,
The processing means searches for the value Cx of the gate-source-drain capacitance Cgc for obtaining the overlap length ΔL, and finds the dependence of the gate-source-drain capacitance Cgc on the gate length Lg in a plurality of Cgc-Vg characteristics. Is obtained from the branch point where appears, so that even in the short-channel MOSFET, the overlap length Δ
L can be obtained. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

According to a thirteenth aspect of the present invention, there is provided an apparatus for measuring an overlap length of a MOSFET, comprising:
When measuring the V characteristic, an AC voltage and a DC bias voltage Vg are applied between the gate electrode of the MOS capacitance pattern and the substrate, and the current flowing between the gate electrode and the substrate of the MOS capacitance pattern and the voltage between the gate electrode and the substrate are changed. A voltage applied between the plurality of MOs having different gate lengths Lg formed in a surface portion of the semiconductor substrate or a well in the surface portion is measured.
When measuring the gate-substrate capacitance CGSUB for the SFET, a DC bias voltage VSUB is applied to the substrate, and a DC bias voltage Vg is applied between the gate, source and drain.
A DC bias voltage VSUB and an AC voltage are applied, and the DC bias voltage VSUB is changed to
Measuring means for measuring a current flowing between the gate and the substrate of the OSFET;
A CV characteristic indicating a relationship between the DC bias voltage Vg applied between the gate electrode of the OS capacitance pattern and the substrate and the capacitance C is obtained. From the CV characteristic, the DC bias voltage Vg is equal to the flat band voltage VFB. The first processing for obtaining the flat band capacitance CFB per unit area of the gate electrode at a certain point, and the overlap length LSD and the gate width formed in the surface portion of the semiconductor substrate or in the well of the surface portion are constant. And a plurality of Ms having different gate lengths Lg
The DC bias voltage VSUB is applied to the substrate of the OSFET, and the DC bias voltage Vg, the DC bias voltage VSUB, and the AC voltage are applied between the gate, source, and drain, and the DC bias voltage VSUB is changed. Gate-substrate capacitance CGSUB based on the current flowing between the gate and substrate at Vg = VSUB + VFB
The second processing for obtaining
A third process for determining the built-in potential Vbi between the source and the drain, and the gate-substrate capacitance CGSUB
(Vbi−VSUB) is plotted to obtain a regression line, and the intercept value of the CGSUB axis in the regression line is CFB ·
Because of (Lg−2LSD) · W, the overlap length LSD is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain.
And a processing means for performing a fourth process for obtaining

According to the thirteenth aspect of the present invention, the DC bias voltage VSUB applied to the substrate is measured by the measuring means and the processing means in such a manner that the DC bias voltage VSUB is driven in the forward direction until the source / drain is forward biased. Since the overlap length is obtained by performing the processing, the influence of the depletion layer formed between the source / drain and the substrate in the capacitance measurement can be suppressed, and the evaluation accuracy of the PN junction position between the source / drain and the substrate can be improved. Can be achieved.

Also, since the bias is set (Vg = VSUB + VFB) so that the energy band of the region where the capacitance of the MOSFET is measured becomes flat, the depletion layer formed between the source / drain and the substrate is a PN junction. And the disturbance to the PN junction position determination is reduced. Therefore, the overlap length close to the metallurgical bonding position can be obtained.

According to a fourteenth aspect of the present invention, there is provided an apparatus for measuring the overlap length of a MOSFET, comprising:
When measuring the V characteristic, an AC voltage and a DC bias voltage Vg are applied between the gate electrode of the MOS capacitance pattern on the diffusion layer and the diffusion layer, and the current flowing between the gate electrode of the MOS capacitance pattern and the diffusion layer and the gate electrode The voltage applied between the gate electrode and the diffusion layer is measured, and the gate-source-drain capacitance Cgc is measured for a plurality of MOSFETs having different gate lengths Lg formed in the surface portion of the semiconductor substrate or in the wells of the surface portion. In this case, a DC bias voltage Vg and an AC voltage are applied between the gate and the source / drain, and the DC bias voltage Vg as a gate voltage is applied.
Alternatively, a measuring means for measuring a current flowing between the gate-source / drain by changing the DC bias voltage VSUB applied to the substrate, and based on a measurement result of the measuring means,
C indicating the relationship between the DC bias voltage Vg applied between the gate electrode of the MOS capacitance pattern and the diffusion layer and the capacitance C
A first process of determining a −V characteristic, and determining a flat band capacitance CFB ′ per unit area of the gate electrode at a point where the DC bias voltage Vg becomes equal to the flat band voltage VFB from the CV characteristic; The overlap length LSD and the gate width W formed in the surface portion of the semiconductor substrate or in the well of the surface portion are constant and the gate length Lg
Are applied with a DC bias voltage Vg and an AC voltage between the gate and the source / drain, and the DC bias voltage V
A plurality of Cgc-Vg characteristics indicating the relationship between the gate-source-drain capacitance Cgc and the gate voltage Vg based on the current flowing between the gate-source-drain measured by the measuring means when g is changed. The second processing to be obtained and the plotting of the gate-source-drain capacitance Cgc with respect to each gate length Lg at the gate voltage Vg at which the gate-source-drain capacitance Cgc is saturated in the plurality of Cgc-Vg characteristics. Cgc
A third process for obtaining the Lg characteristic; and a gate fringe capacitance CFL on one side of the intercept of the Cgc axis of the Cgc-Lg characteristic.
And the gate voltage V while changing the DC bias voltage V SUB applied to the MOSFET substrate.
a fifth process for measuring the gate-source-drain capacitance CGSD when g is Vg = 0, a sixth process for obtaining a built-in potential Vbi between the substrate-source-drain by simulation, and a process for measuring the gate-source-drain The capacitance CGSD is plotted against √ (Vbi−VSUB) to obtain the CGSD−√ (Vbi−VSUB) characteristic, and the CGSD−
最小 Since the minimum value of the gate-source-drain capacitance CGSD in the (Vbi-VSUB) characteristic is CFB ′ · LSD · W + 2CFL, the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain And processing means for performing a seventh process for obtaining the overlap length LSD.

According to the fourteenth aspect of the present invention, the DC bias voltage VSUB applied to the substrate is measured by the measuring means and the processing means in such a manner that the DC bias voltage VSUB is driven in the forward direction until the MOSFET is turned on, and data processing is performed. In this way, the overlap length is determined, so that the influence of the depletion layer formed between the source, drain and substrate in the capacitance measurement can be suppressed, and the accuracy of the evaluation of the PN junction position between the source, drain and substrate can be improved. I can do it.

Further, since the bias is set (Vg = 0 V) so that the energy band of the region where the capacitance of the MOSFET is to be measured is flat, the depletion layer formed between the source / drain and the substrate has a PN junction. And the disturbance to the PN junction position determination is reduced. Therefore, the overlap length close to the metallurgical bonding position can be obtained.

According to the recording medium of the present invention, a DC bias voltage Vg is applied between a gate, a source and a drain for a plurality of MOSFETs having different gate lengths formed in a surface portion of a semiconductor substrate or in a well of the surface portion. And applying an AC voltage, changing the DC bias voltage Vg as a gate voltage to measure a current flowing between the gate, the source and the drain, and based on the measurement result, a gate-source-drain capacitance Cgc and a gate voltage. A first process of obtaining a plurality of Cgc-Vg characteristics indicating a relationship with Vg, obtaining a value Vx of a gate voltage Vg in which dependency on a gate length Lg appears in the plurality of Cgc-Vg characteristics, and obtaining the Cgc-Vg A second method of obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the characteristic.
And the gate-source-to-gate length Lg at the gate voltage Vg at which the gate-source-drain capacitance Cgc is saturated in the plurality of Cgc-Vg characteristics.
A third process of obtaining the Cgc-Lg characteristic by obtaining and plotting the drain-to-drain capacitance Cgc, and a fourth process of obtaining the fringe capacitance Cf from the Cgc axis intercept of the Cgc-Lg characteristic obtained by the third process. , The Cgc-L
From the point where Cgc = Cx in the g characteristic, based on the fringe capacitance Cf, the overlap length ΔL which is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain, and the gate in the overlap region And a fifth process for obtaining an overlap capacitance Cov formed between the diffusion region and the diffusion region. A program for causing a computer to execute a method for measuring an overlap length and an overlap capacitance of a MOSFET, comprising: The gist is a recording medium that can be read by a computer in which the recording is performed.

According to the fifteenth aspect of the present invention, a plurality of MOSFETs having different gate lengths formed in the surface portion of the semiconductor substrate or in the wells of the surface portion are provided with gates.
A DC bias voltage Vg and an AC voltage are applied between the source and the drain, the DC bias voltage Vg as a gate voltage is changed, and a current flowing between the gate and the source and the drain is measured. A first process of obtaining a plurality of Cgc-Vg characteristics indicating a relationship between a source-drain capacitance Cgc and a gate voltage Vg, and a value of a gate voltage Vg in which the plurality of Cgc-Vg characteristics has dependency on a gate length Lg Vx is determined, and the gate voltage at the gate voltage value Vx is obtained from the Cgc-Vg characteristic.
A second process for obtaining a value Cx of the source-drain capacitance Cgc;
Gate voltage V at which the source-drain capacitance Cgc is saturated
g is obtained by plotting the gate-source-drain capacitance Cgc with respect to each gate length Lg at g.
a third process for obtaining the gc-Lg characteristic, a fourth process for obtaining the fringe capacitance Cf from the Cgc axis intercept of the Cgc-Lg characteristic obtained by the third process, and the Cgc-Lg
From the point where Cgc = Cx in the characteristics, the fringe capacitance C
The overlap length ΔL, which is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as a source or a drain, based on f, and the overlap formed between the gate and the diffusion region in the overlap region. And a fifth process for obtaining the lap capacitance Cov, wherein a program for causing the computer to execute the method for measuring the overlap length and the overlap capacitance of the MOSFET is recorded on a computer-readable recording medium. Therefore, by causing the computer system to read and execute this program, the overlap length ΔL can be accurately obtained even in the short-channel MOSFET. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

In the recording medium according to the present invention, instead of the second processing, the gate-source / gate-source / gate-length (Lm) at any two gate lengths Lm and Ln (m に お い て n) in the plurality of Cgc-Vg characteristics may be used. The difference between the drain-to-drain capacitances Cgc is taken, and the value of the gate voltage Vg at a value where the difference is a certain ratio with respect to the maximum value is defined as the gate voltage value Vx in which the dependence on the gate length Lg appears in the plurality of Cgc-Vg characteristics. And a sixth process for obtaining a value Cx of a gate-source-drain capacitance Cgc at a gate voltage value Vx from the Cgc-Vg characteristic. A computer-readable recording medium having recorded thereon a program for causing a computer to execute the overlap capacity measuring method.

According to the sixteenth aspect of the present invention, instead of the second processing, in the plurality of Cgc-Vg characteristics, the gate-source circuit at any two gate lengths Lm and Ln (m ≠ n) is used. The difference between the drain-to-drain capacities Cgc is taken, and the value of the gate voltage Vg at a certain ratio of the difference to the maximum value is defined as the gate voltage value Vx in which the dependence on the gate length Lg appears in the plurality of Cgc-Vg characteristics. And a sixth process for obtaining a value Cx of a gate-source-drain capacitance Cgc at a gate voltage value Vx from the Cgc-Vg characteristic. A program for causing a computer to execute the overlap capacity measuring method is recorded on a computer-readable recording medium. , To read the program in the computer system, by executing, even in short-channel MOSFET, can be obtained accurately overlap length [Delta] L. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

A recording medium according to claim 17, wherein instead of the second processing, the gate-source-drain capacitance Cgc is changed by the gate voltage Vg in the plurality of Cgc-Vg characteristics obtained in the first processing. ∂Cgc / ∂V differentiated by
g indicating the relationship between g and the gate voltage Vg.
A seventh process for obtaining a Vg-Vg characteristic;
The rising point of the gc / ∂Vg-Vg characteristic is obtained to determine the gate length Lg in the plurality of ∂Cgc / ∂Vg-Vg characteristics.
An eighth process for determining the value of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Cgc-Vg characteristic by setting the value of the gate voltage Vg at which the dependence on the voltage appears to Vx. The gist of the present invention is a computer-readable recording medium storing a program for causing a computer to execute the method for measuring the overlap length and the overlap capacitance of a MOSFET according to claim 1.

According to the seventeenth aspect, in place of the second processing, the plurality of Cs obtained in the first processing are obtained.
∂Cgc / ∂Vg obtained by differentiating the gate-source-drain capacitance Cgc with the gate voltage Vg in the gc-Vg characteristic.
∂Cgc / ∂V indicating the relationship between と Cgc / ∂V
a seventh process for obtaining a g-Vg characteristic;
The rising point of the c / ｇVg-Vg characteristic is obtained, and the value of the gate voltage Vg in which the dependency on the gate length Lg appears in the plurality of ∂Cgc / ∂Vg-Vg characteristics is Vx,
An eighth process for obtaining a value Cx of a gate-source-drain capacitance Cgc at a gate voltage value Vx from the Cgc-Vg characteristic. Since the program for causing the computer to execute the overlap capacitance measuring method is recorded on a computer-readable recording medium, the computer system can read and execute the program so that even a short-channel MOSFET can accurately perform the method. Overlap length Δ
L can be obtained. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

The recording medium according to claim 18, wherein the Cgc-V obtained in the first processing is used instead of the second processing.
The gate-source-drain capacitance Cgc of the g characteristic is differentiated by the gate voltage Vg, and the differentiated gate-source-drain capacitance Cgc is further differentiated by the gate length Lg.
A ninth process for obtaining a ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic indicating a relationship between / ∂Lg (∂Cgc / ∂Vg) and the gate voltage Vg, and the ∂ / ∂Lg (∂Cgc / ∂V
g) Finding the rising point of the -Vg characteristic
The value of the gate voltage Vg at which the dependence on the gate length Lg appears in the c-Vg characteristic is Vx, and the Cgc-
A tenth process for obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Vg characteristic;
2. The MOSF according to claim 1, wherein
The present invention provides a computer-readable recording medium storing a program for causing a computer to execute the ET overlap length / overlap capacity measurement method.

According to the eighteenth aspect of the invention, instead of the second processing, the Cgc-Vg obtained in the first processing is used.
The gate-source-drain capacitance Cgc of the characteristic is differentiated by the gate voltage Vg, and the differentiated gate-source-drain capacitance Cgc is further differentiated by the gate length Lg.
A ninth process for obtaining a ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic indicating a relationship between ∂Lg (∂Cgc / ∂Vg) and the gate voltage Vg, and the ∂ / ∂Lg (∂Cgc / ∂) V
g) Finding the rising point of the -Vg characteristic
The value of the gate voltage Vg at which the dependence on the gate length Lg appears in the c-Vg characteristic is Vx, and the Cgc-
A tenth process for obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Vg characteristic;
2. The MOSF according to claim 1, wherein
Since a program for causing a computer to execute the ET overlap length / overlap capacity measurement method is recorded on a computer-readable recording medium, the computer system reads the program and executes the program, thereby shortening the program. Channel MOSF
Also in the ET, the overlap length ΔL can be accurately obtained. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

The recording medium according to claim 19, wherein the Cgc-V obtained in the first processing is used instead of the second processing.
The gate-source-drain capacitance Cgc of the g characteristic is differentiated by the gate voltage Vg, and the differentiated gate-source-drain capacitance Cgc is further differentiated by the gate length Lg.
A ninth process for obtaining a ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic indicating a relationship between / ∂Lg (∂Cgc / ∂Vg) and the gate voltage Vg, and the ∂ / ∂Lg (∂Cgc / ∂V
g) The value of the gate voltage Vp at which a peak occurs in the -Vg characteristic, the half-value width in the ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic is Vw, and the constant is k (1.0 <k <1.5), Vx = Gate voltage value V obtained as Vp-kVw
x is the gate length Lg in the plurality of Cgc-Vg characteristics.
And the gate voltage at the gate voltage Vx from the Cgc-Vg characteristic.
Eleventh calculation of the value Cx of the source-drain capacitance Cgc
2. The processing according to claim 1, further comprising:
A gist of the present invention is a computer-readable recording medium that stores a program for causing a computer to execute the OSFET overlap length / overlap capacitance measurement method.

According to the nineteenth aspect, instead of the second processing, the Cgc-Vg obtained in the first processing is used.
The gate-source-drain capacitance Cgc of the characteristic is differentiated by the gate voltage Vg, and the differentiated gate-source-drain capacitance Cgc is further differentiated by the gate length Lg.
A ninth process for obtaining a ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic indicating a relationship between ∂Lg (∂Cgc / ∂Vg) and the gate voltage Vg, and the ∂ / ∂Lg (∂Cgc / ∂) V
g) The value of the gate voltage Vp at which a peak occurs in the -Vg characteristic, the half-value width in the ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic is Vw, and the constant is k (1.0 <k <1.5), Vx = Gate voltage value V obtained as Vp-kVw
x is the gate length Lg in the plurality of Cgc-Vg characteristics.
And the gate voltage at the gate voltage Vx from the Cgc-Vg characteristic.
Eleventh calculation of the value Cx of the source-drain capacitance Cgc
2. The processing according to claim 1, further comprising:
A program for causing a computer to execute the method of measuring the overlap length and the overlap capacitance of the OSFET is recorded on a computer-readable recording medium. Channel M
Also in the OSFET, the overlap length ΔL can be accurately obtained. At the same time, the overlap capacity C
ov and fringe volume can be determined.

The recording medium according to the twentieth aspect is characterized in that
A CV characteristic indicating a relationship between the DC bias voltage Vg applied between the gate electrode of the S capacitance pattern and the substrate and the capacitance C is obtained. From the CV characteristic, the DC bias voltage Vg is equal to the flat band voltage VFB. The first processing for obtaining the flat band capacitance CFB per unit area of the gate electrode at a certain point, and the overlap length LSD and the gate width W formed in the surface portion of the semiconductor substrate or in the well of the surface portion are constant. And a plurality of MOSs having different gate lengths Lg
For the FET, a DC bias voltage VSUB is applied to the substrate, and a DC bias voltage Vg, a DC bias voltage VSUB, and an AC voltage are applied between the gate and the source / drain. -Capacity between substrates CGSUB
, A third process for obtaining a built-in potential Vbi between the substrate, the source and the drain by simulation, and regression by plotting the gate-substrate capacitance CGSUB against √ (Vbi-VSUB). A straight line is obtained, and the intercept value of the CGSUB axis in the regression line is CFB ·
Because of (Lg−2LSD) · W, the overlap length LSD is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain.
And a fourth process for obtaining
A gist is a computer-readable recording medium that stores a program for causing a computer to execute the OSFET overlap length measurement method.

According to the twentieth aspect of the present invention, the MOS
A CV characteristic indicating a relationship between the capacitance C and a DC bias voltage Vg applied between the gate electrode of the capacitance pattern and the substrate is obtained, and the DC bias voltage Vg becomes equal to the flat band voltage VFB based on the CV characteristic. In the first process for obtaining the flat band capacitance CFB per unit area of the gate electrode at a point, the overlap length LSD and the gate width W formed in the surface portion of the semiconductor substrate or in the well of the surface portion are constant. MOSFs having different gate lengths Lg
Applying a DC bias voltage VSUB to the substrate for ET,
And a DC bias voltage V between the gate and the source / drain.
g, while applying the DC bias voltage VSUB and the AC voltage, and changing the DC bias voltage VSUB, Vg
= V SUB + V FB, a second process for measuring the gate-substrate capacitance CGSUB, a third process for obtaining a built-in potential Vbi between the substrate, source and drain by simulation, and the gate-substrate capacitance CGSUB
(Vbi−VSUB) is plotted to obtain a regression line, and the intercept value of the CGSUB axis in the regression line is CFB ·
Because of (Lg−2LSD) · W, the overlap length LSD is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain.
And a fourth process for determining
Since the program for causing the computer to execute the FET overlap length measuring method is recorded on a computer-readable recording medium, the computer system reads and executes the program, so that the direct current applied to the substrate is reduced. Bias voltage VSUB
Can be measured in the forward direction to the limit where the source / drain is forward biased, and data processing can be performed. As a result, the influence of the depletion layer formed between the source / drain and the substrate in the capacitance measurement can be suppressed. As a result, the evaluation accuracy of the PN junction position between the source / drain and the substrate can be improved.

Further, since the bias is set (Vg = VSUB + VFB) so that the energy band of the region for which the capacitance of the MOSFET is measured becomes flat, the depletion layer formed between the source / drain and the substrate becomes a PN junction. And the disturbance to the PN junction position determination is reduced. Therefore, the overlap length close to the metallurgical bonding position can be obtained.

Further, in the recording medium according to the present invention, CV characteristics indicating a relationship between a DC bias voltage Vg applied between the gate electrode of the MOS capacitance pattern on the diffusion layer and the diffusion layer and the capacitance C are obtained. A first process for obtaining a flat band capacitance C FB ′ per unit area of the gate electrode at a point where the DC bias voltage Vg becomes equal to the flat band voltage V FB from the CV characteristics; The overlap length LSD and the gate width W formed in the surface well are constant and the gate length L
For a plurality of MOSFETs having different g, a DC bias voltage Vg and an AC voltage are applied between the gate and the source / drain, and the DC bias voltage Vg as a gate voltage is applied.
g, the current flowing between the gate, source and drain is measured, and a plurality of Cgc-Vg characteristics indicating the relationship between the gate-source-drain capacitance Cgc and the gate voltage Vg are obtained based on the measurement result. 2 and the gate-source-drain capacitance Cg for each gate length Lg at the gate voltage Vg at which the gate-source-drain capacitance Cgc is saturated in the plurality of Cgc-Vg characteristics.
a third process of obtaining the Cgc-Lg characteristic by obtaining and plotting c; and a fourth process of obtaining the gate fringe capacitance CFL on one side from the intercept of the Cgc axis of the Cgc-Lg characteristic.
And changing the gate voltage Vg to Vg = 0 while changing the DC bias voltage VSUB applied to the MOSFET substrate.
A fifth process of measuring the gate-source-drain capacitance CGSD in the above, a sixth process of obtaining a built-in potential Vbi between the substrate-source-drain by simulation, and a process of measuring the gate-source-drain capacitance C
GSD is plotted against √ (Vbi−VSUB) and CGSD−
特性 (Vbi-VSUB) characteristic is obtained, and the CGSD-√ (Vbi-VSUB)
SUB) Characteristics in gate-source-drain capacitance CG
Since the minimum value of SD is CFB ′ · LSD · W + 2CFL, the seventh process of obtaining the overlap length LSD which is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain is described. A gist of the present invention is a computer-readable recording medium storing a program for causing a computer to execute a method of measuring an overlap length of a MOSFET, the method comprising:

According to the twenty-first aspect of the present invention, C representing the relationship between the DC bias voltage Vg applied between the gate electrode of the MOS capacitance pattern on the diffusion layer and the diffusion layer and the capacitance C.
A first process of obtaining a −V characteristic, and a diffusion band flat band capacitance CFB ′ per unit area of the gate electrode at a point where the DC bias voltage Vg becomes equal to the flat band voltage VFB from the CV characteristic; The overlap length LSD and the gate width W formed in the surface portion of the semiconductor substrate or in the well of the surface portion are constant and the gate length Lg
DC bias voltage Vg and AC voltage are applied between the gate, source and drain of the plurality of MOSFETs having different
Is changed to measure the current flowing between the gate-source / drain, and based on the measurement result, a plurality of Cgc-Vg characteristics indicating the relationship between the gate-source-drain capacitance Cgc and the gate voltage Vg are obtained. And the gate-source-drain capacitance Cgc for each gate length Lg at the gate voltage Vg at which the gate-source-drain capacitance Cgc is saturated in the plurality of Cgc-Vg characteristics.
, And a third process for obtaining the Cgc-Lg characteristic by plotting, and a fourth process for obtaining the gate fringe capacitance CFL on one side of the intercept of the Cgc axis of the Cgc-Lg characteristic. Fifth process for measuring the gate-source-drain capacitance CGSD when the gate voltage Vg is Vg = 0 while changing the DC bias voltage VSUB, and sixth process for obtaining a built-in potential Vbi between the substrate, source and drain by simulation. Processing and the gate-source-drain capacitance CGS
D is plotted against √ (Vbi-VSUB) and CGSD-√
(Vbi−VSUB) characteristic is obtained, and the CGSD−√ (Vbi−VSU) is obtained.
B) Gate-source-drain capacitance CGSD in characteristics
Since the minimum value is CFB ′ · LSD · W + 2CFL, a seventh process for obtaining an overlap length LSD which is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain is provided. Since the program for causing the computer to execute the method of measuring the overlap length of the MOSFET is recorded on a computer-readable recording medium, the program is read and executed by a computer system. The DC bias voltage VSUB applied to the substrate can be measured and processed in a forward direction until the MOSFET is turned on to the limit at which the MOSFET is turned on, and as a result, the DC bias voltage VSUB is formed between the source / drain and the substrate in the capacitance measurement. The effect of the depletion layer can be suppressed, and between the source / drain and the substrate It can be improved evaluation accuracy of definitive PN junction position.

Further, since the bias is set (Vg = 0 V) so that the energy band of the region where the capacitance of the MOSFET is to be measured is flat, the depletion layer formed between the source / drain and the substrate has a PN junction. And the disturbance to the PN junction position determination is reduced. Therefore, the overlap length close to the metallurgical bonding position can be obtained.

[0047]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows the electrical configuration of the apparatus for measuring the overlap length and overlap capacitance of the MOSFET according to the first embodiment of the present invention, and FIG. 2 shows the electrical configuration of the electrical measurement apparatus in FIG. In FIG.
The overlap length / overlap capacitance measuring device is an electric measuring device 2 that performs electric measurement necessary for calculating the gate-source-drain capacitance Cgc for the device group 1 to be measured.
And an input device 3 such as a keyboard and a mouse, a recording medium 4 on which various processing programs are recorded, and a data processing device 5 operated by the various programs recorded on the recording medium 4
And a storage device 6 for temporarily storing measurement data and calculation data, and an output device 7 such as a display device or a printer.

As shown in FIG. 2, the electric measuring device 2 includes an element mounting portion 21 for mounting the device group 1 to be measured, and a gate for each device to be measured in the device group 1 under the control of the data processing device 5. A measuring unit 22 for measuring a current and a voltage between the source and the drain.

The element mounting portion 21 has a gate 1g, a source 1
s, a drain 1d, and a mounting terminal electrically connected to each of the semiconductor substrate 1b. The measuring unit 22
Is a variable DC bias voltage source 221 for applying a DC bias voltage to the gate 1g, an AC voltage source 222 connected in series to the variable DC bias voltage source 221, and an application between the gate 1g, the source 1s, and the drain 1d. A voltmeter 223 for measuring a voltage and an ammeter 224 for measuring a current flowing between the gate 1g and the source 1s / drain 1d.
And

The variable DC bias voltage source 221 and the AC voltage source 222 are connected in series, and one end of the variable DC voltage source 221 is grounded. The AC voltage source 222 is
Is connected to the gate mounting terminal of Also, element mounting part 2
One gate mounting terminal is grounded via a voltmeter 223 and an ammeter 224. Further, the source mounting terminal and the drain mounting terminal of the element mounting portion 21 are commonly connected, and the ammeter 2
24 are grounded together. The board mounting terminal of the element mounting portion 21 is grounded. As described above, each measurement target element is electrically connected to the measurement section 22 via the element mounting section 21.

Next, the operation of the data processing device 5 will be described with reference to the flowchart of FIG. First, gate lengths Lg manufactured by the same process differ (Lg = L1, L2, Lg).
3), a plurality of MOSFETs (in this embodiment, NMOS
A device group 1 to be measured composed of a transistor) is prepared, and the device group 1 is previously mounted on the device mounting portion 21 of the electric measuring device. As shown in FIG. 2, this mounting is performed by the gate 1g, the source 1s, the drain 1d,
This is performed by connecting the semiconductor substrate 1b to a corresponding mounting terminal of the element mounting portion 21.

In step 300, a DC bias voltage Vg is applied between the gate, the source, and the drain by the variable DC voltage source 221 and an AC voltage is applied by the AC voltage source 222.
By changing the DC bias voltage Vg as a gate voltage, a current and a voltage flowing between the gate, source, and drain are measured by an ammeter 224 and a voltmeter 223, and based on the measurement result, a capacitance Cgc between the gate, source, and drain is determined. And a plurality of Cgc-Vg characteristics indicating the relationship between the gate voltage and the gate voltage Vg. FIG. 4 shows the obtained Cgc-Vg characteristics.
FIG. 7 shows an actual measurement example of the Cgc-Vg characteristic. In the figure, curves P1, P2, P3, and P4 indicate that the gate lengths Lg are 1.0 μm, 0.5 μm, 0.36 μm, 0.
MOSFET with 24 μm and gate width W of 1.0 mm
Shows the Cgc-Vg characteristics.

Next, the gate voltage Vg in which the dependence on the gate length Lg appears in the plurality of Cgc-Vg characteristics.
Is obtained (step 302). Where multiple C
The following two methods are available for obtaining the gate voltage value Vx in which the dependence on the gate length Lg appears in the gc-Vg characteristic. First, in the first method, a difference between the gate-source-drain capacitances Cgc at arbitrary two gate lengths Lm and Ln (m ≠ n) in a plurality of Cgc-Vg characteristics is calculated, and the difference is determined with respect to the maximum value. The value of the gate voltage Vg at a certain ratio value is defined as the gate voltage value Vx in which the dependency on the gate length Lg appears in the plurality of Cgc-Vg characteristics. FIG. 8 shows an actual measurement example in which the difference between the Cgc-Vg characteristics is obtained. In the figure, a curve P10 indicates MOSFETs having gate lengths Lg of 1.0 μm and 0.5 μm, respectively.
The curve P11 shows the difference characteristics of the Cgc-Vg characteristics of the MOS transistors having the gate lengths Lg of 0.5 μm and 0.36 μm, respectively.
The curve P12 shows the difference characteristic of the Cgc-Vg characteristic of the MOSFET having the gate lengths Lg of 0.36 μm and 0.24 μm, respectively.

A second method for obtaining the gate voltage value Vx is that a gate-source voltage is obtained in a plurality of Cgc-Vg characteristics.
ΔC obtained by differentiating the drain-to-drain capacitance Cgc with the gate voltage Vg
gc / ∂Vg and a plurality of 示 す indicating the relationship between the gate voltage Vg.
Cgc / ΔVg−Vg characteristics are obtained, and the plurality of ΔCgc /
The rising point of the Vg-Vg characteristic is obtained to obtain the plurality of
The value of the gate voltage Vg at which the dependence on the gate length Lg appears in the Cgc / ∂Vg-Vg characteristic is defined as Vx. ΔCg obtained from the Cgc-Vg characteristic shown in FIG.
FIG. 5 shows the c / ΔVg-Vg characteristics. ∂Cgc / ∂Vg
FIG. 9 shows an actual measurement example of the -Vg characteristic. In FIG.
1, Q2, Q3, and Q4 each have a gate length Lg of 1..
ΔCgc / of MOSFETs with 0 μm, 0.5 μm, 0.36 μm, 0.24 μm and gate width W of 1.0 mm
From the figure showing the ∂Vg-Vg characteristic, the gate voltage value V
It turns out that x is -0.4V.

The value Vx of the gate voltage Vg at which the dependence on the gate length Lg appears in a plurality of Cgc-Vg characteristics is obtained by one of the above two methods.
A value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx is obtained from the c-Vg characteristic (step 3).
04).

In step 306, the plurality of Cgc-
In the Vg characteristic, the gate-source-drain capacitance Cg
The Cgc-Lg characteristic shown in FIG. 6 is obtained by obtaining and plotting the gate-source-drain capacitance Cgc with respect to each gate length Lg at the gate voltage Vg at which c is saturated.

Next, Cgc-Lg obtained in step 306
The fringe capacitance Cf is determined from the Cgc axis intercept of the characteristic (step 308), and in step 310, from the point where Cgc = Cx in the Cgc-Lg characteristic, the diffusion between the gate and the diffusion region serving as the source or drain is determined based on the fringe capacitance Cf. An overlap length ΔL, which is a length in the gate length direction in the overlap region, and an overlap capacitance Cov formed between the gate and the diffusion region in the overlap region are obtained. FIG. 10 shows an actual measurement example of the Cgc-Lg characteristic. The figure shows that the gate voltage Vg is 2.0 V
, The fringe capacitance Cf is 0.08 pF, the overlap capacitance Cov is 0.13 pF, and the overlap length ΔL is 56 nm.

According to the present embodiment, the search for the value Cx of the gate-source-drain capacitance Cgc for obtaining the overlap length ΔL is performed in a plurality of Cgc-Vg characteristics. Is determined from the branch point where the dependence on the gate length Lg appears, so that the overlap length ΔL can be accurately obtained even in a short-channel MOSFET. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

Next, the MO according to the second embodiment of the present invention will be described.
An SFET overlap length / overlap capacitance measuring device will be described. MOSFE according to the present embodiment
The device configuration of the T overlap length / overlap capacitance measuring device is the same as the MOSFET overlap length / overlap capacitance measuring device according to the first embodiment shown in FIGS. Since the operation is the same except for the operation, the operation will be described with reference to FIGS.

The operation of the data processing device 5 according to the embodiment of the present invention will be described with reference to the flowchart of FIG. As in the first embodiment, first, gate lengths Lg manufactured by the same process are different (Lg = L1, L2, Lg).
3), a plurality of MOSFETs (in this embodiment, NMOS
A device group 1 to be measured composed of a transistor) is prepared, and the device group 1 is previously mounted on the device mounting portion 21 of the electric measuring device. As shown in FIG. 2, this mounting is performed by the gate 1g, the source 1s, the drain 1d,
This is performed by connecting the semiconductor substrate 1b to a corresponding mounting terminal of the element mounting portion 21.

In FIG. 11, in step 400, a DC bias voltage Vg is applied between the gate, source and drain from the variable DC voltage source 221 and an AC voltage is applied from the AC voltage source 222 to change the DC bias voltage Vg as a gate voltage. Then, a current and a voltage flowing between the gate, the source, and the drain are measured by an ammeter 224 and a voltmeter 223, and based on the measurement result, a plurality of values indicating the relationship between the gate-source-drain capacitance Cgc and the gate voltage Vg are determined. Cg
Obtain c-Vg characteristics. The obtained Cgc-Vg characteristics are as shown in FIG. FIG. 1 shows an example of actual measurement of Cgc-Vg characteristics.
It is shown in FIG. In the figure, curves P21, P22, P2
3, P24 has a gate length Lg of 1.0 μm,
Gate width W at 0.5 μm, 0.36 μm, 0.24 μm
Shows the Cgc-Vg characteristic of a MOSFET having a thickness of 1.0 mm.

Next, in step 402, step 40
The gate-source-drain capacitance Cgc of the Cgc-Vg characteristic obtained at 0 is differentiated by the gate voltage Vg, and the differentiated gate-source-drain capacitance Cgc is further differentiated by the gate length Lg. ∂ / ∂L (∂Cgc / ∂V) indicating the relationship between ∂Cgc / ∂Vg) and gate voltage Vg
g) Find the -Vg characteristic. This characteristic diagram is shown in FIG.
FIG. 15 shows an actual measurement example of the ∂ / ∂L (∂Cgc / ∂Vg) -Vg characteristics. In the figure, curves R1 and R2 indicate that the gate length Lg is between 0.5 μm and 0.36 μm and that the gate length Lg is 0.36 μm.
And between 0.24 μm, the curve R3 shows the gate length Lg
Is between 1.0 μm and 0.5 μm.

Further, in step 404, step 402
From the ∂ / ∂L (∂Cgc / ∂Vg) -Vg characteristics obtained in the above, the value Vx of the gate voltage Vg at which the dependency on the gate length Lg appears in the plurality of Cgc-Vg characteristics is obtained.
This is represented by ∂ / ∂L (∂Cgc / ∂Vg) in FIG.
The value of the gate voltage Vg at the rising point of the -Vg characteristic is Vx
Asking. From FIG. 12, the gate voltage value Vx is -0.4
V. Further, the gate voltage value Vx may be obtained as follows. That is, the gate-source-drain capacitance Cgc of the Cgc-Vg characteristic is changed to the gate voltage Vg.
And the differentiated gate-source-drain capacitance Cgc is further differentiated by the gate length Lg.
A ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic showing a relationship between (∂Cgc / ∂Vg) and the gate voltage Vg is obtained,
The gate voltage value Vp at which a peak occurs in the ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic, and the ∂ / ∂L
g (∂Cgc / ∂Vg) -Vg
w, a constant k (1.0 <k <1.5), and Vx = Vp−k ·
The gate voltage value Vx obtained as Vw is calculated by the plurality of Cgc values.
It is assumed that the gate voltage value Vx has a dependency on the gate length Lg in the -Vg characteristic. ∂ / ∂Lg (∂Cgc / ∂
Vg)-Gate voltage value Vx based on half-value width in -Vg characteristic
FIG. 16 shows an example of actual measurement for obtaining. In the figure, the vertical axis represents ∂ / ∂Lg (∂Cgc / ∂Vg) and its maximum value ∂ / ∂L.
g (∂Cgc / ∂Vg) max. In the figure, Vp is 0.5 V, half width Vw is 0.8 V, and constant k is 1.1. From these values, the gate voltage value Vx
Is: Vx = Vp−k · Vw = 0.5−1.1 × 0.8 =
-0.38V. The gate length Lg is a value between 1.0 μm and 0.5 μm. Steps 406 to 412 thereafter are the same as steps 304 to 310 in FIG. 3 showing the operation of the data processing device according to the first embodiment. That is, from the Cgc-Vg characteristic, the value Cgc of the gate-source-drain capacitance Cgc at the gate voltage value Vx is obtained.
x is obtained (step 406), and the plurality of Cgc-Vg
The Cgc-Lg characteristic shown in FIG. 13 is obtained by obtaining and plotting the gate-source-drain capacitance Cgc with respect to each gate length Lg at the gate voltage Vg at which the gate-source-drain capacitance Cgc is saturated in the characteristics (step 408). ).

Next, Cgc-Lg obtained in step 408
The fringe capacitance Cf is obtained from the Cgc axis intercept of the characteristic (step 410), and in step 412, from the point where Cgc = Cx in the Cgc-Lg characteristic, the diffusion between the gate and the diffusion region serving as the source or drain is determined based on the fringe capacitance Cf. An overlap length ΔL, which is a length in the gate length direction in the overlap region, and an overlap capacitance Cov formed between the gate and the diffusion region in the overlap region are obtained. FIG. 17 shows an actual measurement example of the Cgc-Lg characteristic. The figure shows that the gate voltage Vg is 2.0 V
, The fringe capacitance Cf is 0.08 pF, the overlap capacitance Cov is 0.13 pF, and the overlap length ΔL is 56 nm.

According to the present embodiment, similarly to the first embodiment, the search for the value Cx of the gate-source-drain capacitance Cgc for obtaining the overlap length ΔL is performed by a plurality of Cgc-Vg Gate-source characteristics
Since the dependency between the drain-to-drain capacitance Cgc and the gate length Lg is obtained from the branch point, the short channel M
Also in the OSFET, the overlap length ΔL can be accurately obtained. At the same time, the overlap capacity C
ov and fringe volume can be determined.

Next, a third embodiment of the overlap length measuring apparatus according to the present invention will be described with reference to FIGS. The overlap length measuring apparatus according to the present embodiment changes the DC bias voltage VSUB applied to the semiconductor substrate of the MOSFET so as to drive in the forward direction until the source / drain-semiconductor substrate junction is forward biased. This is to determine the lap length.

The apparatus configuration of the MOSFET overlap length measuring apparatus according to the present embodiment is the same as the MOSFET overlap length / overlap capacity measuring apparatus according to the first embodiment shown in FIGS. The configuration of the measuring unit 22 of the electric measuring device 2 is the same except for a slightly different point and the operation of the data processing device 5, so the device configuration will be described with reference to FIGS. .

FIG. 18 shows the configuration of the electric measuring device 2 in FIG. The electric measuring device 2 includes an element mounting portion 21 ′ for mounting the device group 1 to be measured, and a current and a voltage between the gate and the substrate for each device to be measured of the device group 1 under the control of the data processing device 5. And a measurement unit 22 'for measurement.

The element mounting portion 21 'is provided on each of the gate 1g, the source 1s, the drain 1d and the semiconductor substrate 1b of the MOSFET or the MOS capacitor (M
OS capacitance pattern) 40 gate 40g, semiconductor substrate 4
0b.

The measuring unit 22 ′ includes a variable DC bias voltage source 2 for applying a DC bias voltage to the gate 1 g.
21, 225, an AC voltage source 222 connected in series with the variable DC bias voltage source 221, and a current flowing between the gate 1g (or gate 40g) of the MOSFET and the semiconductor substrate 1b (or semiconductor substrate 40b) are measured. 224 and gate 1g (or gate 40g)
And a voltmeter 223 for measuring a voltage applied between the semiconductor substrate 1b (or the semiconductor substrate 40b). The variable DC bias voltage source 225 functions as a DC bias voltage source that applies a DC bias voltage to the semiconductor substrate 1b of the MOSFET as the device group 1 to be measured.

The variable DC bias voltage sources 221 and 225 and the AC voltage source 222 are connected in series, and one end of the variable DC bias voltage source 225 is grounded. Also, element mounting part 2
The gate mounting terminal 1 ′ is connected to the substrate mounting terminal of the element mounting portion 21 ′ via a voltmeter 223. The board mounting terminal of the element mounting portion 21 ′ is connected to a connection point P between the variable DC bias voltage source 221 and the variable DC bias voltage source 225 via the ammeter 224. Further, the source mounting terminal and the drain mounting terminal of the element mounting portion 21 'are commonly connected and grounded.

Next, the operation of the data processing device 5 according to the embodiment of the present invention will be described with reference to the flowchart of FIG. First, the gate 40g and the semiconductor substrate 40b of the MOS capacitor 40 shown in FIG. 19A are set so as to be connected to corresponding mounting terminals of the element mounting portion 21 '.

In FIG. 20, in step 500, M
Gate of OS capacitor (MOS capacitance pattern) 40-
A DC bias voltage Vg is applied between the semiconductor substrates by the variable DC bias voltage source 221 and an AC voltage is applied by the AC voltage source 222, and the voltage source 225 is set to 0V. While changing the DC bias voltage Vg as the gate voltage,
The current flowing between the gate and the semiconductor substrate of the S capacitor 40 and the voltage applied between the gate and the semiconductor substrate of the S capacitor 40 are measured by an ammeter 2
24, a voltmeter 223 is measured, and a CV characteristic indicating a relationship between the gate voltage Vg and the capacitance C of the MOS capacitor 40 is obtained based on the measurement result. This C-V characteristic is shown in FIG.
It is shown in FIG. In the figure, the horizontal axis is the gate voltage Vg, and the vertical axis is C / C0. Here, C is M when the gate voltage Vg is applied.
The capacitance of the OS capacitor 40, and C0 is the capacitance of the MOS capacitor 40 when Vg = 0. In FIG. 21, a solid line X1 shows an ideal CV characteristic, and a broken line X2 shows an actually obtained CV characteristic. Ideal C-
In the V characteristic curve X1, the capacitance of the MOS capacitor 40 at Vg = 0 is called a flat band capacitance CFB.

The actually obtained CV characteristic curve X
2 is a MOS capacitor 4 due to a work function difference between a gate electrode and a semiconductor substrate and an electric charge contained in an oxide film.
Ideal CV due to the surface potential occurring at zero
From the characteristic curve X1, the voltage axis V is equal to the flat band voltage VFB.
The characteristic is shifted along g. Here, the flat band voltage VFB is a value obtained by compensating the surface potential and
The applied voltage required to flatten the energy band up to the surface of the semiconductor substrate of the capacitor 40, that is, the gate voltage Vg.

In step 502, the flat band capacitance C FB per unit area of the gate electrode in the MOS capacitor 40 at the point where the gate voltage, that is, the DC bias voltage Vg becomes equal to the flat band voltage V FB, from the CV characteristics obtained in step 500. Ask for.

Next, a plurality of MOs manufactured by the same process and having different gate lengths Lg (Lg = L1, L2, L3) formed in the surface portion of the semiconductor substrate or in the wells of the surface portion (Lg = L1, L2, L3).
An element group 1 to be measured composed of SFETs (NMOS transistors in the present embodiment) is prepared and
Is mounted on the element mounting portion 21 ′. This attachment is performed by connecting the gate 1g, the source 1s, the drain 1d, and the semiconductor substrate 1b of each MOSFET to be measured to the corresponding attachment terminal of the element attachment portion 21 ', as shown in FIG.

Next, in step 504, a DC bias voltage VSUB is applied to the surface of the semiconductor substrate or a plurality of MOSFETs having different gate lengths Lg formed in the wells of the surface, and a gate-source-drain DC bias voltage Vg, DC bias voltage VSU
B and the AC voltage are applied, and the gate-substrate capacitance CGSUB at Vg = VSUB + VFB is measured while changing the DC bias voltage VSUB. That is, MOSF
Bias setting (Vg = VSUB + VF) so that the energy band of the target area of the ET capacitance measurement becomes flat.
B) to increase the DC bias voltage VSUB from 0.7 V in the forward direction to -1.0 in the reverse direction with respect to the source / drain.
It should be changed to about V.

In step 506, the built-in potential Vbi between the substrate and the source / drain is obtained by simulation. In the next step 508, the gate-substrate capacitance CGSUB is plotted with respect to √ (Vbi-VSUB), as shown in FIG. Find a regression line. Here, the gate-substrate capacitance CGSUB is obtained by the following equations (3) and (4).

DSUB (VSUB) = k√ (Vbi−VSUB) (3)

CGSUB = CFB · (Lg−2LSD−2DSUB (VSUB)) · W + 2CSW (VSUB) (4) where DSUB is a depletion layer substrate formed between the substrate and the source / drain, as shown in FIG. DSUB (V1) and DSUB (V2) are the distances between the edge on the side and the boundary of the PN junction formed between the substrate and the source / drain.
This represents DSUB when VSUB = V1, V2 (V1> V2). LSD is the overlap length which is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain. Also Csw
Is the lateral capacitance between the gate and the substrate, the value decreases as DSUB decreases, and Csw at the limit of DSUB = 0
= 0. As shown in FIG. 22, as the voltage at which the PN junction formed between the source / drain and the substrate is forward-biased increases, the thickness of the depletion layer formed between the substrate / source / drain decreases.

Further, at step 510, the value of the intercept of the CGSUB axis CFB · (L
g-2LSD) .W (LSD is the overlap length, W is the gate width), the overlap length LSD which is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain is determined.

According to the present embodiment, the DC bias voltage VSUB applied to the substrate is measured in such a manner that it is driven in the forward direction until the source / drain is forward biased. The influence of the depletion layer formed between the substrates can be suppressed, and the accuracy of evaluating the PN junction position between the source / drain and the substrate can be improved.

Further, since the bias is set (Vg = VSUB + VFB) so that the energy band of the region for which the capacitance of the MOSFET is measured becomes flat, the depletion layer formed between the source / drain and the substrate becomes a PN junction. And the disturbance to the PN junction position determination is reduced. Therefore, according to the present embodiment, the overlap length close to the metallurgical bonding position can be obtained.

Next, an overlap length measuring apparatus according to a fourth embodiment of the present invention will be described with reference to FIGS. The overlap length measuring apparatus according to the present embodiment obtains the overlap length by changing the DC bias voltage VSUB applied to the semiconductor substrate of the MOSFET so as to drive in the forward direction until the MOSFET is turned on. is there.

The device configuration of the MOSFET overlap length measuring apparatus according to the present embodiment is different from the MOSFET overlap length measuring apparatus according to the third embodiment shown in FIGS. Except for the behavior of
Since the configuration is the same, the configuration of the apparatus will be described with reference to FIGS. 1, 18, and 19 as necessary, and redundant description will be omitted.

Next, the operation of the data processing device 5 according to the embodiment of the present invention will be described with reference to the flowchart of FIG. First, the gate 41g and the diffusion layer electrode 41a of the MOS capacitor 41 shown in FIG. 19B are set so as to be connected to the corresponding mounting terminals of the element mounting portion 21 'in FIG. The semiconductor substrate 41b is grounded.

In FIG. 24, in step 600, a variable DC bias voltage source 221 applies a DC bias voltage Vg and an AC voltage source 222 between a gate and a semiconductor substrate of a MOS capacitor (MOS capacitor pattern) 41 formed on a diffusion layer. The current flowing between the gate and the semiconductor substrate of the MOS capacitor 41 and the
The voltage applied between the semiconductor substrates is measured by the ammeter 224 and the voltmeter 223, and the CV characteristic indicating the relationship between the gate voltage Vg and the capacitance C of the MOS capacitor 41 is obtained based on the measurement result. This CV characteristic is as shown in FIG.

In step 602, the flat band capacitance C FB per unit area of the gate electrode in the MOS capacitor 40 at the point where the gate voltage, that is, the DC bias voltage Vg becomes equal to the flat band voltage V FB from the CV characteristics obtained in step 600. Ask for.

Next, a plurality of MOs manufactured by the same process and having different gate lengths Lg (Lg = L1, L2, L3) formed in the surface portion of the semiconductor substrate or in the wells of the surface portion (Lg = L1, L2, L3).
An element group 1 to be measured composed of SFETs (NMOS transistors in the present embodiment) is prepared and
Is mounted on the element mounting portion 21 ′. This attachment is performed by connecting the gate 1g, the source 1s, the drain 1d, and the semiconductor substrate 1b of each MOSFET to be measured to the corresponding attachment terminal of the element attachment portion 21 ', as shown in FIG.

Next, in step 604, as in the processing of steps 300 to 306 in FIG. 3 of the overlap length / overlap capacity measuring apparatus according to the first embodiment, the surface portion of the semiconductor substrate or the well of the surface portion is measured. Gate-source-drain capacitance C of the strong inversion region in a plurality of MOSFETs formed with different gate lengths Lg
gc is measured and the Cgc-Lg characteristic is determined.

That is, a plurality of Ms having different gate lengths Lg
For the OSFET, a DC bias voltage Vg and an AC voltage are applied between the gate, source, and drain by a variable DC bias voltage source 221 and an AC voltage source 222, and the DC bias voltage Vg as a gate voltage is changed to change the gate-source voltage. The current flowing between the drain and the voltage applied between the gate, source, and drain are measured by an ammeter 224 and a voltmeter 223, and the relationship between the gate-source-drain capacitance Cgc and the gate voltage Vg is determined based on the measurement results. Are obtained (see FIG. 4).

Further, in the plurality of Cgc-Vg characteristics, the gate-source-drain capacitance Cgc with respect to each gate length Lg at the gate voltage Vg at which the gate-source-drain capacitance Cgc is saturated is obtained and plotted. A characteristic (this characteristic corresponds to FIG. 6) is obtained.

Next, at step 606, the Cgc-L
Gate fringe capacitance 2 CFL from intercept of Cgc axis of g characteristic
In step 608, the gate-source-drain capacitance CGSD when the gate voltage Vg is Vg = 0 is measured while changing the DC bias voltage VSUB applied to the MOSFET substrate. That is, the bias is set (Vg = 0) so that the energy band of the region where the capacitance of the MOSFET is measured becomes flat,
It is assumed that the DC bias voltage VSUB is changed from 0.7 V in the forward direction to about −1.0 V in the reverse direction with respect to the source / drain.

In step 610, the built-in potential Vbi between the substrate, source and drain is obtained by simulation. In step 612, the gate-source-drain capacitance CGSD is plotted against √ (Vbi-VSUB). CGSD-√ (Vbi-VSUB) characteristic shown in FIG. Here, the gate-source-drain capacitance CGSD is obtained by the following equations (5) and (6).

DSD (VSUB) = k‘√ (Vbi−VSUB) (5)

CGSD = 2CFB ′ · (LSD−DSD (VSUB)) · W + 2CSW ′ (VSUB) + 2CFL (6) where DSD is a depletion layer formed between the substrate and the source / drain, as shown in FIG. DSD (V1), DSD (V2), which is the distance between the source / drain side end and the boundary of the PN junction formed between the substrate and the source / drain.
Represents DSD when VSUB = V1, V2 (V1> V2). LSD is the overlap length which is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain. Csw 'is the internal side surface capacitance between the gate and the source / drain. As DSD decreases, the value decreases and Csw' = 0 at the limit of DSD = 0. As shown in FIG. 25, the higher the forward bias voltage of the PN junction formed between the source / drain and the substrate, the greater the voltage between the substrate and the source / drain.
The thickness of the depletion layer formed between the drains becomes smaller.

Then, in step 614, step 61
Based on the minimum value of the gate-source-drain capacitance CGSD in the CGSD-√ (Vbi-VSUB) characteristic obtained in step 2, the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain is obtained. Find a certain overlap length LSD.

According to the present embodiment, since the DC bias voltage VSUB applied to the substrate is measured in such a way that it is driven in the forward direction up to the limit at which the MOSFET is turned on, the voltage between the source / drain and the substrate in the capacitance measurement is measured. The effect of the depletion layer formed in the substrate can be suppressed, and the accuracy of evaluating the PN junction position between the source / drain and the substrate can be improved.

Also, since the bias is set (Vg = 0 V) so that the energy band of the region where the capacitance of the MOSFET is measured becomes flat, the depletion layer formed between the source / drain and the substrate has a PN junction. And the disturbance to the PN junction position determination is reduced. Therefore, according to the present embodiment, the overlap length close to the metallurgical bonding position can be obtained.

A plurality of MOSFs having different gate lengths formed in the surface portion of the semiconductor substrate or in the wells of the surface portion.
For ET, a DC bias voltage Vg and an AC voltage are applied between the gate, source, and drain, and the DC bias voltage Vg as a gate voltage is changed to measure a current flowing between the gate, source, and drain. A first process for obtaining a plurality of Cgc-Vg characteristics indicating a relationship between a gate-source-drain capacitance Cgc and a gate voltage Vg based on the above, and a dependency on the gate length Lg appears in the plurality of Cgc-Vg characteristics. Gate voltage Vg
Of the gate-source-drain capacitance Cgc at the gate voltage Vx from the Cgc-Vg characteristic.
A second process for calculating the value Cx of the plurality of Cgc-V
In g characteristics, gate-source-drain capacitance Cgc
And Cgc-Lg obtained by the third process of obtaining the Cgc-Lg characteristic by obtaining and plotting the gate-source-drain capacitance Cgc with respect to each gate length Lg at the gate voltage Vg at which is saturated. A fourth process of obtaining the fringe capacitance Cf from the Cgc axis intercept of the characteristic, and an overlap region between the gate and a diffusion region serving as a source or a drain based on the fringe capacitance Cf from the point where Cgc = Cx in the Cgc-Lg characteristic. Overlap length ΔL which is the length in the gate length direction at
And a fifth process for obtaining an overlap capacitance Cov formed between the gate and the diffusion region in the overlap region.
A program for causing a computer to execute the overlap length / overlap capacity measurement method of T may be recorded on a computer-readable recording medium.

By causing the computer system to read and execute the program recorded on the recording medium, the overlap length ΔL can be accurately obtained even for a short-channel MOSFET. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

In place of the second processing, any two gate lengths L in the plurality of Cgc-Vg characteristics are used.
The difference between the gate-source-drain capacitances Cgc at m, Ln (m ≠ n) is calculated, and the value of the gate voltage Vg at a ratio of the difference to a maximum value is calculated as the plurality of Cg.
A sixth process for obtaining a gate voltage value Vx in which dependence on the gate length Lg appears in the c-Vg characteristic and obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Cgc-Vg characteristic is described. A program for causing a computer to execute the method for measuring the overlap length and the overlap capacitance of a MOSFET, which is characterized by having the same, may be recorded on a computer-readable recording medium.

By causing the computer system to read and execute the program recorded on the recording medium, the overlap length ΔL can be accurately obtained even for a short-channel MOSFET. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

Further, instead of the second process, in the plurality of Cgc-Vg characteristics obtained in the first process, the gate-source-drain capacitance Cgc is differentiated by the gate voltage Vg, and is expressed as {Cgc / ∂Vg}. A seventh process for obtaining a plurality of ∂Cgc / ∂Vg-Vg characteristics indicating a relationship with the gate voltage Vg, and obtaining a rising point of the plurality of ∂Cgc / ∂Vg-Vg characteristics to obtain the plurality of ∂Cgc / ∂ The value of the gate voltage Vg at which the dependence on the gate length Lg appears in the Vg-Vg characteristic is Vx, and the value Cx of the gate-source-drain capacitance Cgc at the gate voltage Vx is obtained from the Cgc-Vg characteristic. A program for causing a computer to execute a method for measuring an overlap length and an overlap capacitance of a MOSFET, the method comprising: It may be recorded in a recording medium readable by Yuta. Read the program recorded on this recording medium into a computer system,
By performing this, it is possible to accurately determine the overlap length ΔL even in a short-channel MOSFET. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

Instead of the second process, the gate-source-drain capacitance Cgc of the Cgc-Vg characteristic obtained in the first process is differentiated by the gate voltage Vg, and the differentiated gate-source-drain capacitance is obtained. Cgc is further differentiated by the gate length Lg, and ∂ / ∂Lg (∂Cgc / ∂Vg) showing the relationship between ∂ / ∂Lg (∂Cgc / ∂Vg) and the gate voltage Vg.
g) Ninth processing for obtaining -Vg characteristic, and ∂ / ∂Lg
A rising point of the (∂Cgc / ∂Vg) -Vg characteristic is obtained, and a value of the gate voltage Vg at which the dependence on the gate length Lg appears in the plurality of Cgc-Vg characteristics is Vx,
And a tenth process for obtaining a value Cx of a gate-source-drain capacitance Cgc at a gate voltage value Vx from the Cgc-Vg characteristic.
A program for causing a computer to execute the overlap length / overlap capacity measurement method described above may be recorded on a computer-readable recording medium.

By reading and executing the program recorded on the recording medium by a computer system, the overlap length ΔL can be accurately obtained even for a short-channel MOSFET. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

A CV characteristic indicating the relationship between the DC bias voltage Vg applied between the gate electrode of the MOS capacitance pattern and the substrate and the capacitance C is obtained. From the CV characteristic, the DC bias voltage Vg is determined to be a flat band. A first process for obtaining a flat band capacitance CFB per unit area of the gate electrode at a point equal to the voltage VFB, and an overlap length LSD and a gate width formed in a surface portion of the semiconductor substrate or a well in the surface portion. W is constant and the gate length Lg
DC bias voltage VSUB, a DC bias voltage VSUB, an AC voltage between a gate, a source and a drain, and a DC bias voltage VSU.
Gate at Vg = VSUB + VFB while changing B
A second process for measuring the inter-substrate capacitance CGSUB, a third process for obtaining a built-in potential Vbi between the substrate, the source and the drain by simulation, and a process for calculating the gate-substrate capacitance CGSUB with respect to √ (Vbi-VSUB). A regression line is obtained by plotting, and since the intercept value of the CGSUB axis in the regression line is CFB · (Lg−2LSD) · W, the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain And a fourth process for obtaining an overlap length LSD which is the length of the MOSFET. A program for causing a computer to execute the MOSFET overlap length measurement method is recorded on a computer-readable recording medium. It may be.

By causing the computer system to read and execute the program recorded on this recording medium, the DC bias voltage VSUB applied to the substrate is supplied to the source system.
Measurement and data processing can be performed in such a way that the drain is driven in the forward direction up to the limit at which the drain is forward biased. As a result, the influence of a depletion layer formed between the source / drain and the substrate in the capacitance measurement can be suppressed,・ Evaluation accuracy of the PN junction position between the drain and the substrate can be improved.

Also, since the bias is set (Vg = VSUB + VFB) so that the energy band of the region where the capacitance of the MOSFET is measured becomes flat, the depletion layer formed between the source / drain and the substrate is a PN junction. And the disturbance to the PN junction position determination is reduced. Therefore, the overlap length close to the metallurgical bonding position can be obtained.

The DC bias voltage Vg applied between the gate electrode of the MOS capacitor pattern on the diffusion layer and the diffusion layer
Characteristics obtained from the CV characteristics showing the relationship between the capacitance and the capacitance C, and from the CV characteristics, the diffusion layer flat band capacitance CFB per unit area of the gate electrode at the point where the DC bias voltage Vg becomes equal to the flat band voltage VFB. And a plurality of MOSFETs formed in the surface portion of the semiconductor substrate or in the wells of the surface portion, having the same overlap length LSD and gate width W and different gate lengths Lg.
With respect to, a DC bias voltage Vg and an AC voltage are applied between the gate and the source and the drain, and the DC bias voltage Vg as the gate voltage is changed to measure a current flowing between the gate and the source and the drain. A second process of obtaining a plurality of Cgc-Vg characteristics indicating a relationship between the gate-source-drain capacitance Cgc and the gate voltage Vg based on the gate-source-drain capacitance Cgc in the plurality of Cgc-Vg characteristics. A third process of obtaining a Cgc-Lg characteristic by obtaining and plotting a gate-source-drain capacitance Cgc with respect to each gate length Lg at a saturated gate voltage Vg;
Fourth processing for obtaining the gate fringe capacitance CFL on one side from the intercept of the Cgc axis of the c-Lg characteristic, and changing the DC bias voltage VSUB applied to the MOSFET substrate while changing the gate-source voltage when the gate voltage Vg is Vg = 0. Fifth processing for measuring the drain-to-drain capacitance CGSD, sixth processing for obtaining the built-in potential Vbi between the substrate, source and drain by simulation, and setting the gate-source-drain capacitance CGSD to √ (Vbi-VSUB) CGSD-√ (Vbi-VSUB) characteristic is obtained by plotting
The minimum value of the gate-source-drain capacitance CGSD in the CGSD-√ (Vbi-VSUB) characteristic is CFB '· LSD · W +
A seventh process for obtaining an overlap length LSD which is a length in a gate length direction in an overlap region between a gate and a diffusion region serving as a source or a drain because of 2CFL. A program for causing a computer to execute the length measuring method may be recorded on a computer-readable recording medium.

By reading this program into a computer system and executing the program, the DC bias voltage VSUB applied to the substrate can be measured and driven in such a way that the DC bias voltage VSUB is driven in the forward direction until the MOSFET is turned on. As a result, the influence of the depletion layer formed between the source / drain and the substrate in the capacitance measurement can be suppressed, and the accuracy of evaluating the PN junction position between the source / drain and the substrate can be improved.

Further, since the bias is set (Vg = 0 V) so that the energy band of the region for which the capacitance of the MOSFET is measured becomes flat, the depletion layer formed between the source / drain and the substrate has a PN junction. And the disturbance to the PN junction position determination is reduced. Therefore, the overlap length close to the metallurgical bonding position can be obtained.

[0109]

As described above, according to the first aspect of the present invention, the search for the value Cx of the gate-source-drain capacitance Cgc for obtaining the overlap length ΔL is performed by a plurality of Cgc. Since the dependence on the gate length Lg of the gate-source-drain capacitance Cgc in the −Vg characteristic is determined from the branch point, the overlap length Δ can be accurately determined even in a short-channel MOSFET.
L can be obtained. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

According to the second to fifth aspects of the present invention, the search for the value Cx of the gate-source-drain capacitance Cgc for obtaining the overlap length ΔL is performed in a plurality of Cgc-Vg characteristics. Since the dependency between the source-drain capacitance Cgc and the gate length Lg is determined from the branch point, the short-channel MOSFE
Also at T, the overlap length ΔL can be accurately obtained. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

According to the sixth aspect of the present invention, the DC bias voltage VSUB applied to the substrate is measured in such a manner as to drive in the forward direction up to the limit at which the source / drain is forward biased. The influence of the depletion layer formed between the source / drain and the substrate can be suppressed, and the evaluation accuracy at the PN junction position between the source / drain and the substrate can be improved.

Further, since the bias is set (Vg = VSUB + VFB) so that the energy band of the region where the capacitance of the MOSFET is measured becomes flat, the depletion layer formed between the source / drain and the substrate has a PN junction. And the disturbance to the PN junction position determination is reduced. Therefore, the overlap length close to the metallurgical bonding position can be obtained.

According to the seventh aspect of the present invention, the DC bias voltage VSUB applied to the substrate is measured in such a manner that it is driven in the forward direction up to the limit at which the MOSFET is turned on. The influence of the depletion layer formed between the drain and the substrate can be suppressed, and the evaluation accuracy of the PN junction position between the source and the drain can be improved.

Further, since the bias is set (Vg = 0 V) so that the energy band of the region where the capacitance of the MOSFET is measured becomes flat, the depletion layer formed between the source / drain and the substrate becomes a PN junction. And the disturbance to the PN junction position determination is reduced. Therefore, the overlap length close to the metallurgical bonding position can be obtained.

According to the present invention, the processing means searches for the value Cx of the gate-source-drain capacitance Cgc for obtaining the overlap length ΔL in a plurality of Cgc-Vg characteristics. Gate-source
Since the dependency between the drain-to-drain capacitance Cgc and the gate length Lg is obtained from the branch point, the short channel M
Also in the OSFET, the overlap length ΔL can be accurately obtained. At the same time, the overlap capacity C
ov and fringe volume can be determined.

According to the ninth to twelfth aspects of the present invention,
The processing means searches for the value Cx of the gate-source-drain capacitance Cgc for obtaining the overlap length ΔL, and finds the dependence of the gate-source-drain capacitance Cgc on the gate length Lg in a plurality of Cgc-Vg characteristics. Is obtained from the branch point where appears, so that even in the short-channel MOSFET, the overlap length Δ
L can be obtained. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

According to the thirteenth aspect of the present invention, the DC bias voltage VSUB applied to the substrate is measured by the measuring means and the processing means such that the DC bias voltage VSUB is driven in the forward direction until the source / drain is forward biased. Since the overlap length is obtained by performing the processing, the influence of the depletion layer formed between the source / drain and the substrate in the capacitance measurement can be suppressed, and the evaluation accuracy at the PN junction position between the source / drain and the substrate can be improved. Can be achieved.

Since the bias is set (Vg = VSUB + VFB) so that the energy band of the region where the capacitance of the MOSFET is measured becomes flat, the depletion layer formed between the source / drain and the substrate is a PN junction. And the disturbance to the PN junction position determination is reduced. Therefore, the overlap length close to the metallurgical bonding position can be obtained.

According to the fourteenth aspect of the present invention, the DC bias voltage VSUB applied to the substrate is measured by the measuring means and the processing means in such a manner that the DC bias voltage VSUB is driven in the forward direction until the MOSFET is turned on, and data processing is performed. In this manner, the overlap length is determined, so that the influence of the depletion layer formed between the source, drain and substrate in the capacitance measurement can be suppressed, and the evaluation accuracy of the PN junction position between the source, drain and substrate can be improved. I can do it.

Since the bias is set (Vg = 0 V) so that the energy band of the region where the capacitance of the MOSFET is measured becomes flat, the depletion layer formed between the source / drain and the substrate has a PN junction. And the disturbance to the PN junction position determination is reduced. Therefore, the overlap length close to the metallurgical bonding position can be obtained.

According to the fifteenth aspect of the present invention, a plurality of MOSFETs having different gate lengths formed in the surface portion of the semiconductor substrate or in the wells of the surface portion are provided.
A DC bias voltage Vg and an AC voltage are applied between the source and the drain, the DC bias voltage Vg as a gate voltage is changed, and a current flowing between the gate and the source and the drain is measured. A first process of obtaining a plurality of Cgc-Vg characteristics indicating a relationship between a source-drain capacitance Cgc and a gate voltage Vg, and a value of a gate voltage Vg in which the plurality of Cgc-Vg characteristics has dependency on a gate length Lg Vx is determined, and the gate voltage at the gate voltage value Vx is obtained from the Cgc-Vg characteristic.
A second process for obtaining a value Cx of the source-drain capacitance Cgc;
Gate voltage V at which the source-drain capacitance Cgc is saturated
g is obtained by plotting the gate-source-drain capacitance Cgc with respect to each gate length Lg at g.
a third process for obtaining the gc-Lg characteristic, a fourth process for obtaining the fringe capacitance Cf from the Cgc axis intercept of the Cgc-Lg characteristic obtained by the third process, and the Cgc-Lg
From the point where Cgc = Cx in the characteristics, the fringe capacitance C
The overlap length ΔL, which is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as a source or a drain, based on f, and the overlap formed between the gate and the diffusion region in the overlap region. And a fifth process for obtaining the lap capacitance Cov, wherein a program for causing the computer to execute the method for measuring the overlap length and the overlap capacitance of the MOSFET is recorded on a computer-readable recording medium. Therefore, by causing the computer system to read and execute this program, the overlap length ΔL can be accurately obtained even in the short-channel MOSFET. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

According to the sixteenth aspect of the present invention, instead of the second processing, in the plurality of Cgc-Vg characteristics, the gate-source voltage at any two gate lengths Lm and Ln (m ≠ n) is obtained. The difference between the drain-to-drain capacitances Cgc is taken, and the value of the gate voltage Vg at a value where the difference is a certain ratio with respect to the maximum value is defined as the gate voltage value Vx in which the dependence on the gate length Lg appears in the plurality of Cgc-Vg characteristics. And a sixth process for obtaining a value Cx of a gate-source-drain capacitance Cgc at a gate voltage value Vx from the Cgc-Vg characteristic. A program for causing a computer to execute the overlap capacity measuring method is recorded on a computer-readable recording medium. , To read the program in the computer system, by executing, even in short-channel MOSFET, can be obtained accurately overlap length [Delta] L. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

According to the seventeenth aspect of the present invention, according to the seventeenth aspect, instead of the second processing, a gate is used in the plurality of Cgc-Vg characteristics obtained in the first processing. ∂Cgc / ∂Vg obtained by differentiating the source-drain capacitance Cgc with the gate voltage Vg and the gate voltage Vg
A seventh process for obtaining a plurality of ∂Cgc / ∂Vg-Vg characteristics indicating the relationship between the plurality of ∂Cgc / ∂Vg-Vg.
A plurality of ΔCgc / ΔV is obtained by calculating a rising point of the characteristic.
The value of the gate voltage Vg at which the dependence on the gate length Lg appears in the g-Vg characteristic is Vx, and the Cgc-
8. The measurement of the overlap length and the overlap capacitance of the MOSFET according to claim 1, further comprising an eighth process of obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Vg characteristic. Since the program for causing the computer to execute the method is recorded on a computer-readable recording medium, this program is read and executed by the computer system, so that even in the short channel MOSFET, the overlap length can be accurately determined. ΔL can be determined. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

According to the eighteenth aspect, instead of the second processing, the Cgc-Vg obtained in the first processing is obtained.
The gate-source-drain capacitance Cgc of the characteristic is differentiated by the gate voltage Vg, and the differentiated gate-source-drain capacitance Cgc is further differentiated by the gate length Lg.
A ninth process for obtaining a ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic indicating a relationship between ∂Lg (∂Cgc / ∂Vg) and the gate voltage Vg, and the ∂ / ∂Lg (∂Cgc / ∂) V
g) Finding the rising point of the -Vg characteristic
The value of the gate voltage Vg at which the dependence on the gate length Lg appears in the c-Vg characteristic is Vx, and the Cgc-
A tenth process for obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Vg characteristic;
2. The MOSF according to claim 1, wherein
Since a program for causing a computer to execute the ET overlap length / overlap capacity measurement method is recorded on a computer-readable recording medium, the computer system reads the program and executes the program, thereby shortening the program. Channel MOSF
Also in the ET, the overlap length ΔL can be accurately obtained. At the same time, the overlap capacity Cov and the fringe capacity can be obtained.

According to the nineteenth aspect, instead of the second processing, the Cgc-Vg obtained in the first processing is used.
The gate-source-drain capacitance Cgc of the characteristic is differentiated by the gate voltage Vg, and the differentiated gate-source-drain capacitance Cgc is further differentiated by the gate length Lg.
A ninth process for obtaining a ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic indicating a relationship between ∂Lg (∂Cgc / ∂Vg) and the gate voltage Vg, and the ∂ / ∂Lg (∂Cgc / ∂) V
g) The value of the gate voltage Vp at which a peak occurs in the -Vg characteristic, the half-value width in the ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic is Vw, and the constant is k (1.0 <k <1.5), Vx = Gate voltage value V obtained as Vp-kVw
x is the gate length Lg in the plurality of Cgc-Vg characteristics.
And the gate voltage at the gate voltage Vx from the Cgc-Vg characteristic.
Eleventh calculation of the value Cx of the source-drain capacitance Cgc
2. The processing according to claim 1, further comprising:
A program for causing a computer to execute the method of measuring the overlap length and the overlap capacitance of the OSFET is recorded on a computer-readable recording medium. Channel M
Also in the OSFET, the overlap length ΔL can be accurately obtained. At the same time, the overlap capacity C
ov and fringe volume can be determined.

According to the twentieth aspect, the MOS
A CV characteristic indicating a relationship between the capacitance C and a DC bias voltage Vg applied between the gate electrode of the capacitance pattern and the substrate is obtained, and the DC bias voltage Vg becomes equal to the flat band voltage VFB based on the CV characteristic. In the first process for obtaining the flat band capacitance CFB per unit area of the gate electrode at a point, the overlap length LSD and the gate width W formed in the surface portion of the semiconductor substrate or in the well of the surface portion are constant. MOSFs having different gate lengths Lg
Applying a DC bias voltage VSUB to the substrate for ET,
And a DC bias voltage V between the gate and the source / drain.
g, while applying the DC bias voltage VSUB and the AC voltage, and changing the DC bias voltage VSUB, Vg
= V SUB + V FB, a second process for measuring the gate-substrate capacitance CGSUB, a third process for obtaining a built-in potential Vbi between the substrate, source and drain by simulation, and the gate-substrate capacitance CGSUB
(Vbi−VSUB) is plotted to obtain a regression line, and the intercept value of the CGSUB axis in the regression line is CFB ·
Because of (Lg−2LSD) · W, the overlap length LSD is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain.
And a fourth process for determining
Since the program for causing the computer to execute the FET overlap length measuring method is recorded on a computer-readable recording medium, the computer system reads and executes the program, so that the direct current applied to the substrate is reduced. Bias voltage VSUB
Can be measured in the forward direction to the limit where the source / drain is forward biased, and data processing can be performed. As a result, the influence of the depletion layer formed between the source / drain and the substrate in the capacitance measurement can be suppressed. As a result, the evaluation accuracy of the PN junction position between the source / drain and the substrate can be improved.

Further, since the bias is set (Vg = VSUB + VFB) so that the energy band of the region where the capacitance of the MOSFET is measured becomes flat, the depletion layer formed between the source / drain and the substrate has a PN junction. And the disturbance to the PN junction position determination is reduced. Therefore, the overlap length close to the metallurgical bonding position can be obtained.

According to the twenty-first aspect of the present invention, C representing the relationship between the DC bias voltage Vg applied between the gate electrode of the MOS capacitance pattern on the diffusion layer and the diffusion layer and the capacitance C.
A first process of obtaining a −V characteristic, and a diffusion band flat band capacitance CFB ′ per unit area of the gate electrode at a point where the DC bias voltage Vg becomes equal to the flat band voltage VFB from the CV characteristic; The overlap length LSD and the gate width W formed in the surface portion of the semiconductor substrate or in the well of the surface portion are constant and the gate length Lg
DC bias voltage Vg and AC voltage are applied between the gate, source and drain of the plurality of MOSFETs having different
Is changed to measure the current flowing between the gate-source / drain, and based on the measurement result, a plurality of Cgc-Vg characteristics indicating the relationship between the gate-source-drain capacitance Cgc and the gate voltage Vg are obtained. And the gate-source-drain capacitance Cgc for each gate length Lg at the gate voltage Vg at which the gate-source-drain capacitance Cgc is saturated in the plurality of Cgc-Vg characteristics.
, And a third process for obtaining the Cgc-Lg characteristic by plotting, and a fourth process for obtaining the gate fringe capacitance CFL on one side of the intercept of the Cgc axis of the Cgc-Lg characteristic. Fifth process for measuring the gate-source-drain capacitance CGSD when the gate voltage Vg is Vg = 0 while changing the DC bias voltage VSUB, and sixth process for obtaining a built-in potential Vbi between the substrate, source and drain by simulation. Processing and the gate-source-drain capacitance CGS
D is plotted against √ (Vbi-VSUB) and CGSD-√
(Vbi−VSUB) characteristic is obtained, and the CGSD−√ (Vbi−VSU) is obtained.
B) Gate-source-drain capacitance CGSD in characteristics
Since the minimum value is CFB ′ · LSD · W + 2CFL, a seventh process for obtaining an overlap length LSD which is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain is provided. Since the program for causing the computer to execute the method of measuring the overlap length of the MOSFET is recorded on a computer-readable recording medium, the program is read and executed by a computer system. The DC bias voltage VSUB applied to the substrate can be measured and processed in a forward direction until the MOSFET is turned on to the limit at which the MOSFET is turned on, and as a result, the DC bias voltage VSUB is formed between the source / drain and the substrate in the capacitance measurement. The effect of the depletion layer can be suppressed, and between the source / drain and the substrate It can be improved evaluation accuracy of definitive PN junction position.

Further, since the bias is set (Vg = 0 V) so that the energy band of the region where the capacitance of the MOSFET is measured becomes flat, the depletion layer formed between the source / drain and the substrate is a PN junction. And the disturbance to the PN junction position determination is reduced. Therefore, the overlap length close to the metallurgical bonding position can be obtained.

[Brief description of the drawings]

FIG. 1 is a MOSFET according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing an electrical configuration of the overlap length / overlap capacity measurement device of FIG.

FIG. 2 is a circuit diagram showing a configuration of the electric measurement device in FIG.

FIG. 3 is a flowchart showing processing contents of the data processing device in FIG. 1;

FIG. 4 is a graph Cgc-V showing the relationship between the gate-source-drain capacitance Cgc and the gate voltage Vg obtained based on the measurement result of each part of the MOSFET by the electric measurement device.
g characteristic diagram.

FIG. 5 shows dCgc / d obtained from Cgc-Vg characteristics.
dCgc / dV indicating the relationship between dVg and gate voltage Vg
The g-Vg characteristic figure.

FIG. 6 is a graph showing the relationship between the gate length Lg of the MOSFET and the gate-source / drain capacitance Cgc.
g characteristic diagram.

FIG. 7 is a graph showing the relationship between the gate-source-drain capacitance Cgc and the gate voltage Vg obtained based on the measurement result of each part of the MOSFET by the electric measurement device.
FIG. 9 is a graph showing actual measurements of g characteristics.

8 is a characteristic diagram showing a difference between Cgc-Vg characteristics shown in FIG.

9 is a view showing a differential characteristic of the Cgc-Vg characteristic shown in FIG.

10 is a characteristic diagram showing the relationship between the gate length Lg of the MOSFET and the gate-source-drain capacitance Cgc obtained based on the Cgc-Vg characteristics shown in FIG. 7;

FIG. 11 shows a MOSFE according to a second embodiment of the present invention.
9 is a flowchart showing processing contents of a data processing device of the overlap length and overlap capacity measurement device of T.

FIG. 12 shows ∂ / ∂Lg obtained by differentiating the dCgc / dVg-Vg characteristic shown in FIG. 5 with the gate length Lg.
∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic diagram showing the relationship between (∂Cgc / ∂Vg) and gate voltage Vg.

FIG. 13 is a graph showing the relationship between the gate length Lg of the MOSFET and the gate-source-drain capacitance Cgc.
-Lg characteristic diagram.

FIG. 14 is a graph showing the relationship between the gate-source-drain capacitance Cgc and the gate voltage Vg obtained based on the measurement result of each part of the MOSFET by the electric measurement device.
FIG. 4 is a characteristic diagram showing an example of actual measurement of Vg characteristics.

FIG. 15 is a graph showing the relationship between ∂ / ∂Lg (∂Cgc / ∂Vg) and the gate voltage Vg obtained from the Cgc-Vg characteristics shown in FIG. 14 and ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristics. .

FIG. 16 shows ∂ / ∂Lg (∂Cgc / ∂V) shown in FIG.
g) Among the -Vg characteristics, MOSFET having the largest gate length
FIG. 7 is a diagram showing a characteristic indicating a difference between the characteristic of the MOSFET and the characteristic of the MOSFET having the minimum gate length.

FIG. 17 is a characteristic diagram showing the relationship between the gate length Lg of the MOSFET and the gate-source-drain capacitance Cgc obtained based on the Cgc-Vg characteristics shown in FIG. 14;

FIG. 18 is a circuit diagram showing a configuration of an electrical measuring device in an overlap length measuring device according to a third embodiment of the present invention.

FIG. 19A is an explanatory view showing the structure of a MOS capacitor, and FIG. 19B is a diagram showing an MO formed on a diffusion layer.
FIG. 3 is an explanatory diagram showing a structure of an S capacitor.

FIG. 20 is a flowchart showing processing contents of a data processing device in the overlap length measuring device according to the third embodiment of the present invention.

FIG. 21 is a characteristic diagram showing CV characteristics of a MOS capacitor.

FIG. 22 is an explanatory diagram showing a state of a depletion layer formed between a source / drain of a MOSFET and a substrate when the overlap length is measured by the overlap length measuring device according to the third embodiment of the present invention.

FIG. 23 shows that the MOSFET gate-substrate capacitance CGSUB is set to √ (V) when the overlap length is measured by the overlap length measuring apparatus according to the third embodiment of the present invention.
bi-VSUB).

FIG. 24 is a flowchart showing processing contents of a data processing device in the overlap length measuring device according to the fourth embodiment of the present invention.

FIG. 25 is an explanatory diagram showing a state of a depletion layer formed between a source / drain of a MOSFET and a substrate when the overlap length is measured by the overlap length measuring apparatus according to the third embodiment of the present invention.

FIG. 26 shows that the capacitance CGSUB between the gate and the substrate of the MOSFET at the time of measuring the overlap length by the overlap length measuring device according to the third embodiment of the present invention is represented by Δ (V
bi-VSUB).

FIG. 27 is a cross-sectional view showing a structure of a device used when measuring an overlap length by a conventional overlap length measuring method.

28 is a characteristic diagram showing measurement results of gate-substrate capacitance with respect to the gate voltage of each device shown in FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 element group to be measured 2 electrical measuring device 3 input device 4 recording medium 5 data processing device 6 storage device 7 output device 21 element mounting unit 22 measuring unit 221 variable DC bias voltage source 222 AC voltage source 223 voltmeter 224 ammeter 225 variable DC bias voltage source

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 29/00 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/8234 G01R 27/26 H01L 21/66 H01L 27/088 G01R 31/26

Claims (21)

(57) [Claims] A plurality of MOSFEs having different gate lengths formed in a surface portion of a semiconductor substrate or a well of the surface portion.
For T, a DC bias voltage Vg and an AC voltage are applied between the gate, source, and drain, and the DC bias voltage Vg as a gate voltage is changed to measure a current flowing between the gate, source, and drain. A first process for obtaining a plurality of Cgc-Vg characteristics indicating a relationship between a gate-source-drain capacitance Cgc and a gate voltage Vg based on the above, and a dependency on a gate length Lg appears in the plurality of Cgc-Vg characteristics A second process of obtaining a value Vx of the gate voltage Vg and obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Cgc-Vg characteristic; and a gate in the plurality of Cgc-Vg characteristics. -Source
By obtaining and plotting the gate-source-drain capacitance Cgc with respect to each gate length Lg at the gate voltage Vg at which the drain-to-drain capacitance Cgc is saturated, Cgc-L
a third process for obtaining the g characteristic; and Cgc of the Cgc-Lg characteristic obtained by the third process.
A fourth process of obtaining a fringe capacitance Cf from an axis intercept; and a gate length in an overlap region between a gate and a diffusion region serving as a source or a drain based on the fringe capacitance Cf from the point where Cgc = Cx in the Cgc-Lg characteristic. A fifth process of obtaining an overlap length ΔL that is a length in the direction and an overlap capacitance Cov formed between the gate and the diffusion region in the overlap region. Lap length / overlap capacity measurement method. 2. In place of the second processing, any two gate lengths Lm, Lm,
The difference between the gate-source-drain capacitances Cgc at Ln (m ≠ n) is obtained, and the value of the gate voltage Vg at a certain ratio of the difference to the maximum value is calculated as the plurality of Cgc-
A sixth process of obtaining a gate voltage value Vx at which dependency on the gate length Lg appears in the Vg characteristic, and obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Cgc-Vg characteristic. 2. The MOSFE according to claim 1, wherein:
Method for measuring overlap length and overlap capacity of T. 3. The method according to claim 2, wherein the plurality of Cgc-Vg characteristics obtained in the first processing are replaced with gate-to-gate characteristics.
A seventh process of obtaining a plurality of ∂Cgc / ∂Vg-Vg characteristics indicating a relationship between ∂Cgc / ∂Vg obtained by differentiating the source-drain capacitance Cgc with the gate voltage Vg and the gate voltage Vg; A branch point of the / Vg-Vg characteristic is obtained, a value of the gate voltage Vg at which the dependence on the gate length Lg appears in the plurality of the Cgc / Vg-Vg characteristics is Vx, and the gate voltage is obtained from the Cgc-Vg characteristic. Value C of gate-source-drain capacitance Cgc at value Vx
8. An MOSFE according to claim 1, further comprising: an eighth process for obtaining x.
Method for measuring overlap length and overlap capacity of T. 4. The gate-source-drain capacitance obtained by differentiating the gate-source-drain capacitance Cgc of the Cgc-Vg characteristic obtained in the first process by a gate voltage Vg instead of the second process. The relationship between the gate voltage Vg and ∂ / ∂Lg (∂Cgc / ∂Vg), which is obtained by differentiating the inter-capacitance Cgc with the gate length Lg, ∂ / ∂Lg (∂Cgc / ∂).
Vg) -ninth processing for obtaining the Vg characteristic; and determining the rising point of the ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic to show dependence on the gate length Lg in the plurality of Cgc-Vg characteristics. 10. A tenth process, wherein a value of a gate voltage Vg is Vx, and a value Cx of a gate-source-drain capacitance Cgc at the gate voltage value Vx is obtained from the Cgc-Vg characteristic. 2. The method for measuring an overlap length and an overlap capacitance of a MOSFET according to 1. 5. The gate-source-drain capacitance obtained by differentiating the gate-source-drain capacitance Cgc of the Cgc-Vg characteristic obtained in the first process by a gate voltage Vg instead of the second process. The relationship between the gate voltage Vg and ∂ / ∂Lg (∂Cgc / ∂Vg), which is obtained by differentiating the inter-capacitance Cgc with the gate length Lg, ∂ / ∂Lg (∂Cgc / ∂).
Vg) -Ninth processing for obtaining the Vg characteristic; a gate voltage value Vp at which a peak occurs in the ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic;
g (∂Cgc / ∂Vg) -Vg
w, a constant k (1.0 <k <1.5), and Vx = Vp−k ·
The gate voltage value Vx obtained as Vw is calculated by the plurality of Cgc values.
An eleventh process of obtaining a gate voltage value Vx at which dependency on the gate length Lg appears in the -Vg characteristic, and obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Cgc-Vg characteristic; 2. The MOSFE according to claim 1, wherein:
Method for measuring overlap length and overlap capacity of T. 6. A CV characteristic indicating a relationship between a capacitance C and a DC bias voltage Vg applied between a gate electrode of a MOS capacitance pattern and a substrate is obtained, and the DC bias voltage Vg is flattened from the CV characteristic. A first process for obtaining a flat band capacitance CFB per unit area of a gate electrode at a point equal to the band voltage VFB; and an overlap length LSD and a gate formed in a surface portion of a semiconductor substrate or a well in the surface portion. A DC bias voltage VSUB is applied to the substrate for a plurality of MOSFETs having a constant width W and different gate lengths Lg, and
While applying the DC bias voltage Vg, the DC bias voltage VSUB and the AC voltage between the source and the drain, and changing the DC bias voltage VSUB, Vg = VSUB + VFB
A second process of measuring the gate-substrate capacitance CGSUB in the above, a third process of obtaining a built-in potential Vbi between the substrate-source / drain by simulation, and a process of calculating the gate-substrate capacitance CGSUB by − (Vbi−VSUB). And the intercept of the CGSUB axis in the regression line is CFB · (Lg−2LSD) · W, so that in the overlap region between the gate and the diffusion region serving as the source or drain. A fourth process for obtaining an overlap length LSD which is a length in the gate length direction; and a method for measuring an overlap length of a MOSFET. 7. A CV characteristic showing a relationship between a capacitance C and a DC bias voltage Vg applied between the gate electrode of the MOS capacitance pattern on the diffusion layer and the diffusion layer, and the DC bias is obtained from the CV characteristic. Voltage Vg is flat band voltage VFB
A first process for obtaining a flat band capacitance CFB ′ per unit area of the gate electrode at a point where the overlap length LSD and the overlap length LSD formed in the surface portion of the semiconductor substrate or the well of the surface portion are obtained. For a plurality of MOSFETs having a constant gate width W and different gate lengths Lg, a DC bias voltage V
g and an AC voltage are applied, the DC bias voltage Vg as a gate voltage is changed to measure a current flowing between the gate-source / drain, and based on the measurement result, a gate-source-drain capacitance Cgc and a gate Voltage Vg
A second process for obtaining a plurality of Cgc-Vg characteristics indicating a relationship between the gate-source and the plurality of Cgc-Vg characteristics.
By obtaining and plotting the gate-source-drain capacitance Cgc with respect to each gate length Lg at the gate voltage Vg at which the drain-to-drain capacitance Cgc is saturated, Cgc-L
a third process for obtaining a g characteristic, a fourth process for obtaining a gate fringe capacitance CFL on one side from an intercept of a Cgc axis of the Cgc-Lg characteristic, and a DC bias voltage VSUB applied to a MOSFET substrate.
A fifth process of measuring the gate-source-drain capacitance CGSD when the gate voltage Vg is Vg = 0 while changing the gate voltage Vg = 0, a sixth process of obtaining a built-in potential Vbi between the substrate-source-drain by simulation, − The source-drain capacitance CGSD is set to √ (Vbi
−VSUB) and plotting CGSD−√ (Vbi−VSU)
B) The characteristic is obtained, and since the minimum value of the gate-source-drain capacitance CGSD in the CGSD-√ (Vbi-VSUB) characteristic is CFB ′ · LSD · W + 2CFL, the difference between the gate and the diffusion region serving as the source or drain is obtained. 7. A method for measuring an overlap length of a MOSFET, comprising: a seventh process for obtaining an overlap length LSD which is a length in the gate length direction in the overlap region. 8. A plurality of MOSFEs having different gate lengths formed in a surface portion of a semiconductor substrate or in a well of the surface portion.
Measuring means for applying a DC bias voltage Vg and an AC voltage between a gate, a source, and a drain, and changing the DC bias voltage Vg as a gate voltage to measure a current flowing between the gate, the source, and the drain; A first process of obtaining a plurality of Cgc-Vg characteristics indicating a relationship between a gate-source-drain capacitance Cgc and a gate voltage Vg based on a measurement result of the measurement unit; and a gate length in the plurality of Cgc-Vg characteristics. The value Vx of the gate voltage Vg at which the dependence on Lg appears is determined, and
a second process for obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the gc-Vg characteristic, and a gate where the gate-source-drain capacitance Cgc is saturated in the plurality of Cgc-Vg characteristics By obtaining and plotting the gate-source-drain capacitance Cgc with respect to each gate length Lg at the voltage Vg, Cgc is obtained.
A third process for obtaining the -Lg characteristic, a fourth process for obtaining the fringe capacitance Cf from the Cgc axis intercept of the Cgc-Lg characteristic obtained by the third process, and Cgc = Cx in the Cgc-Lg characteristic. From the point of view, based on the fringe capacitance Cf, the overlap length ΔL which is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain, and the distance between the gate and the diffusion region in the overlap region And a processing unit for performing a fifth process for obtaining the formed overlap capacitance Cov. 9. The method according to claim 6, wherein the processing unit includes a gate-source-drain capacitance Cgc at any two gate lengths Lm and Ln (m ≠ n) in the plurality of Cgc-Vg characteristics, instead of the second processing. The gate voltage Vg at a ratio of the difference to the maximum value is defined as the gate voltage value Vx in which the dependence on the gate length Lg appears in the plurality of Cgc-Vg characteristics, and the Cg
9. The overlap length and overlap capacitance of the MOSFET according to claim 8, wherein a sixth process of obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the c-Vg characteristic is performed. measuring device. 10. The processing means differentiates a gate-source-drain capacitance Cgc with a gate voltage Vg in the plurality of Cgc-Vg characteristics obtained in the first processing, instead of the second processing. A seventh process for obtaining a plurality of ∂Cgc / ∂Vg-Vg characteristics indicating a relationship between Cgc / ∂Vg and a gate voltage Vg; and a plurality of ∂Cgc / ∂Vg-
The branch point of the Vg characteristic is determined to obtain the plurality of ΔCgc / ΔVg.
The value of the gate voltage Vg at which the dependency on the gate length Lg appears in the -Vg characteristic is Vx, and the Cgc-V
9. The measurement of the overlap length and the overlap capacitance of the MOSFET according to claim 8, wherein an eighth process of obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the g characteristic is performed. apparatus. 11. The processing means differentiates the gate-source-drain capacitance Cgc of the Cgc-Vg characteristic obtained in the first processing by a gate voltage Vg instead of the second processing, and performs the differentiation. Gate-source-drain capacitance C
gc is further differentiated by the gate length Lg, ∂ / ∂Lg (∂C
gc / ∂Vg) and gate voltage Vgｇ / ∂
Ninth processing for obtaining the Lg (∂Cgc / ∂Vg) -Vg characteristic, and obtaining the rising point of the ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic to obtain the gate length in the plurality of Cgc-Vg characteristics. The value of the gate voltage Vg at which dependency on Lg appears is Vx, and the gate-source-drain capacitance C at the gate voltage Vx is determined from the Cgc-Vg characteristic.
9. The apparatus for measuring the overlap length and the overlap capacitance of a MOSFET according to claim 8, wherein a tenth process for obtaining a value Cx of gc is performed. 12. The processing means differentiates the gate-source-drain capacitance Cgc of the Cgc-Vg characteristic obtained in the first processing by a gate voltage Vg, and performs the differentiation in place of the second processing. Gate-source-drain capacitance C
gc is further differentiated by the gate length Lg, ∂ / ∂Lg (∂C
gc / ∂Vg) and gate voltage Vgｇ / ∂
Ninth processing for obtaining Lg (ｇCgc / ∂Vg) -Vg characteristics; gate voltage value Vp at which a peak occurs in the ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristics;
/ ∂Lg (∂Cgc / ∂Vg) -Vg = Vp, where Vw is the half-value width and k is the constant (1.0 <k <1.5) in the Vg characteristic.
The gate voltage value Vx obtained as −k · Vw is defined as the gate voltage value Vx that exhibits a dependency on the gate length Lg in the plurality of Cgc-Vg characteristics, and the Cgc-Vg
9. The apparatus according to claim 8, wherein an eleventh process of obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the characteristics is performed. . 13. When measuring CV characteristics of a MOS capacitance pattern, an AC voltage and a DC bias voltage Vg are applied between a gate electrode of the MOS capacitance pattern and the substrate,
The current flowing between the gate electrode and the substrate of the OS capacitance pattern and the voltage applied between the gate electrode and the substrate are measured, and the gate length Lg formed in the surface portion of the semiconductor substrate or the well of the surface portion is measured. When measuring the gate-substrate capacitance CGSUB for a plurality of different MOSFETs, a DC bias voltage VSUB is applied to the substrate, and a DC bias voltage Vg, a DC bias voltage VSUB, and an AC voltage are applied between the gate, source, and drain. And changing the DC bias voltage VSUB to change the plurality of MOSFETs.
Measuring means for measuring a current flowing between the gate and the substrate, and a relationship between a DC bias voltage Vg applied between the gate electrode of the MOS capacitance pattern and the substrate and the capacitance C based on the measurement result of the measuring means. A first process of obtaining a CV characteristic shown in FIG. 1 and obtaining a flat band capacitance CFB per unit area of the gate electrode at a point where the DC bias voltage Vg becomes equal to the flat band voltage VFB from the CV characteristic; A plurality of MOSFETs having a constant overlap length LSD and a constant gate width and different gate lengths Lg formed in a surface portion of a substrate or a well of the surface portion.
The DC bias voltage VSUB is applied to the substrate, and the DC bias voltage VSUB is applied between the gate, source and drain.
g, the DC bias voltage VSUB and the AC voltage are applied, and the gate-substrate capacitance CGSUB is obtained based on the current flowing between the gate and the substrate at Vg = VSUB + VFB obtained when the DC bias voltage VSUB is changed. In the second process and simulation,
Third to find built-in potential Vbi between drains
And the gate-substrate capacitance CGSUB is changed to √ (Vbi−
VSUB) to obtain a regression line, and the intercept value of the CGSUB axis in the regression line is CFB · (Lg−2L).
SD) · W to determine the overlap length LSD which is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain.
And a processing means for performing the processing of (1) and (2). 14. When measuring CV characteristics of a MOS capacitance pattern, an AC voltage and a DC bias voltage Vg are applied between a gate electrode of the MOS capacitance pattern on the diffusion layer and the diffusion layer.
To measure the current flowing between the gate electrode and the diffusion layer of the MOS capacitor pattern and the voltage applied between the gate electrode and the diffusion layer. When measuring the gate-source-drain capacitance Cgc for a plurality of MOSFETs having different gate lengths Lg, a DC bias voltage Vg and an AC voltage are applied between the gate-source-drain, and the DC bias as a gate voltage is applied. Measuring means for measuring the current flowing between the gate, source and drain by changing the voltage Vg or the DC bias voltage VSUB applied to the substrate;
A CV characteristic indicating a relationship between the capacitance C and a DC bias voltage Vg applied between the gate electrode and the diffusion layer of the capacitance pattern is obtained. From the CV characteristic, the DC bias voltage Vg becomes equal to the flat band voltage VFB. Flat band capacitance CF per unit area of gate electrode at a point
A first process for obtaining B ', and an overlap length LSD formed in a surface portion of the semiconductor substrate or a well in the surface portion.
And a DC bias voltage Vg and an AC voltage are applied between the gate, source, and drain for a plurality of MOSFETs having a constant gate width W and different gate lengths Lg,
When the DC bias voltage Vg as the gate voltage is changed, the gate-source current is measured based on the current flowing between the gate-source-drain measured by the measurement means.
A second process of obtaining a plurality of Cgc-Vg characteristics indicating a relationship between the drain-to-drain capacitance Cgc and the gate voltage Vg; and a second process of obtaining a plurality of Cgc-Vg characteristics at the gate voltage Vg at which the gate-source-drain capacitance Cgc is saturated in the plurality of Cgc-Vg characteristics. Gate-source-drain capacitance C for each gate length Lg
a third process for obtaining Cgc-Lg characteristics by obtaining and plotting gc; and Cgc of the Cgc-Lg characteristics.
Fourth processing for obtaining the gate fringe capacitance CFL on one side from the axis intercept, and changing the gate voltage Vg to Vg = while changing the DC bias voltage VSUB applied to the MOSFET substrate.
A fifth process for measuring the gate-source-drain capacitance CGSD at 0, a sixth process for obtaining a built-in potential Vbi between the substrate, source and drain by simulation, and a process for calculating the gate-source-drain capacitance CGSD as √ CGSD plotted against (Vbi-VSUB)
-√ (Vbi-VSUB) characteristic is obtained, and the CGSD-√ (Vbi-
Since the minimum value of the gate-source-drain capacitance CGSD in the (VSUB) characteristic is CFB ′ · LSD · W + 2CFL, the length which is the length in the gate length direction in the overlap region between the gate and the diffusion region serving as the source or drain is over. And a processing unit for performing a seventh process for obtaining the lap length LSD. 15. A plurality of MOSFs having different gate lengths formed in a surface portion of a semiconductor substrate or a well of the surface portion.
For ET, a DC bias voltage Vg and an AC voltage are applied between the gate and the source and the drain, and the DC bias voltage Vg as the gate voltage is changed to measure a current flowing between the gate and the source and the drain. A first process for obtaining a plurality of Cgc-Vg characteristics indicating a relationship between a gate-source-drain capacitance Cgc and a gate voltage Vg based on the above, and a dependency on a gate length Lg appears in the plurality of Cgc-Vg characteristics A second process of obtaining a value Vx of the gate voltage Vg and obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Cgc-Vg characteristic; A gate-source for each gate length Lg at a gate voltage Vg at which the source-drain capacitance Cgc is saturated; A third process of obtaining a Cgc-Lg characteristic by obtaining and plotting a capacitance Cgc between the drain and the drain; and a Cgc of the Cgc-Lg characteristic obtained by the third process.
A fourth process of obtaining a fringe capacitance Cf from an axis intercept; and a gate length in an overlap region between a gate and a diffusion region serving as a source or a drain based on the fringe capacitance Cf from the point where Cgc = Cx in the Cgc-Lg characteristic. A fifth process of obtaining an overlap length ΔL that is a length in the direction and an overlap capacitance Cov formed between the gate and the diffusion region in the overlap region. A computer-readable recording medium on which a program for causing a computer to execute the lap length / overlap capacity measuring method is recorded. 16. In place of the second processing, any two gate lengths L in the plurality of Cgc-Vg characteristics
The difference between the gate-source-drain capacitances Cgc at m, Ln (m ≠ n) is calculated, and the value of the gate voltage Vg at a ratio of the difference to a maximum value is calculated as the plurality of Cg.
a sixth process of obtaining a gate voltage value Vx at which dependence on the gate length Lg appears in the c-Vg characteristic, and calculating a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Cgc-Vg characteristic; 2. The MOSFE according to claim 1, wherein:
A computer-readable recording medium on which a program for causing a computer to execute the overlap length / overlap capacity measurement method of T is recorded. 17. Instead of the second process, in the plurality of Cgc-Vg characteristics obtained in the first process, a gate-source-drain capacitance Cgc is differentiated by a gate voltage Vg, and is expressed as {Cgc / ∂Vg}. A seventh process of obtaining a plurality of ∂Cgc / ∂Vg-Vg characteristics indicating a relationship with a gate voltage Vg; and obtaining a branch point of the plurality of ∂Cgc / ∂Vg-Vg characteristics to obtain the plurality of ∂Cgc / ∂. The value of the gate voltage Vg at which the dependence on the gate length Lg appears in the Vg-Vg characteristic is Vx, and the value Cgc of the gate-source-drain capacitance Cgc at the gate voltage Vx is obtained from the Cgc-Vg characteristic.
8. An MOSFE according to claim 1, further comprising: an eighth process for obtaining x.
A computer-readable recording medium on which a program for causing a computer to execute the overlap length / overlap capacity measurement method of T is recorded. 18. The gate-source-drain differential obtained by differentiating the gate-source-drain capacitance Cgc of the Cgc-Vg characteristic obtained in the first processing by the gate voltage Vg instead of the second processing. Further, the inter-capacitance Cgc is differentiated by the gate length Lg, and the relation between ∂ / ∂Lg (∂Cgc / ∂Vg) and the gate voltage Vg∂ / ∂Lg (∂Cgc /
A ninth process for determining the ∂Vg) -Vg characteristic; and determining a rising point of the ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic to determine the dependence of the plurality of Cgc-Vg characteristics on the gate length Lg. And a tenth process for determining the value of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Cgc-Vg characteristic, wherein the value of the appearing gate voltage Vg is Vx. Item 1. MOSFE according to item 1.
A computer-readable recording medium on which a program for causing a computer to execute the overlap length / overlap capacity measurement method of T is recorded. 19. The gate-source-drain capacitance obtained by differentiating the gate-source-drain capacitance Cgc of the Cgc-Vg characteristic obtained in the first processing by the gate voltage Vg instead of the second processing. Further, the inter-capacitance Cgc is differentiated by the gate length Lg, and the relation between ∂ / ∂Lg (∂Cgc / ∂Vg) and the gate voltage Vg∂ / ∂Lg (∂Cgc /
A ninth process for determining the ∂Vg) -Vg characteristic; a gate voltage value Vp at which a peak occurs in the ∂ / ∂Lg (∂Cgc / ∂Vg) -Vg characteristic;
g (∂Cgc / ∂Vg) -Vg
w, a constant k (1.0 <k <1.5), and Vx = Vp−k ·
The gate voltage value Vx obtained as Vw is calculated by the plurality of Cgc values.
An eleventh process of obtaining a gate voltage value Vx at which dependency on the gate length Lg appears in the -Vg characteristic, and obtaining a value Cx of the gate-source-drain capacitance Cgc at the gate voltage value Vx from the Cgc-Vg characteristic; 2. The MOSFE according to claim 1, wherein:
A computer-readable recording medium on which a program for causing a computer to execute the overlap length / overlap capacity measurement method of T is recorded. 20. A CV characteristic showing a relationship between a capacitance C and a DC bias voltage Vg applied between a gate electrode of a MOS capacitance pattern and a substrate is obtained, and the DC bias voltage Vg is flattened from the CV characteristic. A first process for obtaining a flat band capacitance CFB per unit area of a gate electrode at a point equal to the band voltage VFB; and an overlap length LSD and a gate formed in a surface portion of a semiconductor substrate or a well in the surface portion. A DC bias voltage VSUB is applied to the substrate for a plurality of MOSFETs having a constant width W and different gate lengths Lg, and
While applying the DC bias voltage Vg, the DC bias voltage VSUB and the AC voltage between the source and the drain, and changing the DC bias voltage VSUB, Vg = VSUB + VFB
A second process of measuring the gate-substrate capacitance CGSUB in the above, a third process of obtaining a built-in potential Vbi between the substrate-source / drain by simulation, and a process of calculating the gate-substrate capacitance CGSUB by − (Vbi−VSUB). And the intercept of the CGSUB axis in the regression line is CFB · (Lg−2LSD) · W, so that in the overlap region between the gate and the diffusion region serving as the source or drain. A fourth process for obtaining an overlap length LSD which is a length in the gate length direction; and a computer readable program recorded with a program for causing the computer to execute a MOSFET overlap length measurement method. recoding media. 21. A CV characteristic showing a relationship between a capacitance C and a DC bias voltage Vg applied between the gate electrode of the MOS capacitance pattern on the diffusion layer and the diffusion layer, and the DC bias is obtained from the CV characteristic. Voltage Vg is flat band voltage V
A first process for obtaining a diffusion band flat band capacitance CFB 'per unit area of the gate electrode at a point equal to FB, and an overlap length LSD formed in a surface portion of the semiconductor substrate or a well in the surface portion. For a plurality of MOSFETs having a constant gate width W and different gate lengths Lg, a DC bias voltage Vg and an AC voltage are applied between a gate, a source, and a drain to change the DC bias voltage Vg as a gate voltage. Gate-source
A second process of measuring a current flowing between the drains and obtaining a plurality of Cgc-Vg characteristics indicating a relationship between a gate-source-drain capacitance Cgc and a gate voltage Vg based on the measurement result; Gate-source
By obtaining and plotting the gate-source-drain capacitance Cgc with respect to each gate length Lg at the gate voltage Vg at which the drain-to-drain capacitance Cgc is saturated, Cgc-L
a third process for obtaining a g characteristic, a fourth process for obtaining a gate fringe capacitance CFL on one side from an intercept of a Cgc axis of the Cgc-Lg characteristic, and a DC bias voltage VSUB applied to a MOSFET substrate.
The fifth process of measuring the gate-source-drain capacitance CGSD when the gate voltage Vg is Vg = 0 while changing the gate voltage Vg, and the sixth process of obtaining the built-in potential Vbi between the substrate-source-drain by simulation, -Source-drain capacitance CGSD
(Vbi-VSUB) and plotting CGSD-√ (Vbi-VSUB)
−VSUB) characteristic, and the minimum value of the gate-source-drain capacitance CGSD in the CGSD-√ (Vbi-VSUB) characteristic is CFB ′ · LSD · W + 2CFL. And a seventh process for obtaining an overlap length LSD which is a length in the gate length direction in the overlap area of the MOSFET. A program for causing a computer to execute a method for measuring an overlap length of a MOSFET is recorded. A computer-readable recording medium.