JPH08298274A - Evaluation method of interface level density of semiconductor element in lateral distribution - Google Patents

Abstract

PURPOSE: To easily and accurately evaluating the interface level density of a semiconductor element in lateral distribution by a method wherein the capacity of a MOSFET is directly measured, and a distance from a gate edge is obtained. CONSTITUTION: A constant voltage is applied to a gate electrode 25 and a source 23 respectively, and a voltage applied to a drain 22 is changed to measure a capacity between the gate electrode 25 and a semiconductor substrate 21, and the interface level density of a semiconductor element in lateral distribution is measured basing on the capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to evaluation of lateral distribution of interface state density existing at an interface between a gate insulating film having a MOSFET structure and a semiconductor substrate.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, reference: "Measurement of La
tial Diffusion Profiles
forSubmicrometer MOSFET's
Katsuhiko KUBOTA et al.
Proc. IEEE 1991 Int. Confe
Rence on Microelectronic
Test Structures, Vol. 4, N
o. 1, March 1991. pp169-174 "
There was something shown in.

Conventionally, measurement in such a field has been performed by the charge pumping method, and as shown in FIG.
The SFET is composed of a semiconductor substrate 1, a drain 2, a source 3, a gate insulating film 4 and a gate electrode 5, and is used to measure the lateral distribution of the interface state density existing at the interface between the gate insulating film 4 of the MOSFET structure and the semiconductor substrate 1. To do. That is, the source 3 is connected to the ground using the pulse power supply 6 for applying the gate electrode, the pulse power supply 7 for applying the drain electrode, and the direct current ammeter 8 connected between the semiconductor substrate 1 and the ground.

FIG. 4 shows the timing when the pulse voltage is applied from the gate electrode applying pulse power source and the drain electrode applying pulse power source. As shown in FIG. 4A, in the gate electrode applying pulse power supply 6, the voltage V _a and the voltage V _i are set so that the channel region of the MOSFET alternately repeats the accumulation state (a) and the inversion state (b). Set and apply pulse voltage.

Therefore, in the n-channel MOSFET, V
The bias condition of _a <V _FB , V _i > V _t must be satisfied. Here, V _t is a threshold voltage and V _FB is a flat band voltage. For p-channel MOSFET, V _a >
The bias condition is V _t , V _i <V _FB , but hereinafter, all n-channel MOSFETs will be described. p
The same measurement can be performed on the channel MOSFETs by setting the bias conditions appropriately. At the same time, the drain electrode application pulse power supply 7 also applies the drain (pulse) voltage V _d in the accumulation state (V _a application) at the timing shown in FIG. 4B.

FIG. 5 is a diagram showing changes in the depletion layer in the vicinity of the drain in the accumulation state (V _a applied) and the inversion state (V _i applied). Here, 11 is a pn junction, 12 is a depletion layer edge, 13 is a hole, and 14 is an electron. In the accumulated state, as shown in FIG. 5A, the holes 13 reach the interface between the gate insulating film 4 and the semiconductor substrate 1 in the channel region, and further reach x _d in the drain 2.

In the inverted state, a channel is formed and the channel region is filled with electrons 14, as shown in FIG. Since the interface states existing at the interface between the gate insulating film 4 and the semiconductor substrate 1 can alternately capture the holes 13 and the electrons 14, the regions where both carriers reach alternately (from the channel to x _d (Region), a hole current corresponding to the interface state density flows in the semiconductor substrate 1.

Therefore, as shown in FIG. 3, the DC component of the substrate current is measured by the DC ammeter 8 to calculate the interface state density. This substrate current is generally called a charge pumping current. Next, the measurement of the lateral distribution of the interface state density will be described. In this measurement, the pulse voltage is applied at the timing shown in FIG. 4. At that time, the drain voltage V _d of the pulse electrode power supply 7 for applying the drain electrode is changed, and the charge pumping current is measured by the DC ammeter 8. By changing the drain voltage V _d, in response to the drain voltage V _d, the depletion layer width of the drain changes, from x _d (gate edge shown in FIG. 5 (a) to reach the position of the hole 13 The distance) also changes.

This change in x _d is calculated by a two-dimensional device simulation, and the relationship shown in FIG. 6 is obtained. In FIG. 6, the horizontal axis represents the drain voltage V _d (V), and the vertical axis represents the distance x from the gate edge to the arrival position of the holes 13.
_d (μm) is shown. FIG. 7 is a diagram showing the relationship between the charge pumping current and the drain (pulse) voltage V _d measured by the DC ammeter of FIG. In this figure,
The horizontal axis represents the drain voltage V _d (V), and the vertical axis represents the charge pumping current I _CP (A).

From the results of FIGS. 6 and 7, the lateral distribution of the interface state density can be calculated using the following equation. N _it (x _d ) = (1 / qfw) (dI _cp / dV _d ) / (dx _d / dV _d ) ... (1) where N _it (x _d ) is at the point of x _d Interface state density, q is elementary charge, f is pulse frequency, w is gate width,
I _cp is the charge pumping current, x _d is the distance from the gate edge, and V _d is the drain (pulse) voltage.

FIG. 8 shows the lateral distribution of the interface state density calculated using the equation (1). In this figure, the vertical axis represents the interface state density N _it (cm ⁻² ) and the horizontal axis represents the distance x _d (μm) from the gate edge.

[0012]

However, in the measuring method described above, a two-dimensional device simulator is required to obtain the relationship between x _d and V _d shown in FIG. Further, in order to perform this simulation with high accuracy, it is necessary to accurately know the two-dimensional profile of the dopant in the drain region, but it was very difficult to accurately obtain the dopant profile.

Further, when there are a lot of charges in the interface state or in the gate insulating film, x _d changes depending on the charge state, and it has been difficult to obtain x _d with high accuracy by simulation. The present invention eliminates the above-mentioned problems and directly implements MO
By obtaining the distance from the gate edge to the arrival position of the holes by measuring the capacitance of the SFET, the lateral distribution of the interface state density can be measured more simply and with high accuracy. It is intended to provide a method for evaluating a lateral distribution.

[0014]

In order to achieve the above object, the present invention provides: (1) In a method for evaluating the lateral distribution of the interface state density of a semiconductor device, the distance from the gate edge is measured by measuring the capacitance of the MOSFET. Based on the calculated distance and the charge pumping method.
And a step of calculating the interface state density of the FET.

(2) In the method for evaluating the lateral distribution of the interface state density of the semiconductor device described in (1) above, the MOS
In the capacitance measurement of the FET, a constant voltage is applied to the gate electrode and the source, and a voltage is changed and applied to the drain to measure the capacitance between the gate electrode and the semiconductor substrate. (3) In the method for evaluating the lateral distribution of the interface state density of the semiconductor device described in (2) above, the MOS described in (2) above is used.
In addition to the capacitance measurement of the FET, a constant voltage is applied to each of the gate electrode, the source and the drain, and the capacitance between the gate electrode and the drain is measured.

(4) In the method of evaluating the lateral distribution of the interface state density of the semiconductor device, the step of calculating the distance from the gate edge by the capacitance measurement of the MOSFET, and the charge pumping method based on the calculated distance. Is used to calculate the interface state density of the MOSFET and simultaneously calculate the lateral dopant distribution of the drain.

(5) In the method for evaluating the lateral distribution of the interface state density of the semiconductor device described in (4) above, the MOS
In the capacitance measurement of the FET, a constant voltage is applied to each of the drain and the source, a voltage is changed and applied to the gate electrode, and the capacitance between the gate electrode and the drain is sequentially measured. (6) In the method for evaluating the lateral distribution of the interface state density of a semiconductor device described in (4) above, the capacitance of the MOSFET is measured by applying a constant voltage to the drain and the source and changing the voltage to the gate electrode. The voltage is applied and the capacitance between the gate electrode and the semiconductor substrate is sequentially measured.

(7) In the evaluation method of the lateral distribution of the interface state density of the semiconductor device as described in (6) above, the above (6)
In addition to the capacitance measurement of the described MOSFET, a gate electrode,
A constant voltage is applied to the drain and the source, respectively, and the capacitance between the gate electrode and the drain is measured.

[0019]

[Action]

(1) According to the method for evaluating the lateral distribution of the interface state density of the semiconductor element according to claim 1, the step of calculating the distance x _d from the gate edge by measuring the capacitance of the MOSFET, and the step of calculating the distance x _d Since the step of calculating the interface state density of the MOSFET by the charge pumping method is performed, it is not necessary to obtain the distance x _d from the gate edge using a two-dimensional device simulator as in the conventional case, and By a simple method that does not require an accurate two-dimensional dopant profile for performing this device simulation with high precision, MO
The interface state density of the SFET can be calculated and the semiconductor device can be evaluated.

(2) According to the method for evaluating the lateral distribution of the interface state density of the semiconductor device according to the second aspect, it is not necessary to obtain the distance x _d from the troublesome gate edge by the two-dimensional device simulation, Since x _d can be obtained with high accuracy, the lateral distribution of the interface state density can be measured more accurately. (3) According to the method for evaluating the lateral distribution of the interface state density of the semiconductor device according to claim 3, in addition to (2) above, it is not necessary to obtain the gate length with high accuracy, and a simple circuit configuration is provided. M
The semiconductor element can be evaluated by calculating the interface state density of the OSFET.

(4) According to the method for evaluating the lateral distribution of the interface state density of the semiconductor device according to claim 4, the MOSFET is
Calculating the distance x _d from the gate edge by measuring the capacitance of the MOSFET, and calculating the interface state density of the MOSFET by the charge pumping method based on the calculated distance and determining the lateral dopant distribution of the drain. It can be calculated at the same time.

(5) According to the method for evaluating the lateral distribution of the interface state density of the semiconductor device according to the fifth aspect, a constant voltage is applied to the drain and the source, and a voltage is applied to the gate electrode while changing the voltage. The capacitance between the gate electrode and the drain is sequentially measured. Therefore, it is not necessary to calculate the distance x _d from the gate edge by a two-dimensional device simulation, and the interface state density of the MOSFET can be easily calculated by measuring the capacitance between the gate electrode and the drain due to the voltage change of only the gate electrode. At the same time, the lateral dopant distribution of the drain can be calculated at the same time.

(6) According to the method for evaluating the lateral distribution of the interface state density of the semiconductor device according to the sixth aspect, a constant voltage is applied to the drain and the source, and a voltage is applied to the gate electrode while changing the voltage. The capacitance between the gate electrode and the semiconductor substrate is sequentially measured. Therefore, it is not necessary to calculate the distance x _d from the gate edge by a two-dimensional device simulation, and the capacitance between the gate electrode and the semiconductor substrate can be easily measured by the voltage change of only the gate electrode.
It is possible to calculate the interface state density of T and simultaneously calculate the lateral dopant distribution of the drain.

(7) According to the method for evaluating the lateral distribution of the interface state density of the semiconductor device according to the seventh aspect, in addition to the above (6), it is not necessary to obtain the gate length with high accuracy, and a simple circuit is provided. With the configuration, the interface state density of the MOSFET and the lateral dopant distribution of the drain can be calculated.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a diagram showing a semiconductor device evaluation apparatus according to a first embodiment of the present invention. In this figure, MOSF
ET is a semiconductor substrate 21, a drain 22, a source 23,
The gate insulating film 24 and the gate electrode 25 are formed.
The lateral distribution measurement of the interface state density existing at the interface between the gate insulating film 24 of the SFET structure and the semiconductor substrate 21 is performed. That is, the semiconductor substrate 21 and the source 2 have a DC power supply 26 for applying a gate electrode and a DC power supply 27 for applying a drain electrode.
3 is connected to the ground, and the DC power supply 26 for applying the gate electrode
A capacitance meter 28 is connected between one end of the and the ground.

That is, the two DC power supplies 26 and 27 are connected to the gate electrode 25 and the drain 22, respectively, and the capacitance meter 28 is connected between the gate electrode 25 and the semiconductor substrate 21. In this figure, the source 23 is connected to the semiconductor substrate 21 for simplification, but it does not need to be grounded in particular, and may have an arbitrary constant potential. In addition,
Although not shown in FIG. 1, the measurement value of the capacitance meter 28, which is common to each embodiment, is input to a microprocessor (data logger) for processing, and a distance x from a gate edge shown below is obtained. _d can be calculated. Further, similar calculation processing can be performed for calculation of the interface state density of the MOSFET and calculation of the lateral dopant distribution of the drain.

As for the voltage application condition, V _a shown in FIG. 4 is applied from the gate electrode application DC power supply 26 to the gate electrode 25, and similarly V _d is applied from the drain electrode application DC power supply 27 to the drain 22. . By measuring the gate-substrate capacitance at that time with the capacitance meter 28, the relationship between the gate-substrate capacitance and the drain voltage V _d shown in FIG. 2 can be obtained. In this case, V _a is a constant voltage and V _d is sequentially changed to measure the gate-substrate capacitance. From the measurement result of FIG. 2, x _d is calculated using the following formula.

X _d = [T _OX / (ε _o ε _ox w)] [C _gb (0) −C _gb (V _d )] + x _d0 (2) where C _gb is the gate-substrate capacitance, ε _ox is the relative permittivity of the gate insulating film, ε _o is the vacuum permittivity, w is the gate width, T
_OX is the gate insulating film, and x _d0 is the distance from the gate edge to the arrival of holes in the drain 22 when the drain voltage is 0V.

MOSFET manufactured by a normal manufacturing process
Since the two-dimensional dopant profile shapes of the drain 22 and the source 23 and the charge distribution of the gate insulating film 24 near the drain 22 and the source 23 are almost equal, x _d and x _S are equal if the drain voltage and the source voltage are the same. Become. Here, x _S is the distance from the gate edge to the arrival of holes in the source 23. In FIG. 1, since the source 23 is connected to the ground, 0 V is applied to the drain electrode application DC power supply 27, and when the gate-substrate capacitance is measured, x _d0 can be calculated by the following equation. .

X _d0 = (1/2) [L- [T _OX / (ε _ox ε _o w)] [C _gb (0) -C _p ]] (3) where C _p is a wiring and a pad And the floating capacitance of the semiconductor substrate 21, and L is the gate length. Therefore, the relationship between x _d and V _d as shown in FIG. 6 can be obtained from the results shown in FIG. 2 by using the above equations (2) and (3).

The charge pumping measurement is performed by using the conventional method as described above, and the lateral distribution of the interface state density is obtained by the equation (1). In the first embodiment, the accuracy of x _d obtained from the capacitance measurement strongly depends on the accuracy of measuring the gate length L. In particular, when the overlap region between the gate electrode 25 and the drain 22 or the overlap region between the gate electrode 25 and the source 23 is much shorter than the gate length L, it is necessary to measure the gate length L extremely accurately.
It was quite difficult to measure. Therefore, a method for calculating x _d without measuring the gate length L will be described below.

FIG. 9 is a diagram showing a semiconductor device evaluation apparatus according to the second embodiment of the present invention. In this embodiment, the connection is the same as that of the first embodiment except that the capacitance meter 28 is connected to the gate electrode 25 and the drain 22. As the voltage application conditions, V _a shown in FIG. 4 is applied to the gate electrode applying DC power supply 26, and similarly V _d is applied to the drain electrode applying DC power supply 27. When V _d is applied so that the depletion layer between the drain 22 and the semiconductor substrate 21 becomes narrow, for example, when V _d is 0 V, the capacitance is approximated by the following equation.

[0033] C _gd (0) = _{[(ε o ε ox wx d0)} / T OX ] + C _fr ... (4) where, C _gd is a gate-to-drain capacitance, x _d0 V _d at the drain 22 is 0V At this time, the distance from the gate edge to the arrival of holes, C _fr is the fringing capacitance between the gate electrode 25 and the drain 22. Therefore,
From the above equations (2) and (4), x _d = [T _OX / (ε _ox ε _ow )] [[C _gb (0) -C _gb (V _d ) + C _gd (0) -C _fr )] (5), x _d can be obtained with high accuracy without measuring the gate length L.

A method capable of simultaneously measuring the lateral distribution of the interface state density and the lateral distribution of the drain dopant density will be described below. FIG. 10 is a diagram showing a semiconductor device evaluation apparatus showing a third embodiment of the present invention. The power supply connection of this embodiment is the same as that of the second embodiment. However,
In this case, the drain voltage V _d is a constant voltage (for example, 0
V), the gate voltage V _a is sequentially changed, and the gate-drain capacitance is measured. It is desirable to set V _d so that the depletion layer between the drain and the substrate is as narrow as possible. If possible, the semiconductor substrate 21 is forward biased.

FIG. 11 shows the relationship between the gate-drain capacitance and the gate voltage obtained in the third embodiment. In the figure, the gate voltage where the capacitance is rapidly increasing corresponds to the threshold voltage. The capacitance in the voltage region lower than this threshold voltage is approximated by the following equation. From C _gd (V _a) = _{[(ε o ε ox wx d)} / T OX ] + C _fr ... (6) the above equation, x _d when the gate voltage V _a can be calculated.

The charge pumping measurement is performed with the device configuration and connection shown in FIG. However, the pulse voltage application condition is different from that of the conventional method, and therefore will be described below with reference to FIG. Here, V _i applied to the DC power supply for applying the gate electrode is a fixed voltage, but V _a is sequentially changed and the charge pumping current is measured directly by the ammeter 8 (see FIG. 3). V _d applied to the DC power supply for applying the drain electrode at that time needs to match the drain voltage V _d applied in the capacitance measurement shown in FIG. 11.

From the capacitance measurement result of FIG. 11 and the charge pumping current measurement result of FIG. 12, the lateral distribution of the interface state density can be calculated using the following equation. N _it (x _d ) = (1 / qfw) (dI _cp / dV _a ) / (dx _d / dV _a ) ... (7) The lateral distribution of the dopant of the drain 22 is the capacitance measurement of FIG. It is calculated by the following formula based on the result.

V _a = V _FB −2φ _F − [2ε _o ε _si qN (2φ _F + V _d )] ^1/2 / C _ox (8) Here, V _FB is a flat band voltage and φ _F is a Fermi potential. , Ε _si is the relative dielectric constant of the semiconductor, and N is the dopant density. FIG. 13 shows a lateral dopant profile of the drain analyzed by using the above equation (8).

FIG. 14 is a diagram showing a semiconductor device evaluation apparatus according to the fourth embodiment of the present invention. The power supply connection of this embodiment is the same as that of the first embodiment. However, in this case, the drain voltage V _d is a constant voltage, for example, 0 V, and the gate voltage V _a is sequentially changed to measure the gate-substrate capacitance. FIG. 15 shows the relationship between the gate-substrate capacitance and the gate voltage obtained in the fourth embodiment.

This capacity is approximated by the following equation. C _gb (V _a ) = [(ε _o ε _ox w) / T _OX ] (L−x _d −x _S ) + C _p (9) Here, x _S is the source 23, and holes from the gate edge. The distance to reach, C _p, is the stray capacitance between the wiring and pad and the substrate.

From the above equation, x _d at the gate voltage V _a can be calculated. The charge pumping measurement and the method for calculating the lateral distribution of the interface state density and the lateral distribution of the dopant density of the drain are the same as those in the third embodiment of the present invention. In the fourth embodiment of the present invention, the accuracy of x _d obtained from the capacitance measurement depends on the accuracy of measuring the gate length L. Therefore, by combining the fourth embodiment with the second embodiment, x _d can be obtained with high accuracy without measuring the gate length L. After calculating x _d using the device configuration and the applied voltage method shown in the second embodiment, the lateral distribution of the interface state density and the lateral distribution of the drain dopant density are calculated according to the fourth embodiment.

The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0043]

As described in detail above, according to the present invention, the following effects can be achieved. (1) According to the invention of claim 1, the step of calculating the distance from the gate edge by measuring the capacitance of the MOSFET, and the step of calculating the interface state density of the MOSFET by the charge pumping method based on this distance. Since it is necessary to determine the distance from the gate edge by using a two-dimensional device simulator as in the conventional method, the accurate two-dimensional profile of the dopant for performing the device simulation with high accuracy is eliminated. A simple method that does not require
The interface state density of the FET can be calculated and the semiconductor element can be evaluated.

(2) According to the second aspect of the invention, since it is not necessary to obtain the distance x _d from the gate edge which is troublesome by the two-dimensional device simulation, the distance x _d can be obtained with high accuracy. The lateral distribution of the interface state density can be measured more accurately. (3) According to the invention described in claim 3, in addition to the above (2), it is not necessary to obtain the gate length with high accuracy, and the interface state density of the MOSFET is calculated with a simple circuit configuration, An evaluation can be done.

(4) According to the invention described in claim 4, MO
Calculating the distance from the gate edge by measuring the capacitance of the SFET, and calculating the interface state density of the MOSFET by the charge pumping method based on this distance, and simultaneously calculating the lateral dopant distribution of the drain. can do. (5) According to the invention described in claim 5, a constant voltage is applied to each of the drain and the source, a voltage is changed and applied to the gate electrode, and the capacitance between the gate electrode and the drain is sequentially measured.

Therefore, it is not necessary to obtain the distance from the gate edge by the two-dimensional device simulation, and the interface state density of the MOSFET can be easily calculated by measuring the capacitance between the gate electrode and the drain due to the voltage change of only the gate electrode. In addition, the lateral dopant distribution of the drain can be calculated at the same time. (6) According to the invention of claim 6, a constant voltage is applied to each of the drain and the source, the voltage is applied to the gate electrode while changing the voltage, and the capacitance between the gate electrode and the semiconductor substrate is sequentially measured.

Therefore, it is not necessary to obtain a troublesome distance from the gate edge by a two-dimensional device simulation, and the interface state density of the MOSFET can be easily determined by measuring the capacitance between the gate electrode and the semiconductor substrate due to the voltage change of only the gate electrode. In addition to the calculation, the lateral dopant distribution of the drain can be calculated at the same time. (7) According to the invention of claim 7, in addition to the above (6), it is not necessary to obtain the gate length with high accuracy, and the interface state density of the MOSFET and the dopant in the lateral direction of the drain are obtained with a simple circuit configuration. The distribution can be calculated.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor device evaluation apparatus according to a first embodiment of the present invention.

FIG. 2 is a drain voltage and gate-substrate capacitance characteristic diagram of the semiconductor device showing the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a conventional semiconductor device charge pumping method.

FIG. 4 is a timing chart when a pulse voltage is applied in a conventional semiconductor device charge pumping method.

FIG. 5 is a diagram showing changes in the depletion layer near the drain when a pulse voltage is applied.

FIG. 6 is a diagram showing a relationship between a distance from a gate edge to a hole arrival position and a drain voltage.

FIG. 7 is a diagram showing a relationship between a charge pumping current and a drain voltage.

FIG. 8 is a diagram showing a lateral profile of interface state density.

FIG. 9 is a diagram showing a semiconductor device evaluation apparatus according to a second embodiment of the present invention.

FIG. 10 is a diagram showing a semiconductor device evaluation apparatus showing a third embodiment of the present invention.

FIG. 11 is a diagram showing a capacitance measurement result according to a third embodiment of the present invention.

FIG. 12 is a diagram showing measurement results of charge pumping according to the third embodiment of the present invention.

FIG. 13 is a diagram showing a lateral dopant profile of a drain region calculated from a capacitance measurement result according to a third example of the present invention.

FIG. 14 is a diagram showing a semiconductor device evaluation apparatus according to a fourth embodiment of the present invention.

FIG. 15 is a diagram showing a capacitance measurement result according to a fourth example of the present invention.

[Explanation of symbols]

 21 Semiconductor Substrate 22 Drain 23 Source 24 Gate Insulating Film 25 Gate Electrode 26 Gate Electrode Applying DC Power Supply 27 Drain Electrode Applying DC Power Supply 28 Capacitance Meter

Claims (7)

[Claims] 1. A method of evaluating a lateral distribution of an interface state density of a semiconductor device, the method comprising: (a) calculating a distance from a gate edge by measuring a capacitance of a MOSFET;
(B) A step of calculating the interface state density of the MOSFET by a charge pumping method based on the calculated distance, and a method for evaluating the lateral distribution of the interface state density of a semiconductor device. 2. The method for evaluating the lateral distribution of interface state density of a semiconductor device according to claim 1, wherein the MOSFET is
The capacitance measurement is performed by applying a constant voltage to the gate electrode and the source, respectively, and changing the voltage to the drain to measure the capacitance between the gate electrode and the semiconductor substrate. Evaluation method of lateral density distribution. 3. The method according to claim 2, wherein the lateral distribution of the interface state density of the semiconductor device is evaluated.
In addition to the capacitance measurement of the OSFET, a constant voltage is applied to each of the gate electrode, the source and the drain to measure the capacitance between the gate electrode and the drain, thereby measuring the lateral distribution of the interface state density of the semiconductor device. Evaluation methods. 4. A method of evaluating a lateral distribution of an interface state density of a semiconductor device, the method comprising: (a) calculating a distance from a gate edge by measuring a capacitance of a MOSFET;
(B) An interface state density of the MOSFET is calculated by a charge pumping method based on the calculated distance, and a lateral dopant distribution of the drain is simultaneously calculated. Evaluation method of lateral density distribution. 5. The method according to claim 4, wherein the lateral distribution of the interface state density of the semiconductor device is evaluated.
The capacitance of the semiconductor device is characterized in that a constant voltage is applied to the drain and the source, a voltage is applied to the gate electrode while changing the voltage, and the capacitance between the gate electrode and the drain is sequentially measured. Evaluation method of lateral distribution of. 6. The method for evaluating lateral distribution of interface state density of a semiconductor device according to claim 4, wherein the MOSFET is
The capacitance of the semiconductor device is characterized in that a constant voltage is applied to the drain and the source, a voltage is changed and applied to the gate electrode, and the capacitance between the gate electrode and the semiconductor substrate is sequentially measured. Evaluation method of lateral density distribution. 7. The method for evaluating lateral distribution of interface state density of a semiconductor device according to claim 6, wherein M according to claim 6 is used.
In addition to the capacitance measurement of the OSFET, a constant voltage is applied to each of the gate electrode, the drain, and the source to measure the capacitance between the gate electrode and the drain. Evaluation methods.