JPS6341040A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To scale down a capacitance measuring device while obtaining the precise value of trench capacitance by mounting first-third transistors turned ON under a first state and turned OFF under a second state and fourth and fifth transistors turned OFF under the first state and turned ON under the second state. CONSTITUTION:Transistors Q1-Q3 are turned ON under a first state, a contact 1 is pre-charged at Vcc, and contacts 2, 3 are discharged. When the states are shifted to a second state from the first state, the transistors Q1-Q3 are turned OFF, transistors Q4, Q5 are turned ON, and charges are also stored in a capacitor Cs2 and the contacts 2, 3. The contacts 1-3 are brought to the same potential Vss at that time, and the quantity of charges at all the contacts is kept at Q. Contact capacitance C1.C2.C3 can be calculated from the depletion layer width of a diffusion layer and a dielectric constant and an area on a pattern and gate capacitance, and potential Vss at the contacts 1, 2, 3 can be acquired from the relationship of the input Vss and output VR of an inverter 4 by measuring the output potential VR of the inverter 4 at a time when the contact 3 is used as an input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device, and in particular to a memory device, etc., which has a groove-type capacitor as a capacitor in its memory cell,
The present invention relates to a semiconductor integrated circuit device that facilitates the measurement of its capacitance value.

[Conventional technology]

Conventional semiconductor integrated circuit devices, for measuring trench capacitance,
As shown in FIG. 4, there are a plurality of groove capacities 43 to 4 to be measured.
A pad 42 for connecting 6 to the outside in parallel is prepared, and a capacitance measuring device 41 is prepared externally, electrically connected to the pad 42, the capacitance is measured, and the groove capacitance is determined. The capacity value for each piece was calculated from the number of pieces.

The capacitance measuring device 41 is composed of a capacitance bridge and measures the impedance Z with respect to an alternating current signal of fD and frequency ω. If the capacitance value and number of groove capacitors are Cs and N, then the relationship Z=1/(N・ωCs)1)
Cs is required.

[Problem that the invention seeks to solve]

In the conventional semiconductor integrated circuit device described above, the capacitance measurement device is large-scale, and the parasitic capacitance from the pad to the input of the capacitance measurement device is so large that it cannot be ignored. In addition, there is a disadvantage that the impedance measurement has to be carried out in a frequency dependent manner, resulting in a lack of measurement accuracy.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor integrated circuit device that can reduce the size of a capacitance measuring device and can determine an accurate value of trench capacitance.

[Means for solving problems]

The semiconductor integrated circuit device of the present invention includes a first capacitor consisting of a trench capacitor whose capacitance value is unknown, a second capacitor whose capacitance value is equal to or known as the capacitance value of the first capacitor, and a first capacitor whose capacitance value is equal to or known to the first capacitor. comprising first to third transistors that are turned on in the first state and turned off in the second state, fourth and fifth transistors that are turned off in the first state and turned on in the second state, and an inverter; One electrode of each of the first and second capacitors is commonly connected to either a power supply terminal or a ground terminal, and the other electrode is connected to all first and second contacts, respectively, and the first and second capacitors are connected to each other. The first transistor
A second contact is connected between the power supply terminal, the ground terminal, or one of the ground terminal and the power supply terminal, and the third transistor is connected between the third contact and the ground terminal. the fourth transistor is connected between the first and second contacts, and the fifth transistor is connected between either one of the first and second contacts and the third contact. and the third contact is connected to the input end of the inverter.

[Effect]

In the first state, one of the first and second capacitors and the contact to which this capacitor is connected are precharged with the power supply voltage, and the other capacitor, the contact to which this capacitor is connected, and the third contact are precharged with the power supply voltage. Discharged.

In the second state, the first to third points of contact are in the same position)
, it is also galvanically disconnected from the power supply electrode and the ground electrode. As a result, the charge precharged in the first state is stored and distributed to the first and second capacitors and the first to third contact capacitors.

The potential of the drop to third contact in the second state is determined from the output potential of the inverter, and the known power supply voltage and the first to
The capacitance value of the first and second capacitors having the same capacitance value can be calculated from the contact capacitance of the third contact point, and if the capacitance value of the second capacitor is known, the first capacitance value can be calculated. be able to.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor integrated circuit device of the present invention. The embodiment shown in FIG. 1 includes an N-channel transistor Q""'rQ', an inverter 4, and a capacitor C, ss a Csz. C81 and Csz have the same groove capacity, and the capacitance value C
Let us have s. φp and φB are input signals,
In the first state, φp is High above Vcc+VT.
Change in level. Here, VCC is a power supply voltage, and 7 transistors are transistors Q1 to QsO1, and threshold voltages.

In the above configuration, in the first state, transistors Ql to Q3 are turned on, contact 1 is precharged to Vcc, and contacts 2 and 3 are discharged.

The amount of accumulated charge Q at this time is expressed by the following equation.

Q=Vcc −(Cs +CI) ・−・・−(1
)C1: Contact capacitance of contact 1 By shifting from the first state to the second state, transistors Q1 to Q3 turn on, transistors Q4 and Qs turn on, and capacitance '1jlC82 and contacts 2 and 3 also turn on. Charge is accumulated. At this time, since the contacts 1 to 3 are at the same potential Vss and the amount of charge of all the contacts is stored in Q, the following equation holds true.

Q=Vss-(2Cs+Cx+C2+Cx) --(
2) C2/C3: From the contact capacitances (1) and (2) of contacts 2 and 3, Cs can be calculated using the following equation.

The specific permittivity can be calculated from the coefficient, area on the pattern, and gate capacitance.

The potential Vss of the contacts 1, 2, and 3 can be determined by measuring the output potential VR of the inverter 4 when the contact 3 is used as an input signal. You can find it by looking at the graph in the figure. The relationship between the time t after changing from the first state to the second state and VR is as shown in Figure 3. When t is large enough and VR reaches the 1,000-stop state, VR is the output potential. do.

In the embodiment shown in FIG. 1, the capacitors 1-Cs1 and Csz may all be connected to the power supply terminal instead of the ground terminal, or the transistor Ql may be connected to the ground terminal and the transistor Q2 may be connected to the power supply terminal. , transistor Qs i contact 2
It may be connected to contact 1 instead.

As another example, it is also possible to configure one of the capacitances xcsl and Csz to be a planar capacitance with a known capacitance value, and to measure the capacitance value of the other groove capacitance.

〔Effect of the invention〕

As explained above, if the present invention is applied to a semiconductor integrated circuit device, it is sufficient to simply measure the output potential from the inverter, and there is an effect that a large-scale device for measuring capacitance, which has been conventionally used, is not required. In addition, since the output potential is measured via an inverter circuit without directly connecting the groove capacitor to an external device, there is no need to consider the load capacitance due to external connections. Frequency dependence was a problem because the capacitance value was obtained from the measurement of the impedance using K, but since this problem is eliminated, there is an effect that an accurate capacitance value can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
Input potential Vss and output potential VR of the inverter in the figure
FIG. 3 is a graph showing the relationship between the time t from the rise of the input potential Vss of the inverter and the output potential VB.
FIG. 4 is an explanatory diagram showing an example of a capacitance measuring method in a conventional semiconductor integrated circuit device. 1-3...Contact, 4-...Inverter,
C81・C5z-...Groove volume 1, Ql~Qs-...
...transistor. Vss:'~Minor: Good l2 ≦tshi>525a
入ノ'1I;U;1〒し手1TS2J

Claims (1)

[Claims] a first capacitor which is a groove capacitor with an unknown capacitance value, a second capacitor whose capacitance value is equal to or known to the capacitance value of said first capacitor, and which is turned on in a first state and in a second state; comprising first to third transistors that are turned off, fourth and fifth transistors that are turned off in the first state and turned on in the second state, and an inverter; One electrode of each is commonly connected to either the power supply terminal or the ground terminal, and the other electrode is connected to the first and second contacts, respectively, and the first and second transistors are connected to the first and second transistors. and the power supply terminal, the ground terminal, or either the ground terminal or the power supply terminal, and the third transistor is connected between the third contact and the ground terminal. , the fourth transistor is connected between the first and second contacts, and the fifth transistor is connected between either one of the first and second contacts and the third contact. . A semiconductor integrated circuit device, wherein the third contact is connected to an input end of the inverter.