JPS61187278A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce inductance while preventing the lowering of effective capacitance by forming a capacitor formed by an electrode pattern on one main surface and a metal on the other main surface shaped through a dielectric to a pellet containing a GaAs field-effect transistor. CONSTITUTION:Upper electrodes 1 on a main surface containing GaAs 3, back electrodes 2 and an interposing dielectric 4 are shaped. GaAs 3 it etched, and capacitances C1, C2 are formed. Since the back electrodes 2 are all connected to a grounding surface at the same potential at that time, wiring electrodes are unnecessitated, and there is hardly inductance intruding in series between the capacitances C1, C2. Accordingly, source inductance intruding in series can be ignored approximately, thus allowing a design only by the thickness of the dielectric and electrode width of effective capacitance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and more particularly to a GaAs field effect transistor and a GaAs IC having a capacitor used for phase matching or the like in the chip.

[Conventional technology]

An example of a conventional capacitor of this type is shown in Figure 2 (a).
), second diagram), two capacitors c consisting of a first electrode 12 and a second electrode 13 are formed on the main surface of the chip 15.
, , C4 are formed. Inductance L2. L3 exists.

Also, on the other side of the conventional capacitor of this type, the third
As shown in Figures (a) and 3(b), two capacitances C5 and C6 are formed on the main surface of the chip 25, consisting of the first electrode 22, the second electrode 23, and the dielectric 26 between them. be done.

Wiring electrode 2 that connects these two capacitances Cs and Co to each other
4 and a portion of the extraction electrode 21 that connects this electrode 14 to the ground plane, each has an inductance L5.
．． L exists.

[Problem that the invention seeks to solve]

The configuration of the conventional capacitor described above includes a capacitance C3°C4 (or a capacitance Cs, C5) K in series, an inductance L3. L
4 (or inductance L5, L6) are entered in series and then connected to ground. In fact, the effective capacity of capacity C3 is 1kCs', and the effective capacity of capacity C4 is C4
/ becomes as shown in the following formula.

Therefore, the effective capacitance C3/, C, / becomes small.

At the same time, since the effective capacitance changes depending on the size of the inductance, designing a large number of capacitors into the same chip becomes extremely complicated. Also, needless to say, wiring is required to connect to ground.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide a semiconductor device having a capacitor with small inductance and no reduction in effective capacitance.

[Means for solving problems]

The structure of the semiconductor device of the present invention is such that a pellet containing an sGaAs field effect transistor is provided with a capacitor formed of an electrode pattern on the main surface and a metal on the other main surface provided to this pattern via a dielectric. It is characterized by:

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIGS. 1(a) and 1(a) are a plan view and a sectional view taken along the line AA' of a semiconductor device according to an embodiment of the present invention.

In these figures, the chip includes an upper electrode 1 on the main surface containing GaAs 3, a back electrode 2, and a dielectric 4 therebetween. GaAs is etched,
This configuration forms capacitors C1 and C2. here,
Since the back electrodes 2 are all connected to the ground plane at the same potential, no wiring electrodes are required. Furthermore, since they are at the same potential, there is almost no inductance #1 that enters in series between the capacitor CI+02.

〔Effect of the invention〕

As explained above, according to the present invention, since the capacitor is formed between the back electrode and the front electrode by etching GaAs, the sheath inductance connected in series can be almost ignored, and the effective capacitance is equal to that of the dielectric material. It can be designed using only the thickness and electrode width, and has the advantage of eliminating the need for wiring.

[Brief explanation of drawings]

FIG. 1(a) is a plan view showing a semiconductor device according to an embodiment of the present invention, FIG. 1(b) is a cross-sectional view taken along line AA' in FIG. 1(a), Figure 2 (a) is a plan view showing an example of a conventional capacitor, and Figure 2 (9)) is B in Figure 2 (a).
3(a) is a plan view showing the other side of the conventional capacitor, and FIG. 3(Φ) is a cross-sectional view taken along line C-C/ of FIG. FIG. 2 is a cross-sectional view taken along a line. In the top view, 1, 12.22...first electrode, 2, 13.23-...second electrode, 3"-"
GaAs. 4, 26...dielectric, 15.25...
Chip, L2゜L3. L5. L6...Inductance s c,, C4*C,, C,...
capacity.

Claims (1)

[Claims] A semiconductor device characterized in that a pellet including a GaAs field effect transistor is provided with a capacitor formed of an electrode pattern on one main surface and a metal on the other main surface provided to this pattern via a dielectric.