JPH01205595A - Manufacture of ceramic multilayer wiring board - Google Patents
Manufacture of ceramic multilayer wiring boardInfo
- Publication number
- JPH01205595A JPH01205595A JP3036388A JP3036388A JPH01205595A JP H01205595 A JPH01205595 A JP H01205595A JP 3036388 A JP3036388 A JP 3036388A JP 3036388 A JP3036388 A JP 3036388A JP H01205595 A JPH01205595 A JP H01205595A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- laminate
- holes
- green sheet
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000919 ceramic Substances 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000007639 printing Methods 0.000 claims abstract description 8
- 238000010030 laminating Methods 0.000 claims abstract description 4
- 239000004020 conductor Substances 0.000 abstract description 25
- 238000003475 lamination Methods 0.000 abstract description 7
- 238000007650 screen-printing Methods 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はセラミック多層配線基板の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method of manufacturing a ceramic multilayer wiring board.
従来のセラミック多層配線基板製造時のセラミッククリ
ーンシー１への積層方法としては、セラミック多層配線
基板を暢成するクリーンシート１枚１枚に信号、もしく
は、電源供給用の貫通孔を形成し、この貫通孔に導体ベ
ース１〜を埋込み、スルーホールを形成し、導体パター
ニングが必要なものはり゛リーンシー１・表面に導体パ
ターンを形成して、最後にこのクリーンシート全部を積
層、熱圧着させる方法をとっていた。The conventional method for laminating ceramic multilayer wiring boards into a ceramic clean sheet 1 when manufacturing a ceramic multilayer wiring board is to form through holes for signal or power supply in each clean sheet that makes up the ceramic multilayer wiring board. Embed the conductor base 1~ in the through hole, form the through hole, form a conductor pattern on the surface of the clean sheet 1 for those that require conductor patterning, and finally laminate all of these clean sheets and bond them by thermocompression. I was taking it.
上述した従来のセラミック多層配線基板の製造方法は、
グリーンシートへの貫通孔形成１貫通孔への導体ペース
）・埋込みによるスルーホールの形成、クリーンシー１
〜表面への導体パターン印刷を行った後に積層、熱圧着
をしていたので、貫通孔形成２貫通孔埋込りによるスル
ーポールの形成、クリーンシート表面への導体パターン
印刷の各工程を経る間に、クリーンシートか伸ひてしま
い、積層、熱圧着の際の各層毎のスルーホールの位置ず
れか大きくなるという欠点かある。The conventional method for manufacturing the ceramic multilayer wiring board described above is as follows:
Through-hole formation in green sheet 1 Conductor paste to through-hole) ・Formation of through-hole by embedding, clean sheet 1
~ Since the conductor pattern was printed on the surface, it was laminated and thermocompression bonded, so the process of forming through holes, forming through poles by embedding through holes, and printing conductor patterns on the surface of the clean sheet. Another drawback is that the clean sheet stretches, which increases the misalignment of the through holes in each layer during lamination and thermocompression bonding.
本発明の目的は、各層毎のスルーホールの位置ずれの小
さいセラミック多層配線基板の製造方法を提供すること
にある。An object of the present invention is to provide a method of manufacturing a ceramic multilayer wiring board in which the positional deviation of through holes in each layer is small.
本発明は、クリーンシー１〜法によって形成されるセラ
ミック多層配線基板の製造方法に於て、り゛リーンシー
１〜を積層、熱圧着し複数のクリーンシー１へ積層体を
形成し、該クリーンシー１へ積層体のそれぞれに貫通孔
を設け該貫通孔へ導体ベース１へを埋込みスルーポール
を形成し、前記クリーンシー１〜積層体のそれぞれの表
面に導体パターンを印刷し、第１の積層体を形成する工
程と、前記第１の積層体を所定の構成に従って積層、熱
圧着し、第２の積層体を形成する工程とを含んでいる。The present invention is a method for manufacturing a ceramic multilayer wiring board formed by the clean sheets 1 to 1, in which the green sheets 1 to 1 are laminated and thermocompressed to form a laminate into a plurality of clean sheets 1. A through hole is provided in each of the laminates 1 to 1, a conductor base 1 is embedded in the through hole to form a through pole, a conductive pattern is printed on each surface of the clean sheet 1 to the laminate, and the first laminate is and a step of laminating the first laminate according to a predetermined configuration and thermocompression bonding to form a second laminate.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）−（ｆ）は本発明の一実施例を説明する工
程順に示した断面図である。FIGS. 1(a) to 1(f) are sectional views showing an embodiment of the present invention in the order of steps.
ます、第１図（ａ）に示すように、フレーｌ−法により
セラミッククリーンシー１〜］をキャステインクする。First, as shown in FIG. 1(a), ceramic clean sheets 1 to 1 are cast ink using the Frey method.
この時のクリーンシー１−厚を約１００μｍとする。The thickness of the clean sheet 1 at this time is about 100 μm.
次に、第１図（ｂ ）に示すように、このクリーンシー
１へ１を所定の大きさに切断しキャステインク方向か９
０度す一つずれる様に積層、熱圧着し、第１層２ａ、第
２層２ｂ、第３層２ｃのクリーンシー１へ積層体を形成
する。この時の積層枚数はその表面に印刷される導体パ
ターンの種類によって異なるか、表面に電源パターンを
印刷する時は４層、信号パターンを印刷する時はクリー
ンシー１への誘電率ε−７の時て２層とする。熱圧着の
際の圧力は積層するクリーンシー１への単位面積当り、
７０ ｋ ｇ ｆ ／ ｃｍ ２て温度７０°Ｃとする
。Next, as shown in FIG. 1(b), cut the clean sheet 1 into a predetermined size and place it in the direction of the cast ink.
They are laminated and thermocompressed so that they are shifted by 0 degrees, and a laminate is formed on the clean sheet 1 of the first layer 2a, second layer 2b, and third layer 2c. The number of layers to be laminated at this time varies depending on the type of conductor pattern printed on the surface.When printing a power pattern on the surface, it is 4 layers, and when printing a signal pattern, it is 4 layers, and when printing a signal pattern, it is 4 layers with a dielectric constant of ε-7 to clean sheet 1. There are two layers. The pressure during thermocompression bonding is per unit area of the clean sheet 1 to be laminated,
70 kg f/cm2 and temperature 70°C.
次に、第１図（Ｃ）に示すように、このクリーンシー１
〜積層体第１層２ａ、第２層２ｂ、第３層２ｃの層毎に
貫通孔３，４を形成する。この時、貫通孔３，４の径は
電源用の貫通孔３で２００μｍ、信号用の貫通孔４は１
００μｍとする。Next, as shown in FIG. 1(C), this clean sheet 1
~Through holes 3 and 4 are formed in each of the first layer 2a, second layer 2b, and third layer 2c of the laminate. At this time, the diameter of the through holes 3 and 4 is 200 μm for the power supply through hole 3, and 1 μm for the signal through hole 4.
00 μm.
次に、第１図（ｄ）に示すように、貫通孔３゜４に導体
ペースト５を埋込み、スルーホール１３゜１４を形成す
る。この時、導体ペーストか完全に貫通孔３．４に埋込
まれる様に、クリーンシート積層体の第１層２ａ、第２
層２ｂ、第３層２Ｃをチャッキングする。印刷後のテー
ブルには真空引きの機構を備え、貫通孔３，４埋込みの
際の導体ペースト５の埋込みを確実なものにしている。Next, as shown in FIG. 1(d), conductor paste 5 is filled in the through holes 3.degree. 4 to form through holes 13.degree. At this time, the first layer 2a and the second layer of the clean sheet laminate should be
Chuck the layer 2b and the third layer 2C. The table after printing is equipped with a vacuum mechanism to ensure that the conductive paste 5 is filled in when the through holes 3 and 4 are filled.
次に、第１図（ｅ）に示すように、グリーンシートの積
層体の第１層２ａ、第２層２ｂ、第３層２ｃの表面に導
体パターン６をスクリーン印刷法により形成する。導体
パターン６の線幅は電源パターンで約２００μｍ、信号
パターンで約１００μｍ、導体パターン６の厚さを約１
０μｍとする。Next, as shown in FIG. 1(e), a conductive pattern 6 is formed on the surfaces of the first layer 2a, second layer 2b, and third layer 2c of the green sheet laminate by screen printing. The line width of the conductor pattern 6 is approximately 200 μm for the power supply pattern, approximately 100 μm for the signal pattern, and the thickness of the conductor pattern 6 is approximately 1 μm.
It is set to 0 μm.
次に、第１図（ｆ＞に示すように、このり゛リーンシー
１ル積層体第１層２ａ、第２層２ｂ、第３層２Ｃを積層
、熱圧着し、第２の積層体７を形成する。この時の圧力
は、単位面積当り１４． Ｏｋ ｇ ｆ／ｃｍ２．温度
は１１０℃とする。Next, as shown in FIG. The pressure at this time is 14.0 kg f/cm2 per unit area and the temperature is 110°C.
このようにして得られた第２の積層体７から成るセラミ
ック多層配線基板全層での積層ずれは約２５μｍてあり
、クリーンシート１枚に、貫通孔形成、貫通孔への導体
ペース１〜埋込み、導体パターンの印刷、積層、熱圧着
を行った場合の位置すれ約５０μｍの１／２になる。The lamination misalignment in all the layers of the ceramic multilayer wiring board made of the second laminate 7 thus obtained is about 25 μm.On one clean sheet, through-holes are formed and conductor paste 1 is embedded in the through-holes. , the positional deviation is approximately 1/2 of 50 μm when the conductor pattern is printed, laminated, and thermocompressed.
なお、本実施例ては、導体層を３層とした場合の例であ
るか、導体がより多層化されても適用させることか可能
であり、セラミック多層配線基板の製造に利用てきる。Note that this embodiment is an example in which the number of conductor layers is three, or the present invention can be applied even if the conductor is multilayered, and can be used for manufacturing a ceramic multilayer wiring board.
以上説明したように本発明は、セラミック多層配線基板
を構成する各絶縁層第１層、第２Ｎ、第３層毎に積層工
程を施した後、貫通孔形成２貫通孔への導体ペスＩ−理
込みによるスルーホールの形成、導体パターンの印刷を
行い、第１の積層体とし、これを第２の積層工程で全層
積層させセラミック多層配線基板にすることにより、貫
通孔形成７貫通孔ｌ＼の導体ペース１〜埋込みによるス
ルーホールの形成、導体パターン印刷］二程でのクリー
ンシー１〜の伸ひを抑えることかてき、セラミック多層
配線基板にする時の積層ずれを小さくてきる効果がある
。As explained above, in the present invention, after performing a lamination process for each of the first, second, and third insulating layers constituting a ceramic multilayer wiring board, through-hole formation 2 conductor pins I- Through-holes are formed by drilling and a conductor pattern is printed to form a first laminate, which is then laminated in all layers in a second lamination process to form a ceramic multilayer wiring board. Formation of through-holes by embedding conductor paste 1 of ＼, printing of conductor pattern] It is possible to suppress the expansion of clean sheet 1 in step 2, and it has the effect of reducing lamination misalignment when making a ceramic multilayer wiring board. be.
第１図（ａ、 ）〜（ｆ）は本発明のセラミック多層配
線基板の一実施例を説明する工程順に示した断面図であ
る。
１・・セラミッククリーンシー１へ、２・・第１の積層
体、２ａ 第１層、２ ｂ−第２層、２Ｃ・第３層、３
，４・・貫通孔、５ ・導体ペースト、６・導体パター
ン、７・・・第２の積層体、８・セラミック多層配線基
板、１３，１．４ ・スルーポール。FIGS. 1(a, 1f) to 1(f) are sectional views showing an embodiment of the ceramic multilayer wiring board of the present invention in the order of steps. 1... To ceramic clean sheet 1, 2... First laminate, 2a first layer, 2 b-second layer, 2C third layer, 3
, 4... through hole, 5 - conductor paste, 6 - conductor pattern, 7... second laminate, 8 - ceramic multilayer wiring board, 13, 1.4 - through pole.
Claims (1)
線基板の製造方法に於て、グリーンシートを積層，熱圧
着し複数のグリーンシート積層体を形成し、該グリーン
シート積層体のそれぞれに貫通孔を設け該貫通孔へ導体
ペーストを埋込みスルーホールを形成し、前記グリーン
シート積層体のそれぞれの表面に導体パターンを印刷し
、第１の積層体を形成する工程と、前記第１の積層体を
所定の構成に従って積層，熱圧着し、第２の積層体を形
成する工程とを含むことを特徴とするセラミック多層配
線基板の製造方法。In a method for manufacturing a ceramic multilayer wiring board formed by the green sheet method, green sheets are laminated and thermocompressed to form a plurality of green sheet laminates, and a through hole is provided in each of the green sheet laminates. filling the holes with conductive paste to form through holes, printing a conductive pattern on each surface of the green sheet laminate to form a first laminate, and forming the first laminate according to a predetermined configuration. A method for manufacturing a ceramic multilayer wiring board, comprising the steps of laminating and thermocompression bonding to form a second laminate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63030363A JP2758603B2 (en) | 1988-02-12 | 1988-02-12 | Manufacturing method of ceramic multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63030363A JP2758603B2 (en) | 1988-02-12 | 1988-02-12 | Manufacturing method of ceramic multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01205595A true JPH01205595A (en) | 1989-08-17 |
| JP2758603B2 JP2758603B2 (en) | 1998-05-28 |
Family
ID=12301782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63030363A Expired - Lifetime JP2758603B2 (en) | 1988-02-12 | 1988-02-12 | Manufacturing method of ceramic multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2758603B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04144299A (en) * | 1990-10-05 | 1992-05-18 | Nec Corp | Through hole structure for ceramic multilayer interconnection board |
| US5323535A (en) * | 1991-02-25 | 1994-06-28 | Canon Kabushiki Kaisha | Electrical connecting member and method of manufacturing the same |
| US5379515A (en) * | 1989-12-11 | 1995-01-10 | Canon Kabushiki Kaisha | Process for preparing electrical connecting member |
| JP2006179956A (en) * | 2002-10-30 | 2006-07-06 | Kyocera Corp | Method of manufacturing capacitor |
| US7204900B1 (en) * | 2004-04-29 | 2007-04-17 | Northrop Grumman Corporation | Method of fabricating structures using low temperature cofired ceramics |
| US7318874B2 (en) * | 2001-03-20 | 2008-01-15 | Tesa Ag | Method for joining ceramic green bodies using a transfer tape and conversion of bonded green body into a ceramic body |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5720496A (en) * | 1980-07-11 | 1982-02-02 | Hitachi Ltd | Method and device for laminating green sheet |
| JPS58197796A (en) * | 1982-05-14 | 1983-11-17 | 株式会社日立製作所 | Method of producing ceramic board |
| JPS61229551A (en) * | 1985-04-04 | 1986-10-13 | 日立化成工業株式会社 | Manufacture of ceramic laminate |
-
1988
- 1988-02-12 JP JP63030363A patent/JP2758603B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5720496A (en) * | 1980-07-11 | 1982-02-02 | Hitachi Ltd | Method and device for laminating green sheet |
| JPS58197796A (en) * | 1982-05-14 | 1983-11-17 | 株式会社日立製作所 | Method of producing ceramic board |
| JPS61229551A (en) * | 1985-04-04 | 1986-10-13 | 日立化成工業株式会社 | Manufacture of ceramic laminate |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5379515A (en) * | 1989-12-11 | 1995-01-10 | Canon Kabushiki Kaisha | Process for preparing electrical connecting member |
| JPH04144299A (en) * | 1990-10-05 | 1992-05-18 | Nec Corp | Through hole structure for ceramic multilayer interconnection board |
| US5323535A (en) * | 1991-02-25 | 1994-06-28 | Canon Kabushiki Kaisha | Electrical connecting member and method of manufacturing the same |
| US7318874B2 (en) * | 2001-03-20 | 2008-01-15 | Tesa Ag | Method for joining ceramic green bodies using a transfer tape and conversion of bonded green body into a ceramic body |
| JP2006179956A (en) * | 2002-10-30 | 2006-07-06 | Kyocera Corp | Method of manufacturing capacitor |
| US7204900B1 (en) * | 2004-04-29 | 2007-04-17 | Northrop Grumman Corporation | Method of fabricating structures using low temperature cofired ceramics |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2758603B2 (en) | 1998-05-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |