JPH07147485A - Manufacture of laminated printed board - Google Patents

Manufacture of laminated printed board

Info

Publication number
JPH07147485A
JPH07147485A JP29299393A JP29299393A JPH07147485A JP H07147485 A JPH07147485 A JP H07147485A JP 29299393 A JP29299393 A JP 29299393A JP 29299393 A JP29299393 A JP 29299393A JP H07147485 A JPH07147485 A JP H07147485A
Authority
JP
Japan
Prior art keywords
interlayer connection
connection hole
laminated printed
intermediate layers
land
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP29299393A
Other languages
Japanese (ja)
Other versions
JP3225451B2 (en
Inventor
和久 ▼角▲井
Kazuhisa Kadoi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP29299393A priority Critical patent/JP3225451B2/en
Publication of JPH07147485A publication Critical patent/JPH07147485A/en
Application granted granted Critical
Publication of JP3225451B2 publication Critical patent/JP3225451B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To provide a method of manufacturing a laminated printed board, wherein the laminated printed board can be formed into a multilayered structure without taking an aspect ratio into consideration. CONSTITUTION:Intermediate layers 3 each provided with an interlayer connection hole 1 and fully covered with an insulating layer 2 excluding a land 1a around the connection hole 1 are provided, and then the intermediate layers 3 are bonded together electrically connecting the lands 1a together.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、積層プリント基板の製
造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a laminated printed circuit board.

【0002】[0002]

【従来の技術】従来、多層積層プリント基板を製造する
には、所望のパターンが形成された複数の中間層をプリ
プレグを介して接合し、しかる後、ドリル等で層間接
続、あるいは素子実装用のスルーホールを形成すること
が行われている。
2. Description of the Related Art Conventionally, in order to manufacture a multilayer laminated printed circuit board, a plurality of intermediate layers having a desired pattern are bonded to each other through a prepreg, and thereafter, interlayer connection is performed by a drill or the like, or element mounting is performed. Through holes are being formed.

【0003】[0003]

【発明が解決しようとする課題】しかし、上述した従来
例において、中間層の積層層数が多くなると、板厚も厚
くなり、その結果、スルーホールの孔径を微小化するの
が困難となるために、積層層数をより増加させることが
できないという欠点を有するものであった。
However, in the above-mentioned conventional example, when the number of laminated layers of the intermediate layers is increased, the plate thickness is also increased, and as a result, it becomes difficult to reduce the hole diameter of the through hole. In addition, it has a drawback that the number of laminated layers cannot be increased.

【0004】本発明は、以上の欠点を解消すべくなされ
たものであって、アスペクト比を考慮することなく多層
化することのできる積層プリント基板の製造方法を提供
することを目的とする。
The present invention has been made in order to solve the above drawbacks, and an object of the present invention is to provide a method for manufacturing a laminated printed circuit board which can be multilayered without considering the aspect ratio.

【0005】[0005]

【課題を解決するための手段】本発明によれば上記目的
は、実施例に対応する図1に示すように、層間接続ホー
ル1を備え、該層間接続ホール1のランド部1aを除い
て全表面を絶縁層2にて被覆した複数の中間層3を形成
し、次いで、前記ランド部1a、1a同士の導通を取っ
て中間層3、3・・同士を接合する積層プリント基板の
製造方法を提供することにより達成される。
According to the present invention, the above object is provided with an interlayer connecting hole 1 as shown in FIG. 1 corresponding to the embodiment, and all of the interlayer connecting hole 1 except the land portion 1a are provided. A method for manufacturing a laminated printed circuit board, in which a plurality of intermediate layers 3 each having a surface covered with an insulating layer 2 are formed, and then the land portions 1a, 1a are electrically connected to each other to join the intermediate layers 3, 3 ,. It is achieved by providing.

【0006】[0006]

【作用】各中間層3は、層間接続ホール1のランド部1
aを除く全表面が絶縁層2で被覆されており、これら中
間層3同士を適宜の接合手段により接合させることによ
り、層間接続ホール1同士が導通し、基体3a上の配線
パターン3b同士は、絶縁層2により絶縁が保たれる。
The intermediate layer 3 is the land portion 1 of the interlayer connection hole 1.
The entire surface except a is covered with the insulating layer 2, and the interlayer connection holes 1 are brought into conduction by joining the intermediate layers 3 with each other by an appropriate joining means, and the wiring patterns 3b on the base 3a are Insulation is maintained by the insulating layer 2.

【0007】中間層3は、一般に厚さが0.1ないし
0.2mmと薄いために、アスペクト比を高めることな
く層間接続ホール1の孔径を微細にすることが可能とな
り、製造効率等の向上がもたらされる。
Since the intermediate layer 3 is generally as thin as 0.1 to 0.2 mm, the hole diameter of the interlayer connection hole 1 can be made fine without increasing the aspect ratio, and the manufacturing efficiency is improved. Is brought about.

【0008】[0008]

【実施例】以下、本発明の望ましい実施例を添付図面に
基づいて詳細に説明する。本発明による積層プリント基
板の製造工程を図1に示す。積層プリント基板を構成す
る中間層3は、基体3aの表裏面に所望のパターニング
を施して形成される。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings. The manufacturing process of the laminated printed circuit board according to the present invention is shown in FIG. The intermediate layer 3 constituting the laminated printed circuit board is formed by subjecting the front and back surfaces of the base body 3a to desired patterning.

【0009】また、基体3aには、層間を接続するため
のスルーホール(層間接続ホール1)と、スルーホール
ランド1a(ランド部1a)が形成されるとともに、基
体3aの表裏面は、スルーホールランド1aを除く全表
面に渡って絶縁層2により覆われている(図1(a)参
照)。
A through hole (interlayer connection hole 1) for connecting the layers and a through hole land 1a (land portion 1a) are formed in the base body 3a, and the front and back surfaces of the base body 3a have through holes. The entire surface except the land 1a is covered with the insulating layer 2 (see FIG. 1A).

【0010】以上のように構成される中間層3は、接続
すべきスルーホールランド1a同士を対峙させた状態で
複数枚積層され、導電性を有する接着体5により接合さ
れる。
A plurality of the intermediate layers 3 having the above-described structure are stacked with the through-hole lands 1a to be connected facing each other, and are bonded by the conductive adhesive 5.

【0011】この状態において、各中間層3、3間はス
ルーホール1、およびスルーホールランド1aを介して
層間接続がなされ、かつ、中間層3、3間の配線パター
ン3bは、各中間層3に形成された絶縁層2により絶縁
される。
In this state, interlayer connection is made between the intermediate layers 3 and 3 through the through hole 1 and the through hole land 1a, and the wiring pattern 3b between the intermediate layers 3 and 3 is the intermediate layer 3 respectively. It is insulated by the insulating layer 2 formed on the.

【0012】図2に中間層3の製造工程を示す。この実
施例において、先ず、基体3aにスルーホール1、およ
び配線パターン3bが形成され、次いで、スルーホール
1のランド部1aにマスク4が施される。マスキング材
としては、感光性ポリイミド樹脂等の使用が可能であ
る。
FIG. 2 shows the manufacturing process of the intermediate layer 3. In this embodiment, first, the through hole 1 and the wiring pattern 3b are formed in the base body 3a, and then the mask 4 is applied to the land portion 1a of the through hole 1. A photosensitive polyimide resin or the like can be used as the masking material.

【0013】この後、上記基体3aの表裏面には、全面
に渡って絶縁材がコーティングされる。絶縁材として
は、レジストのようなものが使用され、例えばエポキシ
樹脂等が使用可能である。また、上記絶縁材(絶縁層
2)の膜厚は、スルーホールランド1aの膜厚よりやや
薄くされる。
Thereafter, the front and back surfaces of the base body 3a are coated with an insulating material over the entire surface. A material such as a resist is used as the insulating material, and for example, an epoxy resin or the like can be used. The thickness of the insulating material (insulating layer 2) is made slightly smaller than that of the through hole land 1a.

【0014】中間層3は、以上の工程の後、上記マスク
4を適宜手段により剥離することにより形成される。マ
スク4の剥離は、マスク4のみを剥離して絶縁材を残留
させる剥離液を適宜選択することによりなされる。
The intermediate layer 3 is formed by peeling the mask 4 by an appropriate means after the above steps. The mask 4 is peeled off by appropriately selecting a peeling liquid that peels off only the mask 4 and leaves the insulating material.

【0015】次に中間層3同士の接合方法の実施例を図
1、図3により示す。この実施例において、接着体5
は、シート状の接着剤中に複数個の微小のカプセル5
a、5a・・を混入させて形成されており、各カプセル
5aは、導体の表層を非導体の表皮により覆って形成さ
れる。
Next, an embodiment of a method for joining the intermediate layers 3 to each other will be described with reference to FIGS. In this embodiment, the adhesive 5
Is a sheet-like adhesive containing a plurality of small capsules 5.
are formed by mixing a, 5a ..., And each capsule 5a is formed by covering the surface layer of the conductor with the skin of the non-conductor.

【0016】係る接着体5を使用した中間層3同士の接
合は、接合すべき中間層3の中間に接着体5を介在させ
た状態で加熱、加圧することによりなされるもので、接
合工程において、カプセル5aの表皮は加圧力により破
断し、加圧方向のみに導電性を示す異方性導電接着体5
として機能する。
The joining of the intermediate layers 3 to each other using the adhesive body 5 is performed by heating and pressing with the adhesive body 5 interposed between the intermediate layers 3 to be joined. The anisotropic conductive adhesive body 5 in which the skin of the capsule 5a is broken by the applied pressure and exhibits conductivity only in the pressing direction
Function as.

【0017】なお、図3において白丸は表皮が破断され
ずに相互に絶縁状態を維持するカプセル5aを、黒丸は
表皮が破断されて相互に導通状態となったカプセル5a
を示すものである。
In FIG. 3, white circles indicate capsules 5a which maintain their insulating state without breaking their skins, and black circles indicate capsules 5a whose skins are broken and are in a mutually conductive state.
Is shown.

【0018】[0018]

【発明の効果】以上の説明より明らかなように、本発明
によれば、アスペクト比を高めることなく、微細な層間
接続ホールを形成することができる。
As is apparent from the above description, according to the present invention, it is possible to form fine interlayer connection holes without increasing the aspect ratio.

【0019】さらに、中間層同士は、層間接続ホールに
比して比較的面積の広いランド部同士の導通を取ること
により行われるので、接合時の位置合わせが容易にな
る。また、接着体に異方性導電体を使用する場合には、
隣接する層間接続ホール間の短絡を考慮することなく、
接合作業を行うことができる。
Further, since the intermediate layers are formed by connecting the lands having a relatively large area as compared with the interlayer connecting holes, the alignment at the time of joining becomes easy. When using an anisotropic conductor for the adhesive,
Without considering a short circuit between adjacent interlayer connection holes,
Joining work can be performed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明を示す図で、(a)は接合前の状態、
(b)は接合状態を示す図である。
FIG. 1 is a diagram showing the present invention, in which (a) is a state before joining,
(B) is a figure showing a joined state.

【図2】中間層の製造工程を示す図である。FIG. 2 is a diagram showing a manufacturing process of an intermediate layer.

【図3】接着体の導通状態を示す図である。FIG. 3 is a diagram showing a conductive state of an adhesive body.

【符号の説明】[Explanation of symbols]

1 層間接続ホール 1a ランド部 2 絶縁層 3 中間層 3a 基体 3b 配線パターン 4 マスク 1 Interlayer Connection Hole 1a Land Part 2 Insulating Layer 3 Intermediate Layer 3a Base 3b Wiring Pattern 4 Mask

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】層間接続ホール(1)を備え、該層間接続
ホール(1)のランド部(1a)を除いて全表面を絶縁
層(2)にて被覆した複数の中間層(3、3・・)を形
成し、 次いで、前記ランド部(1a)同士の導通を取って中間
層(3、3・・)同士を接合する積層プリント基板の製
造方法。
1. A plurality of intermediate layers (3, 3) each having an interlayer connection hole (1), the entire surface of which is covered with an insulating layer (2) except for a land portion (1a) of the interlayer connection hole (1). .) Is formed, and then the land portions (1a) are electrically connected to each other to join the intermediate layers (3, 3 ...) To each other.
【請求項2】前記中間層(3)同士は、加圧方向にのみ
導電性を示す異方性導電接着体により加圧状態で接合さ
れる請求項1記載の積層プリント基板の製造方法。
2. The method for producing a laminated printed circuit board according to claim 1, wherein the intermediate layers (3) are bonded together under pressure by an anisotropic conductive adhesive that exhibits conductivity only in the pressure direction.
【請求項3】基体(3a)に配線パターン(3b)、お
よび層間接続ホール(1)を形成した後、 層間接続ホール(1)のランド部(1a)をマスキング
し、 次いで、基体(3a)の全表面に絶縁材をコーティング
した後、ランド部(1a)のマスク(4)を剥離して中
間層(3)を製造する請求項1または2記載の積層プリ
ント基板の製造方法。
3. A wiring pattern (3b) and an interlayer connection hole (1) are formed on a substrate (3a), and then a land portion (1a) of the interlayer connection hole (1) is masked, and then the substrate (3a). The method for manufacturing a laminated printed circuit board according to claim 1 or 2, wherein the intermediate layer (3) is manufactured by coating the insulating material on the entire surface of (1) and then removing the mask (4) of the land (1a).
【請求項4】前記絶縁層(2)は、層間接続ホール
(1)のランド部(1a)の膜厚よりも薄く形成される
請求項1、2または3記載の積層プリント基板の製造方
法。
4. The method for manufacturing a laminated printed circuit board according to claim 1, wherein the insulating layer (2) is formed thinner than the film thickness of the land portion (1a) of the interlayer connection hole (1).
JP29299393A 1993-11-24 1993-11-24 Manufacturing method of laminated printed circuit board Expired - Fee Related JP3225451B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29299393A JP3225451B2 (en) 1993-11-24 1993-11-24 Manufacturing method of laminated printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29299393A JP3225451B2 (en) 1993-11-24 1993-11-24 Manufacturing method of laminated printed circuit board

Publications (2)

Publication Number Publication Date
JPH07147485A true JPH07147485A (en) 1995-06-06
JP3225451B2 JP3225451B2 (en) 2001-11-05

Family

ID=17789089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29299393A Expired - Fee Related JP3225451B2 (en) 1993-11-24 1993-11-24 Manufacturing method of laminated printed circuit board

Country Status (1)

Country Link
JP (1) JP3225451B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09321439A (en) * 1996-05-31 1997-12-12 Nec Corp Lamination circuit board
JP2002232143A (en) * 2001-01-31 2002-08-16 Toppan Printing Co Ltd Coaxial via hole and its forming method, multilayer wiring board and its producing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09321439A (en) * 1996-05-31 1997-12-12 Nec Corp Lamination circuit board
JP2002232143A (en) * 2001-01-31 2002-08-16 Toppan Printing Co Ltd Coaxial via hole and its forming method, multilayer wiring board and its producing method
JP4734723B2 (en) * 2001-01-31 2011-07-27 凸版印刷株式会社 Manufacturing method of multilayer wiring board using coaxial via hole

Also Published As

Publication number Publication date
JP3225451B2 (en) 2001-11-05

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