JPH01205445A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01205445A JPH01205445A JP3024388A JP3024388A JPH01205445A JP H01205445 A JPH01205445 A JP H01205445A JP 3024388 A JP3024388 A JP 3024388A JP 3024388 A JP3024388 A JP 3024388A JP H01205445 A JPH01205445 A JP H01205445A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- metal
- layer
- wiring
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 16
- 238000000034 method Methods 0.000 abstract description 11
- 229910052759 nickel Inorganic materials 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000007547 defect Effects 0.000 abstract 2
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000000151 deposition Methods 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 238000001312 dry etching Methods 0.000 abstract 1
- 238000009713 electroplating Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000001465 metallisation Methods 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 abstract 1
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に半導体装置の金属配線
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to metal wiring of a semiconductor device.
従来、半導体装置の集積度か高まるにつれて、配線の間
隔及び幅か益々狭くなってきている。このように高密度
化された各半導体素子間の配線材料として安価で、加工
し易いアルミニウムもしくはアルミニウム合金か用いら
れている。Conventionally, as the degree of integration of semiconductor devices increases, the spacing and width of interconnections have become narrower. Aluminum or aluminum alloy, which is inexpensive and easy to process, is used as a wiring material between each of the highly dense semiconductor elements.
第２図は従来の半導体装置の一例を示す半導体チップの
断面図である。これは半導体基板」−に金属配線層を設
けた例で、Ｐ型シリコン基板１」−に酸化Ｍ２か形成さ
れており、その」二に金属蒸着法にＬり二つのアルミニ
ウム配線層３か平行に形成されている。また、アルミニ
ウム配線層３及び酸化膜４の上には、配線層間の絶縁及
びＰ型シリコン基板１の表面を保護するようにＣＶＤ法
により絶縁膜４か形成されている。この例の配線層３の
幅は２μｍ以下、配線層３の間隔は１μｍ以下という非
常に狭い設計仕様である。FIG. 2 is a cross-sectional view of a semiconductor chip showing an example of a conventional semiconductor device. This is an example in which a metal wiring layer is provided on a semiconductor substrate, in which a P-type silicon substrate 1 is formed with oxidized M2, and two aluminum wiring layers 3 are formed in parallel using a metal vapor deposition method. is formed. Further, an insulating film 4 is formed on the aluminum wiring layer 3 and the oxide film 4 by the CVD method so as to insulate between the wiring layers and protect the surface of the P-type silicon substrate 1. In this example, the width of the wiring layer 3 is 2 μm or less, and the interval between the wiring layers 3 is 1 μm or less, which is a very narrow design specification.
上述した半導体装置では、数千時間の使用て内部の配線
か短絡もし７くは断線を起すという問題かある
第３図は半導体装置の内部の配線層の短絡及び断線に至
る状態を説明するだめの配線層の」−面図である。アル
ミニウム配線層３の１−７にある絶縁膜４は通常ＣＶ
Ｄ法により酸化膜として形成されるので、この酸化膜の
改質はアルミニウム配線層３の上面は緻密に、側面は粗
に作られる。従って、アルミニウム配線層３の上面には
圧縮応力、側面には引張応力か作用したままとなる。こ
の状態が長時間続くと、圧縮応力のかかっている部分と
引張応力のかかっている部分との境界でクリープ現象を
引起し、この境界からしみ出し６及び欠落５か発生し、
］００’Ｃ以」二の周囲温度によりさらに加速され、し
み出し６か成長し、ついには隣接のアルミニウム配線層
３に接触したり、または欠落５が進行しアルミニウム配
線層３か断線するという問題か起きる。In the above-mentioned semiconductor device, there is a problem that the internal wiring may short-circuit or break after several thousand hours of use. Figure 3 shows a situation that can lead to a short-circuit or break in the internal wiring layer of a semiconductor device. 2 is a plan view of the wiring layer of FIG. The insulating film 4 on 1-7 of the aluminum wiring layer 3 is usually CV
Since it is formed as an oxide film by the D method, the oxide film is modified so that the top surface of the aluminum wiring layer 3 is dense and the side surfaces are rough. Therefore, compressive stress remains on the top surface of the aluminum wiring layer 3, while tensile stress remains on the side surface. If this state continues for a long time, a creep phenomenon will occur at the boundary between the compressive stress area and the tensile stress area, and seepage 6 and chipping 5 will occur from this boundary.
] The problem is that the seepage 6 grows further due to the ambient temperature of 00'C or higher, and eventually comes into contact with the adjacent aluminum wiring layer 3, or the chipping 5 progresses and the aluminum wiring layer 3 is disconnected. Or wake up.
本発明の目的は、内部配線のしみ出し、欠落による短絡
及び断線か起きない半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device that does not cause short circuits or disconnections due to seepage or missing internal wiring.
〔課題を解決するだめの手段」
本発明の半導体装置は、−導電型半導体基板の一主面上
に複数グ）半導体素子を形成し、前記複数の半導体素子
を金属配線層で接続してなる半導体装置において、前記
金属配線層とし２てアルミニウムを主元素とする金属で
形成し、且つ少なくとも前記金属配線層の側壁かアルミ
ニウムより大きい弾性限度の金属膜て被覆されているこ
とを片んて暢成される。[Means for Solving the Problems] The semiconductor device of the present invention comprises - forming a plurality of semiconductor elements on one principal surface of a conductive type semiconductor substrate, and connecting the plurality of semiconductor elements with a metal wiring layer. In the semiconductor device, it is clear that the metal wiring layer 2 is formed of a metal whose main element is aluminum, and that at least a side wall of the metal wiring layer is covered with a metal film having an elastic limit greater than that of aluminum. will be accomplished.
〔実施例」 次に、本発明について図面を参照して説明する。〔Example" Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（Ｃ）は本発明の一実施例を説明するだ
めの半導体チップの断面図である。まず、第１−図（ａ
）に示すように、Ｐ型シリコン基板１の上に熱酸化法に
より酸化膜２を形成する。FIGS. 1A to 1C are cross-sectional views of a semiconductor chip for explaining an embodiment of the present invention. First, Figure 1 (a
), an oxide film 2 is formed on a P-type silicon substrate 1 by thermal oxidation.
次に、金属蒸着法により全面にアルミニウムを蒸着し、
ホＩ〜リソクラフィ法及び１〜ライエツチンク法を用い
て、アルミニウム蒸着層を選択的に取除き、レジスト層
５とアルミニウム配線層３を形成する。次に、第１図り
１））に示すように、無電界めっき法によりアルミニウ
ム配線層３の側面にニッケル膜６を形成する、このニッ
ケル膜６の厚さは、アルミニウム配線層３の厚さか１μ
ｍ前後のとき、０１〜０２μｍに形成すればよい。また
、アルミニウム配線層３の−Ｌにはレジスト層５かある
ため、めっきされることはないか、レシス１〜層５を除
去して、アルミニウム配線層３の上にもニッケルめっき
膜が形成されてもよい。次に、第１−図＜ｃ＞に示ずよ
うに、レジス１へ層５を取除き、ＣＶ Ｄ法により配線
層間の絶縁及びＰ型シリコン表面保護のための酸化膜を
成長さぜ絶縁膜４を形成する。また、必要に応して、４
００〜４５０°Ｃ程度の温度で熱処理して、ニッケル膜
６とアルミニウム配線層３との密着性をより強化する。Next, aluminum is deposited on the entire surface using a metal vapor deposition method,
The aluminum vapor deposited layer is selectively removed using the lithography method and the lithography method to form the resist layer 5 and the aluminum wiring layer 3. Next, as shown in the first diagram 1)), a nickel film 6 is formed on the side surface of the aluminum wiring layer 3 by electroless plating.
When the thickness is around m, it may be formed to have a thickness of 01 to 02 μm. Also, since there is a resist layer 5 on -L of the aluminum wiring layer 3, it may not be plated, or a nickel plating film may be formed on the aluminum wiring layer 3 by removing resists 1 to 5. You can. Next, as shown in Figure 1 <c>, layer 5 is removed from resist 1, and an oxide film is grown by CVD to insulate between wiring layers and protect the P-type silicon surface. form 4. In addition, if necessary, 4
The adhesion between the nickel film 6 and the aluminum wiring layer 3 is further strengthened by heat treatment at a temperature of about 00 to 450°C.
以」−説明したように本発明により、アルミニウム配線
層の側面に弾性限度のより大きいニッケル膜を形成する
ことによって前述のアルミニウム配線層のしみ出し及び
欠落による配線の短絡及び断線の起きない半導体装置か
得られるという効果かある。- As explained above, the present invention provides a semiconductor device in which short-circuits and disconnections of wiring due to the above-mentioned seepage and chipping of the aluminum wiring layer do not occur by forming a nickel film with a higher elastic limit on the side surface of the aluminum wiring layer. There is an effect that you can get it.
第１図（ａ）〜（Ｃ）は本発明の一実施例を説明するだ
めの半導体チップの断面図、第２図は従来の半導体装置
の一例を示す半導体チップの断面図、第３図は半導体装
置の内部の配線層の短絡及び断線に至る状態を説明する
だめの配線層の上面図である。
１・・Ｐ型シリコン基板、２・酸化膜、３・・アルミニ
ウム配線層、４・・絶縁膜、５・・レシスＩ−層、６・
・ニッケル膜。FIGS. 1(a) to (C) are cross-sectional views of a semiconductor chip for explaining an embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor chip showing an example of a conventional semiconductor device, and FIG. FIG. 2 is a top view of a useless wiring layer illustrating a state in which a wiring layer inside a semiconductor device is short-circuited and disconnected. 1. P-type silicon substrate, 2. Oxide film, 3. Aluminum wiring layer, 4. Insulating film, 5. Resis I-layer, 6.
・Nickel film.
Claims (1)
形成し、前記複数の半導体素子を金属配線層で接続して
なる半導体装置において、前記金属配線層としてアルミ
ニウムを主元素とする金属で形成し、且つ少なくとも前
記金属配線層の側壁がアルミニウムより大きい弾性限度
の金属膜で被覆されていることを特徴とする半導体装置
。In a semiconductor device in which a plurality of semiconductor elements are formed on one principal surface of a semiconductor substrate of one conductivity type, and the plurality of semiconductor elements are connected by a metal wiring layer, the metal wiring layer is made of a metal whose main element is aluminum. and at least a side wall of the metal wiring layer is coated with a metal film having an elastic limit greater than that of aluminum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3024388A JPH01205445A (en) | 1988-02-10 | 1988-02-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3024388A JPH01205445A (en) | 1988-02-10 | 1988-02-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01205445A true JPH01205445A (en) | 1989-08-17 |
Family
ID=12298266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3024388A Pending JPH01205445A (en) | 1988-02-10 | 1988-02-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01205445A (en) |
-
1988
- 1988-02-10 JP JP3024388A patent/JPH01205445A/en active Pending
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