JP2605524B2 - Thin film multilayer circuit board - Google Patents
Thin film multilayer circuit boardInfo
- Publication number
- JP2605524B2 JP2605524B2 JP3259105A JP25910591A JP2605524B2 JP 2605524 B2 JP2605524 B2 JP 2605524B2 JP 3259105 A JP3259105 A JP 3259105A JP 25910591 A JP25910591 A JP 25910591A JP 2605524 B2 JP2605524 B2 JP 2605524B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- insulating layer
- multilayer circuit
- film multilayer
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【０００１】[0001]
【産業上の利用分野】本発明は、各種電子機器の構成に
広く使用されるプリント板ユニットの薄膜多層回路基板
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film multilayer circuit board for a printed circuit board unit widely used in the construction of various electronic devices.
【０００２】最近、特にコンピュータシステムあるいは
大型通信機器等に使用される薄膜多層化配線基板は回路
規模の増大と高速化の要求に伴い、絶縁基板に形成され
る導体パターンは各層において微細化と高密度化が行わ
れるとともに低誘電性が必要となっている。In recent years, in particular, a thin-film multilayer wiring board used for a computer system or a large-sized communication device has been required to have a larger circuit scale and a higher speed. As the density increases, low dielectric properties are required.
【０００３】そのため、絶縁基板のパターン形成面側
に、配線パターンと層間絶縁層を交互に形成して多層化
しているが、この層間絶縁層はポリイミド樹脂の薄膜で
あるので、絶縁基板とは熱膨張率が異なる。したがっ
て、加熱等されて温度が変化すると積層された層間絶縁
層に収縮方向或いは膨張方向の大きな内部応力が発生
し、層間絶縁層と絶縁基板間に境界面剥離が発生する。
このため境界面剥離が発生しない薄膜多層回路基板が要
求されている。 For this reason, a wiring pattern and an interlayer insulating layer are alternately formed on the pattern forming surface side of an insulating substrate to form a multilayer.
However, this interlayer insulating layer is a thin film of polyimide resin.
Therefore, the thermal expansion coefficient is different from that of the insulating substrate. Accordingly
When the temperature changes due to heating, etc., the laminated interlayer insulation
Large internal stress in the direction of contraction or expansion in the layer
As a result, interface separation occurs between the interlayer insulating layer and the insulating substrate.
For this reason, a thin-film multilayer circuit board that does not cause boundary separation is required.
Is required.
【０００４】[0004]
【従来の技術】従来広く使用されている多層薄膜回路基
板は、第２図の側断面図に示すように配線パターン２を
高密度に形成したセラミックよりなる絶縁基板１の回路
形成面側にポリイミド樹脂を塗布した薄膜の層間絶縁層
３を形成し、その層間絶縁層３の上面に異なる配線パタ
ーン２を高密度に形成することにより薄膜絶縁回路層を
設け、この薄膜絶縁回路層の形成を繰り返して行うこと
で複数枚が重畳された構造となっている。2. Description of the Related Art As shown in the side sectional view of FIG. 2, a multilayer thin film circuit board which is widely used in the past has a polyimide on a circuit forming surface side of an insulating substrate 1 made of ceramic on which wiring patterns 2 are formed at high density. A thin-film interlayer insulating layer 3 coated with a resin is formed, and a different wiring pattern 2 is formed at a high density on the upper surface of the interlayer insulating layer 3 to provide a thin-film insulating circuit layer. This formation of the thin-film insulating circuit layer is repeated. In this case, a plurality of sheets are superimposed.
【０００５】[0005]
【発明が解決しようとする課題】以上説明した従来の薄
膜多層回路基板で問題となるのは、第３図に示すように
絶縁基板１の回路形成面側に積層された層間絶縁層３が
絶縁基板１の熱膨張率と大きく異なるポリイミド樹脂で
形成されているため、この薄膜多層回路基板に熱が加わ
るとポリイミド樹脂が収縮または膨張方向の大きな内部
応力を発生して層間絶縁層３が収縮または膨張方向に作
用して、その力により絶縁基板１の端縁部と層間絶縁層
３の境界面で剥離を起こすから高多層化ができないとい
う問題が生じている。The problem with the above-described conventional thin film multilayer circuit board is that the interlayer insulating layer 3 laminated on the circuit forming surface side of the insulating substrate 1 is insulated as shown in FIG. Since the polyimide resin is formed of a polyimide resin that is significantly different from the coefficient of thermal expansion of the substrate 1, when heat is applied to the thin-film multilayer circuit board, the polyimide resin generates a large internal stress in the direction of expansion or contraction, and the interlayer insulating layer 3 contracts or Acting in the direction of expansion, the force causes peeling at the boundary between the edge of the insulating substrate 1 and the interlayer insulating layer 3, so that there is a problem that a high multilayer structure cannot be achieved.
【０００６】本発明は上記のような問題点に鑑み、絶縁
基板と層間絶縁層の密着強度を大きくして熱による境界
面剥離が起らない薄膜多層回路基板の提供を目的とす
る。SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a thin-film multilayer circuit board in which the adhesion strength between an insulating substrate and an interlayer insulating layer is increased so that boundary separation due to heat does not occur.
【０００７】[0007]
【課題を解決するための手段】本発明は図１に例示した
ように、高融点金属よりなる枠状の端縁パターン14を、
絶縁基板１の表面中央部に形成する配線パターン２を囲
むよう絶縁基板１に密着して設け、配線パターン２と端
縁パターン14の上面を密着して覆うように、ポリイミド
樹脂よりなる層間絶縁層13を形成した構成とする。 SUMMARY OF THE INVENTION The present invention is illustrated in FIG.
As described above, the frame-shaped edge pattern 14 made of a high melting point metal,
Surrounds the wiring pattern 2 formed at the center of the surface of the insulating substrate 1
The wiring pattern 2 and the end
The interlayer insulating layer 13 made of a polyimide resin is formed so as to closely cover the upper surface of the edge pattern 14 .
【０００８】[0008]
【作用】本発明では、絶縁基板１の端縁空白部に設けら
れたＣｒ等の高融点金属よりなる枠状の端縁パターン14
を覆う状態で層間絶縁層13を形成することにより、この
層間絶縁層13を形成するポリイミド樹脂の前駆体である
ポリアミック酸中のカルボキシル基とＣｒがイオン結合
することで結合強度が増加するから、端縁パターン14と
層間絶縁層13の密着力が大きくアップして層間絶縁層13
と絶縁基板１の境界面剥離を防止することが可能とな
る。According to the present invention, a frame-shaped edge pattern 14 made of a high melting point metal such as Cr provided in a blank portion of the edge of the insulating substrate 1 is provided.
By forming the interlayer insulating layer 13 in a state of covering, since the carboxyl group in the polyamic acid which is a precursor of the polyimide resin forming the interlayer insulating layer 13 and Cr are ion-bonded, the bonding strength increases, The adhesion between the edge pattern 14 and the interlayer insulating layer 13 is greatly increased, and
It is possible to prevent the boundary surface of the insulating substrate 1 from peeling off.
【０００９】[0009]
【実施例】以下図を参照しながら、本発明を具体的に説
明する。なお、全図を通じて同一符号は同一対象物を示
す。 BRIEF DESCRIPTION OF THE DRAWINGS FIG.
I will tell. The same reference numerals indicate the same objects throughout the drawings.
You.
【００１０】本発明の薄膜多層回路基板は、図１(a) に
示すようにセラミックよりなる絶縁基板１の配線パター
ン２を形成する領域の外側となる基板端縁部に、配線パ
ターン領域を囲む一定幅の枠状で高融点金属，例えばＣ
ｒ−Ｃｕ−Ｃｒよりなる端縁パターン14を形成する。As shown in FIG. 1 (a), the thin film multilayer circuit board of the present invention surrounds the wiring pattern region at the edge of the substrate outside the region where the wiring pattern 2 is formed on the insulating substrate 1 made of ceramic. High melting point metal such as C
An edge pattern 14 made of r-Cu-Cr is formed.
【００１１】配線パターン２の形成領域を含む端縁パタ
ーン14上面の幅方向中心線より内側に、ポリイミド樹脂
よりなる薄膜の層間絶縁層13を形成し、図１(b) に図示
したようにこの層間絶縁層13の上面に、他の配線パター
ン２を形成する。このことを複数回繰り返し実施して、
絶縁基板１の回路形成面側に配線パターン２と層間絶縁
層13とを交互に形成して薄膜多層回路を設けている。 Edge pattern including a region for forming wiring pattern 2
Inward from the widthwise center line of the over down 14 top, to form a thin film of the interlayer insulating layer 13 made of polyimide resin, shown in FIG. 1 (b)
As described above, another wiring pattern is formed on the upper surface of the interlayer insulating layer 13.
2 is formed. Repeat this several times,
Wiring pattern 2 and interlayer insulation on circuit forming surface side of insulating substrate 1
The layers 13 are alternately formed to provide a thin-film multilayer circuit.
【００１２】その結果、一層目の層間絶縁層13を形成す
るポリイミド樹脂と端縁パターン14の結合強度が増加す
るから、絶縁基板１と積層された層間絶縁層13の境界面
剥離を防止することができる。As a result, the bonding strength between the polyimide resin forming the first interlayer insulating layer 13 and the edge pattern 14 is increased, so that separation of the interface between the insulating substrate 1 and the laminated interlayer insulating layer 13 is prevented. Can be.
【００１３】[0013]
【発明の効果】以上の説明から明らかなように本発明に
よれば極めて簡単な構成で、層間絶縁層13と絶縁基板１
が強固に密着することにより境界面剥離を防止できる等
の利点があり、著しい経済的及び、信頼性向上の効果が
期待できる薄膜多層回路基板を提供することができる。As is apparent from the above description, according to the present invention, the interlayer insulating layer 13 and the insulating substrate 1 have a very simple structure.
There is an advantage such that separation of the boundary surface can be prevented by firmly adhering, and it is possible to provide a thin-film multilayer circuit board which is expected to be remarkably economical and to have an effect of improving reliability.
【図１】 本実施例による薄膜多層回路基板を示す図で
ある。FIG. 1 is a diagram showing a thin-film multilayer circuit board according to the present embodiment.
【図２】 従来の薄膜多層回路基板を示す側断面図であ
る。FIG. 2 is a side sectional view showing a conventional thin film multilayer circuit board.
【図３】 問題点を説明する側断面図である。FIG. 3 is a side sectional view illustrating a problem.
１は絶縁基板、２は配線パターン、13は層間絶縁層、14
は端縁パターン、1 is an insulating substrate, 2 is a wiring pattern, 13 is an interlayer insulating layer, 14
Is the edge pattern,
Claims (1)
(14)を、絶縁基板(1) の表面中央部に形成する配線パタ
ーン(2) を囲むよう該絶縁基板(1) に密着して設け、該
配線パターン(2) と該端縁パターン(14)の上面を密着し
て覆うように、ポリイミド樹脂よりなる層間絶縁層(13)
を形成したことを特徴とする薄膜多層回路基板。1. A frame-shaped edge pattern made of a high melting point metal.
(14) is a wiring pattern formed in the center of the surface of the insulating substrate (1).
And provided in close contact with the insulating substrate (1) so as to surround the
The wiring pattern (2) and the upper surface of the edge pattern (14) are brought into close contact with each other.
To cover the interlayer insulating layer made of polyimide resin (13)
A thin-film multilayer circuit board, characterized by forming:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3259105A JP2605524B2 (en) | 1991-10-07 | 1991-10-07 | Thin film multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3259105A JP2605524B2 (en) | 1991-10-07 | 1991-10-07 | Thin film multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05102662A JPH05102662A (en) | 1993-04-23 |
| JP2605524B2 true JP2605524B2 (en) | 1997-04-30 |
Family
ID=17329396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3259105A Expired - Fee Related JP2605524B2 (en) | 1991-10-07 | 1991-10-07 | Thin film multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2605524B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2015102107A1 (en) * | 2014-01-06 | 2017-03-23 | 株式会社村田製作所 | Multilayer wiring board and inspection apparatus including the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63268295A (en) * | 1987-04-27 | 1988-11-04 | Hitachi Ltd | Multilayer interconnection substrate |
| JPH0268992A (en) * | 1988-09-02 | 1990-03-08 | Nec Corp | Multilayered interconnection board |
-
1991
- 1991-10-07 JP JP3259105A patent/JP2605524B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05102662A (en) | 1993-04-23 |
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