JPH01204513A - Current output circuit - Google Patents

Current output circuit

Info

Publication number
JPH01204513A
JPH01204513A JP63029227A JP2922788A JPH01204513A JP H01204513 A JPH01204513 A JP H01204513A JP 63029227 A JP63029227 A JP 63029227A JP 2922788 A JP2922788 A JP 2922788A JP H01204513 A JPH01204513 A JP H01204513A
Authority
JP
Japan
Prior art keywords
output
transistor
diode
circuit
input side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63029227A
Other languages
Japanese (ja)
Inventor
Minoru Yamazaki
稔 山崎
Kozo Hamaguchi
濱口 耕造
Hidenori Morita
秀則 森田
Katsuhisa Shimaya
島矢 勝久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63029227A priority Critical patent/JPH01204513A/en
Publication of JPH01204513A publication Critical patent/JPH01204513A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the effect onto a signal from the output side to the input side by providing a one-stage buffer between the input side and the output side. CONSTITUTION:Feedback of an output signal is produced to the base of a transistor(TR) 10 through a collector-base parasitic capacitance of a TR 10, the red-back signal gives effect on a diode 6 but the effect onto the input side is reduced because of the presence of a TR 5. Since one-stage of buffer is provided between the input and output side in this way, the feedback of the signal from the output side to the input side is reduced and it is especially effective when the circuit is applied to a current output circuit with a high frequency and high output.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、VTRの記録電流増幅回路に利用できる電流
出力回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a current output circuit that can be used in a recording current amplification circuit of a VTR.

従来の技術 従来の回路は、第2図に示す様な構成であった。第2図
において、14.17はそれぞれカレントミラーを構成
するダイオ−、ドとトランジスタ、13は電流源、15
.18はミラー比を決定する抵抗、16は負荷である。
Prior Art A conventional circuit has a configuration as shown in FIG. In FIG. 2, 14 and 17 are diodes, transistors and diodes constituting a current mirror, 13 is a current source, and 15
.. 18 is a resistor that determines the mirror ratio, and 16 is a load.

この回路では、出力信号がトランジスタ17のコレクタ
、ベース間の寄生容量を通じて入力側へ信号の帰還が生
じる。
In this circuit, the output signal is fed back to the input side through the parasitic capacitance between the collector and base of the transistor 17.

発明が解決しようとする課題 この様な従来の構成では、出力信号の入力側への帰還が
大きいという問題点があった。本発明は、この様な問題
点を解決するもので、入力側と出力側との間に一段のバ
ッファを設けることにより、出力側から入力側への信号
の影響を低減することを目的とするものである。
Problems to be Solved by the Invention This conventional configuration has a problem in that a large amount of the output signal is fed back to the input side. The present invention solves these problems, and aims to reduce the influence of signals from the output side to the input side by providing a one-stage buffer between the input side and the output side. It is something.

課題を解決するための手段 この問題点を解決するために本発明は、第1電位点に接
続された電流源の他端と、第1のダイオードのアノード
を接続し、第1のダイオードのカソードは第2のダイオ
ードのアノードと接続し、第2のダイオードのカソード
は抵抗を介して第2電位点に接続する。また、前記第1
のダイオードのアノードと前記電流源との共通接続点に
は、第1のトランジスタのベースを接続し、第1のトラ
ンジスタのコレクタは第1電位点に、エミッタは第3の
ダイオードのアノードにそれぞれ接続し、第3のダイオ
ードのカソードは、抵抗を介して第°2電位点に接続す
る。また、前記第1のトランジスタのエミッタと、前記
第3のダイオードのアノードとの共通接続点からは、第
2のトランジスタのベースを接続し、第2のトランジス
タのエミッタは抵抗を介して第2電位点に接続し、コレ
クタには負荷を接続する回路構成となっている。
Means for Solving the Problem In order to solve this problem, the present invention connects the other end of the current source connected to the first potential point to the anode of the first diode, and connects the cathode of the first diode to the other end of the current source connected to the first potential point. is connected to the anode of the second diode, and the cathode of the second diode is connected to the second potential point via a resistor. In addition, the first
The base of the first transistor is connected to a common connection point between the anode of the diode and the current source, the collector of the first transistor is connected to the first potential point, and the emitter is connected to the anode of the third diode. However, the cathode of the third diode is connected to the second potential point via a resistor. Further, the base of the second transistor is connected to a common connection point between the emitter of the first transistor and the anode of the third diode, and the emitter of the second transistor is connected to a second potential through a resistor. The circuit configuration is such that the collector is connected to a point and the load is connected to the collector.

作用 この回路構成により、出力側から入力側への信号の帰還
を低減できる。
Effect: This circuit configuration can reduce signal feedback from the output side to the input side.

実施例 第1図は本発明の一実施例による電流出力回路の構成図
であり、第1図において、2.3,5゜6.10はそれ
ぞれカレントミラーを構成するダイオードとトランジス
タ、4,7.11はミラー比を決定する抵抗、9は出力
の負荷、1は電流源、8は第2図と同様の電源端子、1
2は基準電位点端子、または接地点である。本回路にお
いては、トランジスタ10のコレクタ、ベース間の寄生
容量を通じてトランジスタ10のベースに出力信号の帰
還が生じる。この帰還された信号は、ダイオード6に影
響を与えるが、トランジスタ5があるため、入力側への
影響は低減される。なお、第1図の実施例では、全てN
PNのトランジスタとダイオードで構成した例を示した
が、本発明は、この構成に限定されるものではなく、他
の極性のトランジスタとダイオードで構成してもよい。
Embodiment FIG. 1 is a block diagram of a current output circuit according to an embodiment of the present invention. In FIG. .11 is the resistor that determines the mirror ratio, 9 is the output load, 1 is the current source, 8 is the power supply terminal as shown in Figure 2, 1
2 is a reference potential point terminal or a ground point. In this circuit, the output signal is fed back to the base of the transistor 10 through the parasitic capacitance between the collector and base of the transistor 10. Although this feedback signal affects the diode 6, the presence of the transistor 5 reduces the effect on the input side. In addition, in the embodiment shown in FIG.
Although an example has been shown in which the device is configured with a PN transistor and a diode, the present invention is not limited to this configuration, and may be configured with transistors and diodes of other polarities.

発明の効果 以上の様に本発明は、入力側と出力側との間に新たに一
段のバッファを設けることにより、入力側が出力側から
の信号の帰還によって受ける影響を低減できる回路を実
現させたもので、特に、高周波、高出力の電流出力回路
に用いる際、有効である。
Effects of the Invention As described above, the present invention realizes a circuit that can reduce the influence that the input side receives from the feedback of the signal from the output side by newly providing one stage of buffer between the input side and the output side. This is particularly effective when used in high frequency, high output current output circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例による電流出力回路を示す回
路図、第2図は従来の電流出力回路を示す回路図である
。 2.3.6.14・・・・・・ダイオード、5.10゜
17・・・・・・トランジスタ、4,7,11,15.
18・・・・・・抵抗、1,13・・・・・・電流源、
9,16・旧・・負荷、8・・・・・・電源端子、12
・・・・・・基準電位点。 代理人の氏名 弁理士 中尾敏男 はが1名第2図
FIG. 1 is a circuit diagram showing a current output circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional current output circuit. 2.3.6.14...Diode, 5.10°17...Transistor, 4,7,11,15.
18...Resistor, 1,13...Current source,
9, 16 Old... Load, 8... Power terminal, 12
...Reference potential point. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 2

Claims (1)

【特許請求の範囲】[Claims] 第1電位点に接続された電流源の他端を、第1のダイオ
ード、第2のダイオードおよび抵抗を介して第2電位点
に接続し、前記第1のダイオードのアノードと前記電流
源との共通接続点に第1のトランジスタのベースを接続
し、前記第1のトランジスタのコレクタを前記第1電位
点にエミッタを、第3のダイオードおよび抵抗を介して
、前記第2電位点に接続し、前記第1のトランジスタの
エミッタと前記第3のダイオードとの共通接続点に第2
のトランジスタのベースを接続し、前記第2のトランジ
スタのエミッタを、抵抗を介して、前記第2電位点に接
続し、同第2のトランジスタのコレクタに負荷を接続し
たことを特徴とする電流出力回路。
The other end of the current source connected to the first potential point is connected to the second potential point via a first diode, a second diode, and a resistor, and the anode of the first diode and the current source are connected to each other. connecting a base of a first transistor to a common connection point; connecting a collector of the first transistor to the first potential point; and connecting an emitter to the second potential point via a third diode and a resistor; A second transistor is connected to a common connection point between the emitter of the first transistor and the third diode.
The current output is characterized in that the bases of the transistors are connected to each other, the emitter of the second transistor is connected to the second potential point via a resistor, and a load is connected to the collector of the second transistor. circuit.
JP63029227A 1988-02-10 1988-02-10 Current output circuit Pending JPH01204513A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63029227A JPH01204513A (en) 1988-02-10 1988-02-10 Current output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63029227A JPH01204513A (en) 1988-02-10 1988-02-10 Current output circuit

Publications (1)

Publication Number Publication Date
JPH01204513A true JPH01204513A (en) 1989-08-17

Family

ID=12270334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63029227A Pending JPH01204513A (en) 1988-02-10 1988-02-10 Current output circuit

Country Status (1)

Country Link
JP (1) JPH01204513A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100669831B1 (en) * 1998-04-30 2007-01-18 코닌클리케 필립스 일렉트로닉스 엔.브이. Amplifier output stage provided with a parasitic-current limiter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100669831B1 (en) * 1998-04-30 2007-01-18 코닌클리케 필립스 일렉트로닉스 엔.브이. Amplifier output stage provided with a parasitic-current limiter

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