JPH01202861A - Manufacture of transistor - Google Patents

Abstract

PURPOSE:To manufacture a mechanically firm transistor having excellent high- frequency characteristics easily by forming a first electrode connected from a first conductive layer to a first semiconductor region and extended onto first and second inclined inner side faces. CONSTITUTION:Even when a semiconductor region 4. is shaped so that length in the direction that semiconductor regions 5, 6 are tied is shortened sufficiently, an electrode 7 on the semiconductor region 4 is also extended onto inclined inner side faces 11b, 12b on insulating layers 11', 12'. Consequently, a transistor can be given large volume easily and can be formed mechanically firmly. Since electrodes 8, 9 are shaped in a self-alignment manner, distances among each of the electrodes 8, 9 and the electrode 7 are shortened, and the electrodes 8, 9 can be formed easily. Accordingly, the mechanically strong transistor having excellent high-frequency characteristics can be manufactured readily.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a method for manufacturing a bipolar type transistor, a field effect type transistor, or the like having a structure in which first, second, and third electrodes are arranged in parallel on a semiconductor substrate.

[Conventional technology]

Conventionally, a transistor as described below with reference to FIG. 4 has been proposed. That is, the semiconductor substrate 1 has a structure in which, for example, a semiconductor layer 3 of n-type and made of GaAS is formed on a semi-insulating semiconductor substrate body 2 made of, for example, GaAs. In the semiconductor substrate 1, from the front surface side, a p-type semiconductor region 4 reaches the semiconductor substrate body 2 so as to bisect the semiconductor layer 3 into n-type semiconductor regions 5 and 6.
Or, it is formed to a depth that cannot be reached (in the figure, the depth that can be reached). Further, when the electrode 7 is formed on the semiconductor region 4 to a depth where the semiconductor region 4 reaches the semiconductor substrate body 2,
If it is ohmically formed to a depth that cannot be reached,
attached to form a Schottky junction. Further, electrodes 8 and 9 are ohmically attached to semiconductor regions 5 and 6, respectively. The above is the structure of the conventionally proposed transistor. A transistor having such a configuration has a semiconductor substrate 1.
If the semiconductor region 4 has a configuration in which the electrodes 7.8 and 9 are arranged side by side on the top, and the semiconductor region 4 is formed to a depth that reaches the semiconductor substrate body 2, the semiconductor regions 4.5 and 6 are respectively placed on the base. The transistor functions as a horizontal bipolar transistor with electrodes 7.8 and 9 serving as a base electrode, an emitter electrode, and a collector electrode, respectively. When the semiconductor regions 4.5 and 6 are formed as a gate region, a source region and a drain region, respectively, and the electrodes 7.8 and 9 are respectively formed as a gate electrode, a source electrode and a drain electrode, it functions as a field effect transistor. do.

[Problem to be solved by the invention]

By the way, in a transistor having a configuration in which electrodes 7, 8 and 9 are arranged side by side on a semiconductor substrate 1 as shown in FIG. 4, the semiconductor region 4 is It is desirable that the length in the direction connecting regions 5 and 6 is as short as possible. However, in this case, it is desirable that the volume of the electrode 7 placed on the semiconductor region 4 be as large as possible even if the length of the semiconductor region is short. Similarly, in order to obtain good high frequency characteristics, it is desirable that the distance between each of the electrodes 8 and 9 and the electrode 7 be as short as possible. However, in the conventional manufacturing method of a transistor having the above-mentioned configuration, the above-mentioned electrodes 7.8 and 9 are
It has been difficult to form the film in a manner that satisfies the above-mentioned desired requirements, either by photolithography or by a processing method using an electron beam. Therefore, the present invention aims to propose a novel method for manufacturing a transistor that is free from the above-mentioned conventional difficulties.

[Means to solve the problem]

The method for manufacturing a transistor according to the present invention involves the following sequential steps to manufacture a transistor having a configuration similar to the conventional transistor described above in FIG. 4. That is, on the semiconductor substrate, first and second
forming first and second insulating layers, each having an inner surface. Next, a first semiconductor region into which impurities are introduced is formed in the semiconductor substrate by an impurity introduction process using the first and second insulating layers as masks. Next, the first and second inner surfaces of the first and second insulating layers are milled by a first milling process using an ion beam directed from a direction oblique to the upper surfaces of the first and second insulating layers. They are formed on the first and second inclined inner surfaces, the distance between which increases from the semiconductor region side to the opposite side. Next, on the first inclined inner surface of the first insulating layer and the second inclined inner surface of the second insulating layer, on the upper surfaces of the first and second insulating layers, and on the first semiconductor A first electrically conductive layer is formed that extends continuously over a region facing between the first and second sloped inner surfaces of the region. Next, the first and second conductive layers are connected to the first conductive layer.
A second milling process using an ion beam from a direction oblique to the top surface of the insulating layer causes the first conductive layer to be connected to the sixteenth semiconductor region and to be connected to the first semiconductor region.
and forming a first electrode extending on the second inclined inner surface. Next, a dry etching process is performed on the first and second insulating layers in a direction perpendicular to their upper surfaces using the first electrode as a mask to remove the first and second insulating layers from the first and second insulating layers. first and second inclined inner surfaces, respectively, the first and second inclined inner surfaces facing the first and second inclined inner surfaces, respectively, and perpendicular to the upper surface of the semiconductor substrate;
forming third and fourth insulating layers, each having a vertical outer surface. Next, the first vertical outer surface of the first electrode, the first vertical outer surface of the third insulating layer, the second vertical outer surface of the fourth insulating layer, and the semiconductor substrate are viewed from above. A second conductive layer is formed continuously extending over the second and third semiconductor regions sandwiching the first electrode. Next, the third and fourth conductive layers are connected to the second conductive layer.
A third milling process using an ion beam from a direction oblique to the first and second vertical outer surfaces of the respective insulating layers of the second conductive layer and the second and third forming second and third electrodes connected to the semiconductor region of the semiconductor region and separated from the first electrode and separated from each other on the first and second vertical outer surfaces; The above is the method for manufacturing a transistor according to the present invention.

[Action/effect]

The transistor manufactured by the transistor manufacturing method according to the present invention has a structure in which first, second, and third electrodes are arranged in parallel on a semiconductor substrate, similar to the conventional transistor described above in FIG. , and the first, second and third semiconductor regions are respectively a base region, an emitter region and a collector region, and the first, second and third electrodes are a base electrode, an emitter electrode and a collector electrode, respectively. The first, second and third semiconductor regions may be used as a gate region, a source region and a drain region, respectively, and the first, second and third semiconductor regions may be made to function as a bipolar transistor.
It is also possible to function as a field effect transistor in which the third electrode is used as a gate electrode, a source electrode, and a drain electrode, respectively. However, according to the method for manufacturing a transistor according to the present invention, even if the first semiconductor region is formed so that its length in the direction connecting the second and third semiconductor regions is sufficiently short, the first semiconductor region The first electrode on the region can be easily formed to have a large volume and be mechanically strong compared to the case of conventional transistor manufacturing methods. Furthermore, the distance between the second and third electrodes and the first electrode is much shorter than in the case of conventional transistor manufacturing methods, making it possible to easily form the second and third electrodes. can. Therefore, according to the method for manufacturing a transistor according to the present invention, it is possible to easily manufacture a transistor that exhibits significantly better high frequency characteristics and is mechanically strong compared to the conventional method for manufacturing a transistor.

Embodiment 1 Next, a first embodiment of a method for manufacturing a transistor according to the present invention will be described with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 4 are designated by the same reference numerals. The method for manufacturing a transistor according to the present invention shown in FIG. 1 takes the following sequential steps to manufacture a transistor having complementarity similar to the conventional transistor manufacturing method described above in FIG. 4. That is, a semi-insulating semiconductor substrate body 2 made of GaAS, for example, is prepared in advance (FIG. 1A). Therefore, on the semiconductor substrate body 2, for example, GaAS
A semiconductor layer 3 having an n-type conductivity is formed by various methods known per se, thereby obtaining a semiconductor substrate 1 in which a semiconductor layer 3 is formed on a semiconductor substrate body 2 (first flash B). ). Next, on the semiconductor substrate 1, that is, on the semiconductor layer 3, insulating layers 11 and 12 having inner surfaces 11a and 12a facing each other and made of SiO2, for example, are formed by various methods known per se. form (Figure 1C). In this case, the insulating layers 11 and 12 may be formed such that their respective inner surfaces 11a and 12a are perpendicular to the upper surface of the semiconductor layer 3 and are spaced from each other by, for example, 0.1 μm. Next, a p-type impurity is introduced into the semiconductor substrate 1 from the upper surface side of the semiconductor layer 3 using the insulating layers 11 and 12 as a mask, so that the semiconductor region 4 into which the impurity has been introduced is formed into the semiconductor layer 3. It is formed to a depth that reaches the semiconductor substrate body 2 so as to divide it into two n-type semiconductor regions 5 and 6 (the first
Flash B). In this case, the p-type impurity introduction treatment is Be, M
It can be used as an ion implantation process for ions such as a, Zn, and Cd. The insulating layers 11 and 12 are then subjected to a milling process known per se using an ion beam obliquely directed to their upper surfaces. 11 inner surface 11
a1 and the inner surface 12a of the insulating layer 12 are respectively formed into inclined inner surfaces 11b and 12b, which are spaced apart from each other from the semiconductor region 4 side to the opposite side (upwards) (see FIG. 1E). ). In this case, the milling process is performed by adjusting the oblique angle of the ion beam with respect to the insulating layers 11 and 12 so that the inclined inner surfaces 11b and 12b are not in contact with the semiconductor region 4. In practice, the inclined inner surfaces 11b and 12b are the same as the side surfaces 11a and 12b.
This is done so that a relationship of contact at the same position as 2a is obtained. Next, a continuous layer is formed on the inclined inner side surface 11b of the insulating layer 11 and the inclined inner side surface 12b of the insulating layer 12, on the upper surfaces of the insulating layers 11 and 12, and on the area facing between the inclined inner surfaces 11b and 12b of the semiconductor region 4. The electrically conductive conductor B13, which extends to 100 mm, is formed by various methods known per se (FIG. 1F). In this case, the conductive layer 13 is formed by vapor deposition, for example, T
It can be formed into a laminated structure of an i layer, a pt layer, and an AU layer. Next, by milling the conductive layer 13 using an ion beam from an oblique direction with respect to the upper surfaces of the insulating layers 11 and 12, the conductive layer 13 is ohmically connected to the semiconductor region 4 and the insulating layer 13 is ohmically connected to the semiconductor region 4. Electrodes 7 are formed that do not extend over the upper surfaces of the insulating layers 11 and 12, but extend over the inclined inner surfaces 11b of the insulating layer 11 and the inclined inner surfaces 12a of the insulating layer 12 (FIG. 1G). Next, by dry etching the insulating layers 11 and 12 from the direction perpendicular to their upper surfaces, using the electrode 7 as a mask and which is known per se, the insulating layers 11 and 12 are etched within the above-mentioned slope. An insulating layer 11 having side surfaces 11b and 12b, respectively, and vertical outer surfaces 11c and 12c, respectively, facing the inclined inner surfaces 11b and 12b and perpendicular to the upper surface of the semiconductor substrate 1.
' and 12' (Fig. 1H). In this case, 02F6 gas may be used for the dry etching process. Next, on the electrode 7, on the vertical outer surface 11c of the insulating layer 11', on the vertical outer surface 12c of the insulating layer 12', and on the semiconductor regions 5 and 6 of the semiconductor layer 3, with the electrode 7 sandwiched therebetween, as seen from above. A continuously extending electrically conductive layer 14 is formed by various methods known per se (FIG. 1I). in this case,
The conductive layer 14 can be formed, for example, into a stacked structure of an AuGe alloy layer, a Ni layer, a Ti layer, and an Au layer by the vaporization method. Next, insulating layers 11' and 12' for conductive layer 14
The conductive layer 1 is formed by milling using an ion beam (indicated by 15 in FIG. 1) from an oblique direction on the vertical outer surfaces 11c and 12G of the
4, electrodes 7 are ohmically connected to the semiconductor regions 5 and 6 and on the vertical outer surfaces 11c and 12C, respectively.
electrodes 8 and 9 which are separated from each other and separated from each other;
(Fig. 1 J). Note that in this case, the conductive layer 1
3 remains on the electrode 7 as indicated by 14'. In this case, the milling process is performed on the vertical outer surfaces 11C and 1 of the insulating layers 11' and 12' of the ion beam 15, respectively.
Vertical outer surface 11 relative to the oblique angle α relative to 2c
The relationship between Ray 1~ where c and 12c are milled is the second
The relationship of the rate at which areas on the vertical outer surfaces 11C and 12C of the conductive layer 14 are milled for a similar angle α is obtained as shown by curve 16 in FIG.
The above-mentioned angle α is appropriately selected by effectively utilizing the fact obtained as shown in 7. In such a case, the portions of the conductive layer 14 on the vertical outer surfaces 11c and 12C of the insulating layers 11' and 12' may overlap the vertical outer surfaces 11C and 12C.
electrodes 8 and 9 are reliably separated from electrode 7;
In addition, they are formed separately from each other. The above is the first embodiment of the method for manufacturing a transistor according to the present invention. The transistor manufactured by the method for manufacturing a transistor according to the present invention has a structure in which electrodes 7, 8 and 9 are arranged in parallel on the semiconductor substrate 1, similar to the conventional transistor described above in FIG. Then, it functions as a horizontal bipolar transistor in which semiconductor regions 4.5 and 6 serve as a base region, an emitter region, and a collector region, respectively, and electrodes 7.8 and 9 serve as a base electrode, an emitter electrode, and a collector electrode, respectively. However, according to the first embodiment of the method for manufacturing a transistor according to the present invention shown in FIG. 1, the semiconductor region 4 is formed so that its length in the direction connecting the semiconductor regions 5 and 6 is sufficiently short. Also, the electrode 7 on the semiconductor region 4 is connected to the inclined inner surfaces 11b and 12 on the insulating layers 11' and 12'.
Since it also extends over b, it can easily have a larger volume than in the case of conventional transistor manufacturing methods.
Moreover, it can be formed mechanically strong. In addition, since the electrodes 8 and 9 are formed in a self-aligned manner, the distance between each of them and the electrode 7 is much shorter than in the case of conventional transistor manufacturing methods, making it easy to use. can be formed into Therefore, according to the method for manufacturing a transistor according to the present invention shown in FIG. 1, it is possible to easily manufacture a transistor that exhibits significantly better high frequency characteristics and is mechanically strong compared to the conventional method for manufacturing a transistor. can do.

Embodiment 2 Next, a second embodiment of the method for manufacturing a transistor according to the present invention will be described. A second embodiment of the method for manufacturing a transistor according to the present invention is similar to the first embodiment of the method for manufacturing a transistor according to the present invention described above with reference to FIGS. As shown in FIG. 3 corresponding to FIG. J, the electrodes 7 are formed at a depth that does not reach the semiconductor substrate body 2, and
The same steps as in the first embodiment of the method for manufacturing a transistor according to the present invention described above with reference to FIGS. to manufacture transistors. The transistor manufactured by the transistor manufacturing method according to the present invention as described above has electrodes 7, 8 and 9 on the semiconductor substrate 1, similar to the transistor manufactured by the transistor manufacturing method according to the present invention described above with reference to FIG. 1J. The semiconductor regions 4.5 have a configuration in which they are arranged in parallel.
and 6 are respectively gate regions, source regions and drain regions, and electrodes 7.8 and 9 are gate electrodes, respectively.
It functions as a field effect transistor with a source electrode and a train electrode. However, the second method of manufacturing a transistor according to the present invention
Although detailed explanation will be omitted in the case of the embodiment, the same excellent effects as in the first embodiment of the method for manufacturing a transistor according to the present invention described above with reference to FIGS. 1A to 1 can be obtained. Note that the above description merely shows two embodiments of the method for manufacturing a transistor according to the present invention, and various modifications and changes may be made without departing from the spirit of the present invention.

[Brief explanation of the drawing]

FIGS. 1A to 1J are cross-sectional views showing sequential steps of a first embodiment of the method for manufacturing a transistor according to the present invention. FIG. 2 shows that by milling a conductive layer extending also on the vertical outer surface of the insulating layer for purposes of illustration,
from the conductive layer, the part of the conductive layer on the vertical outer surface of the insulating layer relative to the vertical outer surface of the insulating layer in the direction of the ion beam, and the insulating layer in the direction of the ion beam when forming mutually separated electrodes; FIG. 3 is a diagram showing the relationship between the rates at which the vertical outer surface of the wafer is milled; FIG. 3 is a cross-sectional view in the final step, showing a second embodiment of the method for manufacturing a transistor according to the present invention. FIG. 4 is a cross-sectional view showing a conventional transistor. 1... Semiconductor substrate 2
・・・・・・・・・・・・・・・・・・Semiconductor substrate body 3・・・・・・・・・・・・・・・・・・：Semiconductor layer 4.
5.6... Semiconductor region 7.7.9... Electrodes 11.12.11', 12'...... Insulating layer 13.1
4...... Conductive layer 15...
......Ion beam 11a112a
...Inner surfaces 11b, 12b...Slanted inner surfaces 11G, 12C...Vertical outer surfaces Applicant Nippon Telegraph and Telephone Corporation @1 Figure 1 Figure 2

Claims (1)

[Scope of Claims] A step of forming, on a semiconductor substrate, first and second insulating layers having first and second inner surfaces facing each other, respectively; and a step of forming a first semiconductor region into which the impurity is introduced by an impurity introduction process using the second insulating layer as a mask; By a first milling process using an ion beam from a direction, the first and second inner surfaces are
forming first and second inclined inner surfaces of the first insulating layer, the distance between which increases from the semiconductor region side to the opposite side; and the first inclined inner surface of the first insulating layer. and a region facing on the second inclined inner surface of the second insulating layer, on the upper surfaces of the first and second insulating layers, and between the first and second inclined inner surfaces of the first semiconductor region. The first extending continuously upwards
and a second milling process on the first conductive layer using an ion beam from a direction oblique to the upper surfaces of the first and second insulating layers. forming a first electrode from the first conductive layer that is connected to the first semiconductor region and extends on the first and second inclined inner surfaces; By dry etching the second insulating layer from the first and second insulating layers in a direction perpendicular to their upper surfaces using the first electrode as a mask, the first and second inclined inner surfaces are etched from the first and second insulating layers. third and fourth insulators each having first and second vertical outer surfaces facing the first and second inclined inner surfaces and perpendicular to the top surface of the semiconductor substrate, respectively; forming a layer on the first electrode, on the first vertical outer side of the third insulating layer, on the second vertical outer surface of the fourth insulating layer, and on the semiconductor substrate from above. A second semiconductor region extending continuously over the second and third semiconductor regions sandwiching the first electrode is shown in FIG.
forming a conductive layer on the second conductive layer, and applying an ion beam to the second conductive layer from a direction oblique to the first and second vertical outer surfaces of the third and fourth insulating layers, respectively. The second and third conductive layers are separated from the second conductive layer by a third milling process using
forming second and third electrodes connected to the semiconductor region of the semiconductor region and separated from the first electrode and separated from each other on the first and second vertical outer surfaces; A method for manufacturing a transistor characterized by comprising: