JPS6387769A - Field effect transistor - Google Patents

Abstract

PURPOSE:To improve the breakdown strength, the power gain, and high frequency characteristics by making a drain taking-out resistance lower without increasing an impurity concentration of a semiconductor substrate by a third region and making an equivalent internal resistance of a second region lower by a fourth region, thereby preparing a gate electrode even on a third region. CONSTITUTION:The difference between diffused depths of a P-type region 43 and an N-type region 44 comes to a channel length and it is well prepared for its length to be minimized. Such a configuration exhibits and excellent high frequency characteristic and then large power gain can be obtained by lowering a drain outflow resistance with the aid of an N-type region 42 located between P-type regions 43 and also lowering a real internal resistance of the P-type regions 43 (that is, an operating internal resistance of a second gate electrode 48) with the aid of a P-type region 43'. Further, a drain voltage is so fed to the surface of the N-type layer 42 through an N<-> type layer 51 surrounded by the P-type regions 43 that the drain breakdown strength becomes higher.

Description

[Detailed description of the invention] The present invention relates to field effect transistors.

Field-effect transistors inherently have excellent frequency characteristics,
Furthermore, since it is thermally stable, it has an excellent advantage in high-frequency, high-output applications.

As an example of a field effect transistor suitable for high frequency and high power applications, an N+ type field effect transistor having an annular P type region within an N- type semiconductor substrate and an annular 1- type region further formed within the N- type semiconductor substrate is used. A semiconductor substrate comprising a gate oxide film on the semiconductor substrate in a region and a gate electrode thereon. The i-plane has seven electrodes, and the N+ region has a source electrode.

In the field effect transistor with this structure, the P-type region that exists under the gate electrode via the gate oxide film operates as a channel, and after the charge passes through this channel,
It passes through a portion of the semiconductor substrate surrounded by the P-type region and is taken out from the drain electrode on the back surface of the semiconductor substrate. Therefore, in such a field effect transistor, the channel length is determined to be shorter than the difference in depth between the P type region and the N+ type region, so it has excellent high frequency characteristics and is suitable for high frequency applications, and the charge is in the P type region. Since it passes through the surrounded portion of the semiconductor substrate and is extracted from the back surface of the semiconductor substrate, a high breakdown voltage can be obtained. Therefore, it is suitable for high voltage and high output applications.

Another advantage of such a configuration is that the channel portion under the gate electrode and the drain electrode are separated from each other, and the feedback capacitance is extremely small.

Furthermore, secondly, the charge is extracted through the semiconductor substrate in the portion surrounded by the P-type region, resulting in normal high voltage output operation. However, the injection
It is determined by the magnitude of the reverse pressure of the P-N junction with the type region. Furthermore, the power gain is limited by the internal resistance of the portion of the semiconductor substrate surrounded by the P-type region. Therefore, if the impurity concentration of the semiconductor substrate is lowered to increase the breakdown voltage, the power gain will decrease.
On the other hand, if the impurities in the semiconductor substrate are increased in order to increase the gain, a problem arises in that the breakdown voltage decreases. Furthermore, since the impurity concentration of the P-type region that acts as a channel is low, the internal resistance of this P-type region cannot be made small, resulting in the problem that the power gain cannot be made small.

The present invention provides a field effect transistor with high breakdown voltage, large power gain, and excellent high frequency characteristics.

According to the present invention, a semiconductor substrate region having a -conductivity type and a first impurity concentration; , a second region of one conductivity type having opposing portions formed in mutually opposing portions of the first region, and a predetermined region of the semiconductor substrate. a third region of one conductivity type and having a third impurity concentration higher than the first impurity concentration formed on the surface of the portion;
a fourth region having a second depth platform of one conductivity type and deeper than the first depth formed in contact with the first region on the opposite side of the second region from the third region; a gate electrode continuously formed on the first region and the third region on the side of the third region from the second region with an insulating film interposed therebetween; and a source electrode in contact with the second region; It has a drain electrode connected to the semiconductor substrate and applies a potential to the first region! Obtain a field effect transistor whose pole is in contact with the fourth region.

According to such a field effect transistor, the drain extraction resistance can be reduced by the third region without increasing the impurity concentration of the semiconductor substrate, and the isomedullary internal resistance of the second region can be reduced by the fourth region, and high power can be achieved. gain can be obtained. Further, since the impurity concentration of the semiconductor substrate can be increased, there is no drop in breakdown voltage, and on the contrary, since the gate electrode is also located on the third region, a high breakdown voltage can be achieved.

Next, the present invention will be explained in more detail with reference to the drawings.

First, a field effect transistor having a structure that is the basis of the present invention will be described with reference to FIGS. 1 to 5, following its manufacturing process.

FIG. 1 shows a semiconductor substrate 41, here several Ω to several tens of Ω.
It is a NW silicon substrate having a resistivity of approximately On the semiconductor substrate 41, there is an N-type region 42 having a resistivity lower than that of the substrate 41 (several hundred mΩ to several tens of Ω), and its thickness is from IRn to several tens of μm.
It is formed at 8 degrees. The region 42 is formed by impurity vapor phase diffusion, solid phase diffusion, ion implantation, epitaxial growth, etc., and the details of the process are known and will be omitted here.

As shown in FIG. 2, on the semiconductor substrate 41 and the N-type region 42, an annular P-type region 43 which becomes a second gate region is selectively formed 11i by impurity diffusion or ion implantation. The depth of the diffusion layer of this P-type region 43 is desirably about 1 prrr=1 μm, and is formed deeper than the N-type region 42 .

Next, as shown in FIG. 3, an N-type region 44 to become a source region is formed inside the P-type region 43 in the same manner as in the formation of the P-type region 43 in FIG. The difference between the depth of the diffusion layer of the P type region 43 and the depth of the diffusion layer of the N type region 44 (, L
l−L, ”) corresponds to the channel length of a field effect transistor, and it is necessary to control it to about several μm from b or less.

FIG. 4 is a diagram illustrating a step of forming an insulating layer 45 that will become a gate insulating film on regions of the P-type region 43 that are opposite to each other. The thickness of the insulator layer 45 is formed to be several hundred to several thousand times thicker.

Next, as shown in FIG. 5, a source electrode 46 is provided on the N-type region 44, a first gate electrode 47 is provided on the insulating layer 45, and a second gate electrode 47 is provided on the KP-type region 43. A drain electrode 49 is provided on the lower surface of the semiconductor substrate 41 . Although aluminum is used as the electrode material, it is particularly preferable to use a semiconductor such as silicon or a metal with good heat resistance, such as molybdenum, for the first gate electrode 47.

The above manufacturing is generally performed by applying planar technology to a silicon substrate, and ultimately a field effect transistor suitable for high frequency, high power applications is formed.

By the way, in the structure shown in FIG. 5, since the overall size is extremely small, the second gate electrode 48 is connected to the P-type region 43.
According to the present invention, as shown in FIG. 6, before the step of FIG. 2 for forming the P-type region 43, two layers of the same P-type region 43' are formed. area 43
VCg on this region 43'
Two gate electrodes 48 are installed. This P
Since the type region 43' has a wide contact area with the second gate 1 [ff148], the internal resistance of the P type region 43, 43' is reduced and the power gain is increased. Further, it is preferable to form the drain electrode 49 on the type layer 52 of the drain region and the N type 142 on the N type layer 151.

According to the present invention, the difference in diffusion depth between the P-type region 43 and the N-type region 44 is the channel length, and this can be made extremely small, resulting in excellent high frequency characteristics.
The drain lead resistance can be reduced by the N2W region 42 between the electrodes 3 and 43, and the effective internal resistance of the P-type region 43 (that is, the operational internal resistance of the second gate 1! pole 48) can be reduced by the P-type region 43', resulting in power gain. can be made larger. Since the drain voltage is applied to the surface of the N-type layer 42 through the N-type layer 51 surrounded by the P-type region 43, the drain breakdown voltage becomes high. This gffXN type layer 42 has a relatively high impurity concentration, making it difficult for the depletion layer to grow from the P type region 43, but the gate electrode above this layer has a gate voltage (this is equal to both the drain potential and the source potential). ) is given, making it easier for the depletion layer to grow. Therefore, the drain breakdown voltage is higher than that of the lower layer.

All opposite conductivity types of the body are used. Further, the P-type region 43 and the N-type region 44 are preferably formed in a round ring shape, but they may be formed in other shapes, or they may be formed in two opposing regions and connected by external wiring. is expected to have the following effects.

As described above, according to the present invention, it is possible to easily realize a field effect transistor that has improved high frequency characteristics, has a high breakdown voltage, and is suitable for high output applications.

[Brief explanation of the drawing]

1 to 5 are cross-sectional views at each step of manufacturing a field effect transistor having a structure that is the basis of the present invention, and FIG. 6 is a cross-sectional view of one embodiment of the present invention. 49...Drain electrode, 46...First
Gate electrode, 48... Second gate electrode, 47.
... Source electrode, 41 ... Semiconductor substrate,
12,43.43'...P type answer 1st eye brown 20th 3rd eye 48th F5 figure 4 da 6th figure

Claims (1)

[Claims] A semiconductor body region of one conductivity type and a first impurity concentration, and a first semiconductor body region of another conductivity type formed so as to have portions facing each other across a predetermined portion on the surface of the semiconductor body region.
a first region having a depth of a third region of the one conductivity type and having a second impurity concentration higher than the first impurity concentration formed on the surface of the semiconductor substrate region between the portions; a fourth region of the other conductivity type formed on the opposite side of the third region and having a second depth deeper than the first depth and in contact with the first region; a gate electrode that is continuously formed on the surface of the first region and the surface of the third region on the side of the third region from the second region with an insulating film interposed therebetween; and a gate electrode that contacts the second region. A field effect transistor comprising a source electrode and a drain electrode connected to the semiconductor substrate region, wherein the electrode applying a potential to the first region contacts the fourth region.