JPH01198063A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To increase the degree of integration and the speed of operation, and reduce manufacturing process, by arranging an emitter region on the main surface part of a base region along the periphery of the base region, and installing an emitter leading-out electrode and a base leading-out electrode which are respectively connected in self alignment manner. CONSTITUTION:A semiconductor region 12 being an emitter region is arranged along the periphery of the main surface part of a base region (semiconductor region 22), and an emitter leading-out electrode 11C is connected. The semiconductor region 12 being the emitter region is formed, by diffusing n-type impurity introduced in the emitter leading out electrode 11c into the main surface part of the base region, and the emitter leading out electrode 11C is connected to the emitter region in the self alignment manner. A base leading-out electrode 21 is connected to a base region (semiconductor region 22), through a connecting hole 20 formed in an interlayer insulating film 19, and a connecting hole defined by a side wall spacer 16 formed on the side wall of the emitter leading-out electrode 11C. A side wall spacer 8 is formed on the side wall of the emitter leading-out electrode 11C by self alignment.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device.

The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device having bipolar transistors or complementary MISFETs.

[Conventional technology]

Bipolar transistor ideal for high driving power and low dissipation gR
Complementary MISFET (CM
A semiconductor integrated circuit device in which O3) is mixed with so-called Bi-CM
O3 is being developed. Bi-CMO9 is the 2ff
Since various types of semiconductor elements are mixed together, the manufacturing process becomes longer than that of a semiconductor integrated circuit device using only a bipolar transistor or a single CMO3.

As a technique for solving this problem, the technique described in Japanese Patent Application No. 116089/1989 previously filed by the applicant of the present application is effective. This technology is used for base extraction electrodes of bipolar transistors, P-channel MIS of 6MO8
The gate electrode of the FET and the gate electrode of the n-channel MI 5FET are made of the same conductive film. The bipolar transistor is constructed of npn type.

B i-6MO8 to which this technology is applied is formed by the manufacturing method described below.

First, a conductor film is formed over the entire surface of the substrate including the bipolar transistor formation region and the 0MO8 formation region. In the bipolar transistor formation region.

The conductive film is formed so as to be in contact with the main surface of the n-type collector region within a region defined by the element isolation insulating film.

In the CMO3 formation region, the conductor film is formed on the channel formation region with a gate insulating film interposed therebetween. As the conductor film, a polycrystalline silicon film is used in which no impurities are introduced to reduce the resistance value.

Next, in the 0MO8 formation region, n
Type impurities are introduced to form an n-type conductor film. After this,
In the bipolar transistor formation region, a p-type impurity is introduced into the conductor film to form the conductor film to be p-type.

Next, the conductor film is subjected to predetermined patterning to form a p-type base extraction electrode and an n-type gate electrode.

The base lead-out electrode is formed on the main surface along the periphery defined by the element isolation insulating film of the collector region and extended from that area to the element isolation insulating crotch.

Next, in the bipolar transistor formation region, the p-type impurity introduced into the base extraction electrode is diffused into the main surface of the collector region to form a p-type base region. The base region is connected to the base extraction electrode in a self-aligned manner.

Next, an emitter extraction electrode is formed so as to be connected to the main surface of the collector region within the region surrounded by the base extraction electrode. The emitter extraction electrode is connected to the main surface of the collector region in self-alignment with the base extraction electrode. The emitter extraction electrode is formed of a polycrystalline silicon film similar to the base extraction electrode.

The emitter extraction electrode and the base extraction electrode are electrically separated. This separation is performed by a sidewall spacer formed in the same manufacturing process as the sidewall spacer formed on the sidewall of each gate electrode of the CMO5.

Next, p-type and n-type impurities are introduced into the main surface of the collector region through the emitter extraction electrode to form a p-type active space region and an n-type emitter region that are integrated with the base region. The emitter region is formed on the main surface of the active base region and is surrounded by the base region.

On the other hand, the CMO 8 sequentially forms a semiconductor region with a low impurity concentration and a semiconductor region with a high impurity concentration after forming the gate electrode. Each of these CMOS is configured with a so-called LDD structure.

The Bi-0MO8 formed in this way has the respective goo 1-1! of the base extraction electrode and 0MO8! Since the poles can be formed using the same conductor film, the manufacturing process can be reduced.

[Problem to be solved by the invention]

Prior to the development of Bi-0MO8 mentioned above, the present inventor discovered that the following problems occurred.

In the bipolar transistor, an emitter region is formed in a region defined by an element isolation insulating film and surrounded by a base region.

In other words, most of the area within the region is occupied by the base region, and a portion thereof becomes the emitter region. For this reason, the current capacity of the bipolar transistor is reduced, resulting in a reduction in operating speed.

In addition, the base extraction electrode of the bipolar transistor and the CMOS (7) husband'r (7) MISFET Tr (7)
Although the gate electrode and the gate electrode are formed of the same conductive film, impurities of different conductivity types are introduced into each film. For this reason.

In order to introduce different impurities into different regions of the conductor film, two mask forming steps and two impurity introduction steps are added, which lengthens the manufacturing process of the semiconductor integrated circuit device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique capable of achieving higher integration and higher operating speed in a semiconductor integrated circuit device having bipolar transistors.

Another object of the invention is to provide bipolar transistors and MI
It is an object of the present invention to provide a technology that can reduce the number of manufacturing steps for achieving the above object in a semiconductor integrated circuit device having an SFET.

Another object of the invention is in Bi-0MO8.

The object of the present invention is to provide a technology that can reduce the number of manufacturing steps to achieve the above object.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device having a bipolar transistor, a base region whose periphery is defined by an inter-element isolation insulating film is provided on the main surface of the collector region of the bipolar transistor, and an emitter is provided on the main surface of the base region along the periphery of the base region. A region is provided, an emitter extraction electrode is provided on the main surface of the emitter region, and an emitter extraction electrode is provided on the main surface of the emitter region, and an emitter extraction electrode is provided on the main surface of the base region within the region defined by the emitter extraction electrode. A base extraction electrode is provided that is connected to the electrode in a self-aligned manner.

Further, in a semiconductor integrated circuit device having a bipolar transistor and a MISFET, the emitter extraction electrode of the bipolar transistor and the gate electrode of the MISFET are formed by introducing impurities of the same conductivity type into a conductor film formed in the same manufacturing process.

Further, in Bi-0MO8, the emitter extraction electrode of the bipolar transistor and each gate electrode of 0MO8 are formed by introducing impurities of the same conductivity type into a conductive film formed in the same manufacturing process.

[For production]

According to the above-mentioned means, it is possible to eliminate mask alignment margins in the manufacturing process between the emitter region and the emitter extraction electrode, and between the emitter extraction electrode and the base extraction electrode, so that the area occupied by the bipolar transistor can be reduced. The bipolar transistor It is possible to increase the emitter current capacity of the device and increase the operating speed.

In addition, since the emitter extraction electrode of the bipolar transistor can be formed in the process of forming the conductor film that forms the gate electrode of the MISFET and the process of introducing impurities into the conductor film, the semiconductor integrated The manufacturing process of the circuit device can be reduced.

In addition, since the emitter extraction electrode of the bipolar transistor can be formed in the step of forming the conductor film forming each gate electrode of 0MO8 and the step of introducing impurities into the conductor film, the Bi -CMO
3 manufacturing steps can be reduced.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a Bi-0MO8 in which an npn type bipolar transistor and a CMO3 are mixed.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

Bi-0MO8, which is an embodiment of the present invention, is shown in FIG. 1 (cross-sectional view of main parts).

As shown in FIG. 1, in Bi-0MO8, a semiconductor element is formed on the main surface of a π-type epitaxial layer 2 laminated on the main surface of a p-type semiconductor substrate 1 made of single crystal silicon. The region of the 0MO8 p-channel MISFET Qp is mainly defined by the element isolation insulating film 8, and is electrically isolated from other regions. The n-channel MISFETQn is
The region is mainly defined by the element isolation insulating film 8 and the p-type channel stopper region 7, and is electrically isolated from other regions. The bipolar transistor Tr mainly consists of a semiconductor substrate 1. Inter-element isolation insulating film 8. p-type channel stopper region7. A p-type well region 6 and a P-type buried semiconductor region (P
The region is defined by an isolation region formed by B L ) 4 and is electrically isolated from other regions.

The bipolar transistor Tr is constructed as shown on the left side of FIG. 1 and in FIG. 2 (plan view). The bipolar transistor Tr is composed of an n-type collector region (or emitter region), a p-type base region, and an n-type emitter region (or collector region). That is, the bipolar transistor Tr is constructed of an npn type.

The collector region is an n° type buried semiconductor region (NBL) 3,
It is composed of an n-type well region 5, an n° type semiconductor region (potential pulling collector region) 9, and an n° type semiconductor region 17. The buried semiconductor region 3 is configured to reduce collector resistance.

The base region is composed of a p-type semiconductor region 22. The semiconductor region 22, which is the base region, is provided on the main surface of the well region 5, which is the collector region, and its periphery is defined by the element isolation insulating film 8. In other words, the base region is formed in self-alignment with the inter-element molecule lJl insulating film 8.

The emitter region is composed of a go-type semiconductor region 12.

The semiconductor region 12 which is an emitter region has the base region (
It is provided on the main surface of the semiconductor region 22) along the periphery of the base region. As shown in FIG. 2, this emitter region is configured to surround, in plan, a portion of the base region connected to a base extraction electrode 21, which will be described later.

A collector lead-out wiring 26 is connected to the semiconductor region 17 of the collector region of the bipolar transistor Tr.

The wiring 26 is connected to the semiconductor region 17 through a contact hole 25 formed in the interlayer insulating films 19 and 24. Wiring 2
Reference numeral 6 is formed in the first layer wiring forming process and is made of, for example, aluminum or aluminum to which a predetermined additive (Si or Cu) is added.

An emitter extraction electrode (first extraction electrode) 11C is connected to the semiconductor region 12 of the emitter region. The emitter extraction electrode 11C is not numbered, but is MISF
It is connected to the semiconductor region 12 through a connection hole formed by removing an insulating film corresponding to the gate insulating film 10 of ETQn and Qp. The emitter extraction electrode 11C is made of high melting point metal silicide (WSi, MoSi, etc.) on a polycrystalline silicon film.
, TaSi, , TiSi, ) films are formed. An n-type impurity (P or As) is introduced (or diffused) into the polycrystalline silicon film to reduce the resistance value. In addition, the emitter extraction electrode 11C is a polycrystalline silicon film (n type).
It may be composed of a single layer. The emitter extraction electrode 11C is formed in the first layer gate wiring formation process. 1st
In the step of forming the gate wiring layer, the emitter extraction electrode 11
In addition to C, the gate electrode 11 of MISFETQn, which will be described later.
A, the goo 1 electrode 11B of MISFET Qp are formed respectively. The semiconductor region 12, which is the emitter region, is an
The emitter extraction ffi pole 11 is formed by diffusing type impurities into the main surface of the base region.
C is connected in self-alignment to the emitter region.

The connection area between the emitter extraction electrode 11C and the emitter region (semiconductor region 12) is at least the connection area for flowing a predetermined amount of current and the manufacturing process between the emitter extraction electrode 12 and the element isolation insulating film 8. It is defined by the mask alignment margin area in . As shown in FIG. 2, an emitter lead-out wiring 26 is connected to the emitter lead-out electrode 11C.

A base lead-out wiring 26 is connected to the semiconductor region 22, which is a base region, with a base lead-out electrode 21 interposed therebetween. The base extraction electrode 21 is a connection hole (corresponding to the connection hole 20) defined by a connection hole 20 formed in the first interlayer insulating film 19 and a sidewall spacer 16 formed on the side wall of the emitter extraction 'R, 111G. It is connected to the base region (semiconductor region 22) through.

The base lead-out ff1m2t is formed of, for example, a polycrystalline silicon film doped with P-type impurities. Since the sidewall spacer 8 is formed in self-alignment with the side wall of the emitter extraction electrode 11C, the base extraction electrode 21 is connected to the base region in self-alignment with respect to the emitter extraction electrode 11C. This base extraction electrode 21 is formed in the second layer gate wiring formation step. Bi-0MO8 of this example
Although not shown, it has a built-in SRAM, and the 21st!
In the first gate wiring formation step, in addition to the base lead-out electrode 21, high resistance load elements and power supply wiring of the memory cell of the SRAM are formed. Base drawer wiring 2
6 is connected to the base drawer mold tizt through a connection hole 25 formed in the interlayer insulation g24. This base lead-out wiring 26 is formed in the first layer wiring formation process.

In this way, in a semiconductor integrated circuit device having a bipolar transistor Tr, the bipolar transistor Tr
A base region (semiconductor region 2
2), an emitter region (semiconductor region 12) is provided on the main surface of the base region along the periphery of the base region, and an emitter lead-out region is provided on the main surface of the emitter region and connected to the region in a self-aligned manner. An electrode 11C is provided, and a base region (
By providing the base extraction electrode 21 connected in self-alignment to the emitter extraction electrode 11C on the main surface of the semiconductor region 22), the emitter region and the emitter extraction electrode 11G, and the emitter extraction electrode 11C and the base extraction Since it is possible to eliminate the mask alignment margin dimension in the manufacturing process between the base electrode 21 and each other, it is possible to reduce the area occupied by the bipolar transistor Tr, improve the degree of integration, and to increase the area around the base region. This is because the emitter region (semiconductor region 12) can occupy most of the area within the region defined by the element isolation insulating film 8 along the line.

The emitter current capacity of the bipolar transistor Tr can be increased and the operating speed can be increased.

Although the numerical value cannot be limited depending on the size of the bipolar transistor Tr, in the Bi-CMO8 that the present inventor is currently developing, the area ratio of the emitter region and the base region (the connection part with the base extraction electrode 21) of the bipolar transistor Tr is We were able to configure the ratio of 7:2. In other words, the area of the emitter region of the bipolar transistor Tr could be configured to be three to four times the area of the base region.

The n-channel MISFET Qn of the CMO3 is configured as shown on the right side of FIG. MISFETQn is formed on the main surface of the P-type well region 6, and
, a gate insulating film 10, a gate pole 11A, a pair of n-type semiconductor regions 14 serving as source or drain regions, and a pair of n°-type semiconductor regions 17.

Well region 6 constitutes a channel forming region of MISFETQn. For example, the well area 6 has 10
The well region 6 has an impurity concentration of approximately 1017 [atoms/as2F]. A p type buried semiconductor region 4 is provided below the well region 6 to reduce its resistance value.

The gate insulating film 10 is formed using, for example, a silicon oxide film formed by oxidizing the main surface of the well region 6, and has a thickness of about 200 [layers].

The gate electrode 11A is composed of the same conductive film as the emitter lead-out electrode 11C, that is, a composite film in which a refractory metal silicide film is formed on a polycrystalline silicon film. Furthermore, the polycrystalline silicon film is made of n-type material into which the same n-type impurity as the emitter lead-out electrode 11C is introduced (or diffused).

The semiconductor region 14 with a low impurity concentration is connected to the channel forming region side of the semiconductor region 17 with a high impurity concentration. This low impurity concentration semiconductor region 14 has a so-called LDD (
M of the structure
Configure ISFETQn. The semiconductor region 14 with a low impurity concentration is mainly the gate electrode 11A or the insulating film 1 above it.
3 as a mask for impurity introduction, and an n-type impurity (for example, P)
It is constructed by introducing by ion implantation.

The semiconductor region 14 with a low impurity concentration is formed in self-alignment with the gate electrode 11A.

The semiconductor region 17 with high impurity concentration mainly consists of the gate electrode 11
Using the sidewall spacer 16 formed on the side wall of A as a mask for impurity introduction, an n-type impurity (for example, As) is introduced by ion implantation. The high impurity concentration semiconductor region 17 is configured in a self-aligned manner with the gate electrode 11A because the sidewall spacer 16 is configured in a self-aligned manner with the gate electrode 11A.

A wiring 26 is connected to the semiconductor region 17, which is the source or drain region of the MI 5FETQn, through a contact hole 25 formed in the interlayer insulating films 19 and 24. The wiring 26 is made of the same conductor film as the collector lead-out wiring 26, the base lead-out wiring 26, and the emitter lead-out wiring 26, respectively.

The p-channel MISFET Qp of CMO3 is configured as shown in the center of FIG. MISFETQp is n
It is formed on the main surface of the −-type well region 5 and is composed of the well region 5, the gate insulating film 10, the gate electrode 11B, a pair of p-type semiconductor regions 15 serving as source or drain regions, and a pair of p°-type semiconductor regions 18. has been done.

Well region 5 constitutes a channel forming region of MISFETQP. The well region 5 is, for example, 1
The impurity concentration is approximately 0'' to 1017 [atoms/c+n'']. In the lower part of the well region 5, an n° type buried semiconductor region 3 is provided which reduces the resistance value similarly to the well region 6.

The gate insulating film 10 is formed in the same manufacturing process as the gate insulating film 10 of the MISFETQn.

The gate electrode 11B is composed of the same conductive film as the base extraction electrode 11C and the gate electrode 11A, that is, a composite film in which a refractory metal silicide film is formed on a polycrystalline silicon film. Moreover, the polycrystalline silicon film is made of n-type into which T1 type impurities of the same conductivity type as the impurities introduced into the polycrystalline silicon films of the gate electrode 11A and the emitter lead-out electrode 11C are introduced (or diffused). has been done.

The semiconductor region 15 with a low impurity concentration is a MISF with an LDD structure.
Configure ETQp. The low impurity concentration semiconductor region 15 is formed in self-alignment with the gate electrode 11B, similar to the low impurity concentration semiconductor region 14. The highly impurity-concentrated semiconductor region 18 is self-aligned with the gate electrode 11B with sidewall spacers 16 interposed therebetween.

A wiring 26 is connected to the semiconductor region 18 which is the source or drain region of the MISFET Qp through a connection hole 25 formed in the interlayer insulating films 19 and 24.

Next, regarding the specific manufacturing method of the above-mentioned Bi-CMOS, FIGS. 3 to 11 (B1-C shown for each manufacturing process)
This will be briefly explained using a cross-sectional view of a main part of a MOS.

First, a p-type semiconductor substrate 1 is prepared. The semiconductor substrate 1 used has a resistivity of, for example, about 10 [Ω·anl].

Next, n-type impurities are selectively introduced into the main surfaces of the bipolar transistor Tr formation region and the p-channel MISFET QP formation region of the semiconductor substrate 1, respectively. Thereafter, p-type impurities are selectively introduced into the main surface of each of the n-channel MISFET Qn formation region and the element isolation region of the semiconductor substrate 1.

Next, an n-type epitaxial layer 2 is grown on the main surface of the semiconductor substrate 1 into which each of an n-type impurity and a p-type impurity is implanted. By this growth of the epitaxial layer 2, an n° type buried semiconductor region 3 and a p′ type buried semiconductor region 4 are formed between the semiconductor substrate 1 and the epitaxial layer 2, respectively.

Next, the bipolar transistor T of the epitaxial layer 2
An n-type well region 5 is formed on the main surface of each of the r formation region and the p channel MISFET Qp formation region. After this,
n-channel MISF of the epitaxial layer 2
A p-type well region 6 is formed on the main surface of each of the E T Q n formation region and the element isolation region.

Next, an inter-element isolation insulating film 8 is formed on the main surface between the half-core element forming regions of the well regions 5 and 6. A p-type channel stopper region 7 is formed on the main surface of the well region 6 under the element isolation insulating film 8 in substantially the same manufacturing process as that for forming the element isolation insulating film 8. The element isolation insulating film 8 is formed to have a thickness of, for example, about 6,000 to 8,000 [layers].

Next, a thin silicon oxide film is formed on each main surface of the well region 5.6. This silicon oxide film is formed to reduce heavy metal contamination and damage to the surfaces of the well regions 5 and 6 caused by the introduction of impurities.

Next, an n-type semiconductor region 9 is selectively formed in the main surface of the region where the collector region of the bipolar transistor Tr in the well region 5 is formed. The semiconductor region 9 is, for example, 101s[
It is formed by introducing P of about 80 [K e V] by ion implantation with an energy of about 80 [K e V].

Next, threshold voltage adjusting impurities are selectively introduced into the main surface of the MISFET QP formation region of the well region 5 and the main surface of the MISFETQn formation region of the well region 6, respectively. This threshold voltage adjustment impurity is a p-type impurity (B)
The P-type impurity is introduced into the main surface portions of the well regions 5 and 6 through the silicon oxide film by ion implantation.

Next, as shown in FIG. 3, a region other than the element isolation insulating film 8 is formed. Well area5. A gate insulating film 10 is formed on each main surface of well region 6 .

The gate insulating film 10 covers each main region of the well region 5.6.
- Using a silicon oxide film formed by oxidizing the surface, it is formed to a thickness of about 200 [layers] as described above.

Next, as shown in FIG.
A p-type semiconductor region 22 is formed to be used as a base region of r. The semiconductor region 22 is, for example, I x 10''[
It is formed by introducing B of about 20 [K e V] by ion implantation with an energy of about 20 [K e V]. When introducing this impurity, the element isolation insulating film 8 is used as a mask for introducing the impurity. Note that when introducing impurities, other element regions other than the base region are covered with an impurity introduction mask, for example, a photoresist film. It is formed on the main surface of.

Next, as shown in FIG.
The gate insulating film 10 in each of the formation regions of the base region and emitter region of r is selectively removed.

Removal of the gate insulating film 10 is a step of removing a portion of the gate insulating film 10 in the CMO8 formation region (not shown) in which the - end of the gate electrode of the lMISFET is extended and directly connected to the source or drain region (direct contact). Performed in the same manufacturing process.

In other words, the manufacturing process is not increased for removing the gate insulating film 10 in the formation regions of the base region and the emitter region.

Next, as shown in FIG. 6, the bipolar transistor T
r, n-channel MISFETQn, P-channel MISF
A conductor film 11 is provided on the entire surface of the substrate including the formation regions of each ETQP.
form. The conductor film 11 is directly connected to the base region (semiconductor region 22) in the formation regions of the base region and emitter region of the bipolar one helangistor Tr, and is formed on the gate insulating film 10 in the collector region.

On the other hand, the conductor film 11 is formed on the gate insulating film 10 in each of the formation regions of MISFETQn and Qp.

This conductive film 11 forms an emitter extraction electrode of the bipolar transistor Tr and a gate electrode of the MISFET. The conductor film 11 is a polycrystalline silicon film deposited by CVD, and an n-type impurity such as P (or As
) is formed of n-type.

N-type impurities are introduced into the entire surface of the polycrystalline silicon film.

In other words, the gate electrode (11A) of MISFETQn
, the gate electrode of MISFETQp (11B), the emitter extraction electrode of bipolar transistor Tr (11C)
) are each formed of an n-type conductor film 11. As shown in FIG. 6, impurities are introduced through a silicon oxide film 11D formed by oxidizing the surface of a polycrystalline silicon film to prevent heavy metal contamination.

Next, after removing the silicon oxide film 11D, a high melting point metal silicide film 11m is formed on the entire surface of the conductor film 11, as shown in FIG. For example, WSi2 formed by sputtering is used as the high melting point metal silicide film 11m. In the high melting point metal silicide film 11m, the underlying conductor film 11 is formed to be n-type in each element region, so even if impurities are diffused from the conductor film 11, no pn junction is formed.

Next, an insulating film 13 is formed on the entire surface of the high melting point metal silicide film 11m. The insulating film 13 is formed using, for example, a silicon oxide film deposited by CVD, and has a thickness of about 2,500 to 3,500 [layers].

Next, the insulating film 13, the high melting point metal silicide film 11m
, conductor film 11 is sequentially subjected to predetermined patterning to form gate electrode 11A, gate electrode 11B, and emitter extraction electrode 11G, respectively, as shown in FIG.

All of these are formed mainly of an n-type conductor film 11. The patterning is performed by anisotropic etching such as RIE. Goo 1 to electrode 11A are n-channel MI
Configures the gate electrode of S F E T Q n. Gate electrode 11B constitutes the gate electrode of p-channel MISFETQP. The emitter extraction electrode 11C constitutes an emitter extraction electrode of the bipolar transistor Tr. As described above, this emitter extraction electrode 11C has one end connected to the main surface of the base region along the periphery of the base region defined by the element isolation insulating film 8, and the other end connected to the element isolation insulating film 8. It is drawn out onto the membrane 8. As shown in FIG. 8, in the emitter extraction electrode 11G, the n-type impurity introduced into the polycrystalline silicon film is diffused into the main surface of the base region (semiconductor region 22) in a self-aligned manner, and the emitter region An n-type semiconductor region 12 is formed. That is, the emitter extraction electrode 11C is connected to the emitter region in a self-aligned manner. By forming the emitter region (semiconductor region 12), the npn bipolar transistor Tr is substantially completed.

Next, the exposed surfaces of the gate electrodes 11A, 11B and the emitter extraction electrode 11C, and the well regions 5.6
An insulating film (not numbered) is formed on each exposed surface. This insulating film can reduce heavy metal contamination and damage caused by introduction of impurities.

Next, using the gate electrode 11A as a mask for impurity introduction, n-type impurities 14n are selectively introduced into the main surface of the well region 6 in the n-channel MISFETQn formation region. n
The type impurity 14n is, for example, toll[atoms/a
P of about m '' 1 is introduced by ion implantation with an energy of about 80 K e Vl. After this, as shown in FIG. A p-type impurity 15p is introduced into the main surface of the well region 5 in the MISFETQp formation region.
The type impurity 15p is, for example, 1013 [atoms/an
”] is introduced by ion implantation with an energy of about 80 [K e V]. The n-type impurity 14rl is introduced in self-alignment with the gate electrode 11A, and the p-type impurity 15p is introduced with respect to the gate electrode 1113. Introduced with self-alignment.

Next, sidewall spacers 1 are placed on the sidewalls of the gate electrodes 11A, 1113 and the emitter extraction electrode 11G.
form 6. The sidewall spacer 16 is formed by forming a silicon oxide film on the entire surface of the substrate by CVD, and applying R to this silicon oxide film.
It can be formed by anisotropic etching such as IE.

Next, using the sidewall spacer 16 as a mask for impurity introduction, the n-channel MISFE 'rQ
An n-type impurity is introduced into the main surface of the well region 6 in the n-formation region to form an n◆-type semiconductor region 17.

The n-type impurity is, for example, I O'' [atoms/c
The semiconductor region 17 can be formed by introducing As of about 80 [K e Vl] by ion implantation with an energy of about 80 [K e Vl. By forming this semiconductor region 17, the n-channel MISFETQn is almost completed.

The n-type impurity forming the semiconductor region 17 is also introduced into the main surface of the collector region (semiconductor region 9) of the bipolar transistor Tr.

Next, using the sidewall spacer 16 as a mask for impurity introduction, p-type impurities are introduced into the main surface of the well region 5 in the p-channel MISFET Qp formation region, and as shown in FIG. Form ridge 18. For example, the p-type impurity is 1016 [atomg/aa”]
It can be formed by introducing BF2 of about 80 K e Vl by ion implantation. The semiconductor region 18 is formed in self-alignment with the gate electrode 11B with the sidewall spacer 8 interposed therebetween. By forming this semiconductor region 18, the p-channel MI SFE TQp is substantially completed.

Next, an interlayer insulating film 19 is formed to cover the entire surface of the substrate, and a connection hole 20 is formed by removing a region of the interlayer insulating film 19 where the base extraction electrode (21) of the bipolar transistor Tr is formed. The substantial opening size (connection area between the base extraction electrode and the base region) of the connection hole 20 is defined by the sidewall spacer 16 formed on the side wall of the emitter extraction electrode ttc. The connection position between the base extraction electrode of the connection hole 20 and the base region is defined by self-alignment with respect to the emitter extraction electrode 11G. Connection hole 2
The opening formed in the interlayer insulating film 19 is made larger than the opening dimension defined by the sidewall spacer 8 by at least an amount corresponding to the mask alignment allowance dimension in the 12-manufacturing process.

Next, as shown in FIG. 11, a base extraction electrode 21 is formed on the interlayer insulating film 19 so as to be connected to the surface of the base region (semiconductor region 22) through the connection hole 20. The base extraction electrode 21 is formed, for example, by introducing a p-type impurity (B) into a polycrystalline silicon film deposited by CVD.

Next, the interlayer insulating film 24, the connection hole 25, and the wiring! By sequentially forming the fA 26, the Bi-CMO 8 of this embodiment shown in FIGS. 1 and 2 is completed.

In this way, bipolar transistor Tr and MISF
In a method for producing Bi-CMO8 having ETQn,
The MISFET Qn is formed on the main surface of the collector region (well region 5) of the bipolar transistor Tr, on the main surface of the base region (semiconductor region 22) whose periphery is defined by the element isolation insulating film 8, and with the gate insulating film 10 interposed therebetween. A step of forming a conductive film 11 whose conductivity type can be controlled by introducing impurities over the entire surface of the substrate including the main surface of the channel forming region (well region 6), and introducing n-type impurities into the entire surface of this conductive film 11. The conductor film 11 is subjected to a predetermined patterning process, and an emitter extraction electrode (first extraction electrode) 11C is formed on the main surface of the base region along the periphery of the base region. The step of forming the gate electrode 11A on the insulating film 10, and the step of forming the emitter extraction electrode 1 on the insulating film 10.
A step of diffusing the n-type impurity introduced into 1C into the main surface of the base region and forming an emitter region (semiconductor region 12) in self-alignment with respect to the emitter extraction electrode 11C, and a step defined by the emitter extraction electrode 11G. A base extraction electrode (second extraction electrode) connected in self-alignment to the emitter extraction electrode 11C on the main surface of the base region in the area where the emitter extraction electrode 11C is formed.
21, the MIS
In the process of forming the conductor film 11 that forms the gate electrode 11A of the FETQn and the process of introducing n-type impurities into the conductor film 11, the emitter lead-out type of the bipolar transistor Tr?
411c, the manufacturing process of Bi-0MO8 can be reduced by an amount corresponding to this process. Therefore, the present invention can reduce the manufacturing process for increasing the operation speed of the Bi-CMOS described above.

Further, in the method for manufacturing Bi-0MO8 having bipolar transistor Tr and OMO8, a base region (semiconductor region 22) The conductivity type can be controlled by introducing impurities into the entire surface of the substrate including the main surface of the CMO 8 and the main surface of each channel forming region (well region 5, 6) of the CMO 8 with the gate insulating film 10 interposed therebetween. A step of forming a conductor film 11, a step of introducing n-type impurities into the entire surface of this conductor film 11, and a step of performing predetermined patterning on this conductor film 11 to form a main surface of the base region along the periphery of the base region. A step of forming an emitter extraction 'lX pole (first extraction electrode) 11C on the top, and forming gate electrodes 11A and 1113 on each gate insulating film 10 of the CMO 8;
a step of diffusing the rl type impurity introduced into the emitter extraction electrode 11C into the main surface of the base region to form an emitter region (semiconductor region 12) in self-alignment with the emitter extraction electrode 11C; Extraction electrode 11
forming a base extraction electrode (second extraction voltage Vi) 21 connected in self-alignment to the emitter extraction electrode 11C on the main surface of the base region within the region defined by C. By this, the emitter extraction electrode 11C of the bipolar transistor Tr is formed in the step of forming the conductor film 11 forming the respective gate electrodes 11A and 11B of the CMO 8 and the step of introducing n-type impurities into the conductor film 11. Therefore, the amount of Bi corresponding to this process is
-0 MO8 manufacturing steps can be reduced.

Note that the present invention can be applied to a B1-CMOS having a pnp bipolar transistor. In this case, the emitter extraction ffl pole of the bipolar transistor (
or collector extraction electrode) and p-channel MISFET
(or the gate electrode of the n-channel MISFET) is formed by introducing n-type impurities into a conductor film formed in the same manufacturing process.

Further, the present invention is not limited to the above structure, but broadly B i
- It can be applied to a CMOS, and it can also be applied to a semiconductor integrated circuit device with a single bipolar transistor.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

The degree of integration of a semiconductor integrated circuit device having bipolar transistors can be improved.

It is possible to increase the operating speed.

In addition, bipolar transistors and M I S F E
The number of manufacturing steps for a semiconductor integrated circuit device having T can be reduced.

Moreover, the manufacturing process of Bi-CMOS can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of Bi 0 MO8 which is an embodiment of the present invention, FIG. 2 is a plan view of a bipolar transistor of Bi-CMO 8, and FIGS. 3 to 11 are - It is principal part sectional drawing shown for each manufacturing process of CMO5. In the figure, Tr...bipolar transistor, Qn. Qp... MISFET, 5, 6... Well region, 8
... Side wall spacer, 10... Gate insulating film, 11A, IIB... Gate electrode, 11C... Emitter extraction electrode, 9, 12, 14, 15.17.1
8.22... Semiconductor region, 21... Base extraction electrode.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device having a bipolar transistor, a base region whose periphery is defined by an inter-element isolation insulating film is provided on the main surface of the collector region or emitter region of the bipolar transistor, and the base region An emitter region or a collector region is provided on the main surface of the base region along the periphery of the emitter region or the collector region, a first extraction electrode is provided on the main surface of the emitter region or the collector region and connected to the region in a self-aligned manner; 1. A semiconductor integrated circuit device comprising: a second lead-out electrode connected to the first lead-out electrode in a self-aligned manner on a main surface of a base region within a region defined by the first lead-out electrode. 2. The first extraction electrode is composed of a conductive film doped with impurities of a predetermined conductivity type, and the emitter region or collector region is formed by diffusing the impurity introduced into the first extraction electrode into the base region. A semiconductor integrated circuit device according to claim 1, characterized in that: 3. In a method of manufacturing a semiconductor integrated circuit device having a bipolar transistor and a MISFET, a gate insulator is provided on the main surface of the base region surrounded by an element isolation insulating film on the main surface of the collector region or emitter region of the bipolar transistor. The MISFET with a membrane interposed
forming a conductive film whose conductivity type can be controlled by introducing impurities over the entire surface of the substrate including the main surface of the channel forming region;
A step of introducing impurities of the same predetermined conductivity type into the entire surface of the conductor film, and performing predetermined patterning on the conductor film to form a first extraction electrode on the main surface of the base region along the periphery of the base region. At the same time, a step of forming a gate electrode on the gate insulating film, and diffusing the impurity introduced into the first extraction electrode into the main surface of the base region so as to be self-aligned with the first extraction electrode. a step of forming an emitter region or a collector region; and a second extraction electrode connected to the main surface of the base region within the region defined by the first extraction electrode in a self-aligned manner with respect to the first extraction electrode. 1. A method of manufacturing a semiconductor integrated circuit device, comprising a step of forming a semiconductor integrated circuit device. 4. In the method of manufacturing a semiconductor integrated circuit device having a bipolar transistor and a complementary MISFET, on the main surface of a base region defined around the main surface of the collector region or emitter region of the bipolar transistor by an inter-element isolation insulating film. and a step of forming a conductive film whose conductivity type can be controlled by introducing impurities over the entire surface of the substrate including the main surface of each channel forming region of the complementary MISFET with a gate insulating film interposed therebetween; a step of introducing impurities of the same predetermined conductivity type into the entire surface, performing predetermined patterning on the conductor film, and forming a first extraction electrode on the main surface of the base region along the periphery of the base region; forming a gate electrode on each gate insulating film of the complementary MISFET; and diffusing the impurity introduced into the first extraction electrode into the main surface of the base region, and forming a gate electrode on the first extraction electrode. a step of forming an emitter region or a collector region in a self-aligned manner; and a second lead-out connected to the main surface of the base region within a region defined by the first lead-out electrode in a self-aligned manner with respect to the first lead-out electrode. 1. A method for manufacturing a semiconductor integrated circuit device, comprising the step of forming an electrode.