JPH01197858A - Information processing controller - Google Patents

Abstract

PURPOSE:To constitute an information processing controller of a simple and small scale by coupling output results of comparators of (n) pieces of flip-flop (P.C-FF) with a preset comparator of each stage by OR logic and inputting them to a shift clock control circuit which has been installed in every stage. CONSTITUTION:At the time of turning on a power source and at the time of resetting, 2<n> kinds of initial values can be set instantaneously by using a preset function. Thereafter, by inputting (n) bit fixed data which is being used at present to a pseudo FIFO, an only stage is selected by a comparator which has been set to P.C-FFs 15(1)-15(n) of each bit. A shift clock operates effectively against this selected stage from the beginning, and the (n) bit fixed data is packed to the first stage of this pseudo FIFO as the data which has been used in the end and sifted. In such a way, the circuit can be constituted simply.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a specific priority order, so-called, for a finite number of data groups handled in information processing.

Least Rec
The present invention relates to an information processing control device that controls an entryUsed (hereinafter abbreviated as LRU) algorithm.

Conventional technology The "LRU" in the LRU algorithm means "least recently used", but this algorithm is a method often used for cache memory control of information processing equipment, and in this case, it uses a finite number of In order to use the cache memory area as effectively as possible, we use control based on the LRU algorithm to update the oldest data stored in the cache memory with new data in order, albeit probabilistically. The aim is to improve system throughput.

In the conventional technology, in order to realize such an LRU algorithm, in the case of the cache memory control described above, time information at the time when certain data in the cache memory is accessed (written or read) is stored in a timer circuit, etc. When the next write access occurs, the time information is generated using , a first-in, first-out method (hereinafter referred to as the FIFO method) was used in which new data was written. FIG. 5 is a simple block diagram of this conventional example, showing a timer circuit 1 that generates time information, a memory 2 that stores time information, a cache memory 3 and a control circuit 4 associated with the time information, and a cache control circuit 5. It consists of In fact, the main control unit and its interface circuit that actually access the cache memory are omitted.

Problems to be Solved by the Invention As is clear from the conventional configuration example described above, the conventional technology requires a timer circuit to generate time information and a circuit such as a memory to store the time information. The control means is also complicated, resulting in an increase in circuit scale.

An object of the present invention is to solve the problem of complicating and increasing the scale of the circuit.

Means for Solving the Problems The present invention provides a D flip-flop with a preset that can be set to "H" level or "L9 level" on the master side, and a D flip-flop that can connect its own stored data and one input from the outside. An n-bit register is configured in the P-C-FF with a D flip-flop having a comparator as the slave side,
The basic configuration is an n-bit, 2n-stage pseudo FIFO in which the positive logic output of the previous-stage PC-FF is connected in series to the input of the next-stage PC-FF, with 2n stages of this register.
This information processing apparatus has a configuration in which each stage is provided with a shift clock control circuit, and this control circuit is controlled by the logical sum of output results from n PC-FF comparators in each stage.

According to the information processing device configured using the above means, when the power is turned on or reset, the preset function is used to
It is possible to set one initial value in an instant,
After that, by inputting the currently used n-bit fixed data into this pseudo FIFO, each bit's P-
A comparator set to C-FF selects only one stage.

The shift clock operates effectively from the initial stage to this selected stage, and the currently used n-bit fixed data is treated as the last used data by this pseudo FIF.
It is packed and shifted to the first stage of O.

EXAMPLES Hereinafter, examples of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a configuration example of an n-bit, 2n-stage pseudo FIFO using PC-FFs.

The master-slave system consists of m master D-latches that can initialize the level to 'H' or 'L', and a slave-side D-latch that has a comparator between its own stored data and one external input. D flip-flop (P-C-F
F) 15(1) to 15(n) constitute an n-bit register, and this register is used for 2n stages of P-C- of the previous stage.
The positive logic output of the FF, so-called Q output, is connected to the next stage P-C.
- Forms a pseudo FIFO with n bits and 2n stages connected in series to the input of the FF, and also connects n P-C-FFs in each stage.
The output results of the comparators are logically summed (OR) for every n bits in each stage.
) The shift clock control circuit 1 is determined by gates 21 (1) to 21 (n) and installed in each stage.
6(1) to 16(n). The shift clock applied to the input terminal 17 is input to the shift clock control circuit 16(1) of the first stage, and the shift clock control circuit of each stage selects the n-bit P-C of its own stage according to the comparison result.
-Controls the clock supply to the FF and the clock supply to the next stage. The data input given to the input terminal 18 is input to the data input terminal of the first-stage p-c-FF, while the data input to all the comparison input data terminals of all the 2n-stage p-c-FFs of the corresponding bit is It is input and the Q output cameras of each preceding stage P-C-FF are compared. In the above configuration, first, each bit P-C-FF of each stage is arbitrarily set to 4Ht or 1L level in terms of hardware by the initial setting signal 19, and the initial value setting of the information processing device is immediately performed. It can be done. When a certain n-bit input data is input as the data currently in use, it is simultaneously compared every n bits for 2n stages, a match detection is performed, and assuming that the m-th stage is selected, the m-th shift Clock control circuit 16 (
1) is activated, the shift lock is enabled for itself, that is, up to the m-th stage, and a shift clock is not supplied to the (m+1)th stage and thereafter. The above operation will be explained using truth diagrams shown in FIGS. 2 and 3. Figure 2 shows the pseudo F in this embodiment at power-on or reset.
This shows how the initial state of IFO is set. Figure 3 shows
It appears that the data currently being used or processed is compared with the data group in the pseudo FIFO, and matching data is detected and the number of stages in which that data is stored is being detected. The data that is
As the latest data, it is shown that the data was packed and shifted to the first stage of the pseudo FIFO, and that the shift operation was performed only for the stage number valves detected above. In this way, pseudo FI
The oldest data is stored in order from the last stage of the FO toward the first stage.

By this operation, the n-bit input data currently in use is packed and shifted from the first stage to the m-th stage, and the input data is registered as the newest data and stored in the final stage as viewed from the output direction of the FIFO. That is, terminal 2
The output data of 0 is the data that was used at the earliest time in the past.

In this way, as is clear from the description of this embodiment, according to the present invention, the information processing control device is used. We can easily create an information processing control device that organizes the past data in order from the oldest out of a finite number of 2n data groups with fixed n bits and controls a certain priority order (LRU algorithm). This can be realized with a configuration. Note that, for convenience of explanation, FIGS. 2 and 3 show an example of the configuration of a 4-bit, 16-stage pseudo FIFO.

FIG. 4 is a diagram showing a configuration example of a master-slave type D flip-flop (P-C-FF) with a preset/comparator. When the power is turned on or reset, the output is set to the I Hl or I L l level by the initial value setting signal 11. The input data 9 is latched into the master O latch 6 and slave D latch 7 by the shift clock 8. The other input data 10 is generated by the output data 12 of this P-C-FF and the comparator 13.
The comparison is made at all times, and the result is outputted from the terminal 14.

As is clear from the detailed description of the invention, according to the present invention, in addition to eliminating the disadvantages such as complication and large-scale circuitry in the prior art, data groups of 2n pieces, which are a finite number with fixed n bits, can be created. It is possible to provide an information processing control device that organizes and stores the data that has been left behind in order from the oldest to the oldest, and controls a certain priority order (LRU algorithm) with a simple and relatively small-scale configuration. Furthermore, as is clear from the embodiments of the invention, the configuration of the present invention can be realized by using simple circuit units multiple times in an array structure, so it also has the effect of being an optimal configuration for a semiconductor integrated circuit. .

[Brief explanation of the drawing]

Figure 1 is a block diagram of the configuration of an embodiment of the present invention, Figures 2 and 3.
The figure is a truth value diagram explaining the present invention in detail, Figure 4 is a configuration diagram of a D flip-flop with preset/comparator (P-C-FF) which is the basic circuit unit of the present invention, and Figure 5 is a conventional example. FIG. 15(1) ~15(n)...-P-C-F F, 1
6(1) to 16 (n)...Shift clock control circuit, 17...Shift clock input terminal, 1
8... Input data input terminal, 19...
Initial value setting signal input terminal, 20...Output data terminal, 21 (1) to 21 (II)...OR
Gate. Name of agent: Patent attorney Toshio Nakao and one other person No. 2rlA Bone No. 3 Figure Schiff) 1 phrase Figure 4/l Figure 5

Claims (1)

[Claims] The master side has a D latch with a preset function that can set the level to 'H' or 'L', and the slave side has a D latch with a comparator between its own stored data and one external input. n by a D flip-flop with preset/comparator (hereinafter abbreviated as P・C-FF)
A bit register is configured, and this register is used for 2^n stages, and the Q output of the previous stage P/C-FF is transferred to the next stage P/C-FF.
An n-bit, 2^n-stage pseudo FI connected in series to the input of
The basic configuration is an FO, and the output results of n P/C-FF comparators in each stage are combined using OR logic and input to the shift clock control circuit installed in each stage. Information processing control device.