JPH0119671B2 - - Google Patents

Info

Publication number
JPH0119671B2
JPH0119671B2 JP56154976A JP15497681A JPH0119671B2 JP H0119671 B2 JPH0119671 B2 JP H0119671B2 JP 56154976 A JP56154976 A JP 56154976A JP 15497681 A JP15497681 A JP 15497681A JP H0119671 B2 JPH0119671 B2 JP H0119671B2
Authority
JP
Japan
Prior art keywords
clock
transmission
signal
circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56154976A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5856549A (ja
Inventor
Tsuguhito Serizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56154976A priority Critical patent/JPS5856549A/ja
Publication of JPS5856549A publication Critical patent/JPS5856549A/ja
Publication of JPH0119671B2 publication Critical patent/JPH0119671B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Small-Scale Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP56154976A 1981-09-30 1981-09-30 バス駆動回路 Granted JPS5856549A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56154976A JPS5856549A (ja) 1981-09-30 1981-09-30 バス駆動回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56154976A JPS5856549A (ja) 1981-09-30 1981-09-30 バス駆動回路

Publications (2)

Publication Number Publication Date
JPS5856549A JPS5856549A (ja) 1983-04-04
JPH0119671B2 true JPH0119671B2 (enExample) 1989-04-12

Family

ID=15595987

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56154976A Granted JPS5856549A (ja) 1981-09-30 1981-09-30 バス駆動回路

Country Status (1)

Country Link
JP (1) JPS5856549A (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4613858A (en) * 1983-10-28 1986-09-23 Sperry Corporation Error isolator for bi-directional communications buses
KR930001922B1 (ko) * 1989-08-28 1993-03-20 가부시기가이샤 히다찌세이사꾸쇼 데이터 처리장치

Also Published As

Publication number Publication date
JPS5856549A (ja) 1983-04-04

Similar Documents

Publication Publication Date Title
US4379327A (en) Universal interface circuit for synchronous and asynchronous buses
US4134073A (en) Clock system having adaptive synchronization feature
US5117443A (en) Method and apparatus for operating at fractional speeds in synchronous systems
JP2914267B2 (ja) 集積回路のデータ転送方法およびその装置
US5903508A (en) Input buffer of memory device for reducing current consumption in standby mode
US3932816A (en) Multifrequency drive clock
EP1051821B1 (en) Arbitration scheme for a serial interface
JPH0119671B2 (enExample)
JPH0326107A (ja) 論理回路
US6510477B2 (en) Bus system
JP3859943B2 (ja) データ送信装置、データ転送システムおよび方法
US6304933B1 (en) Method and apparatus for transmitting data on a bus
US6529570B1 (en) Data synchronizer for a multiple rate clock source and method thereof
US5048061A (en) Method for transmitting information over a bidirectional link, and apparatus for performing the method
JP3246443B2 (ja) 同期式バッファ回路及びこれを用いたデータ伝送回路
JPS6195648A (ja) デ−タ転送方式
JPH07146842A (ja) バスインターフェース回路
JPH0771079B2 (ja) シリアルデ−タ転送装置
US5268931A (en) Data communication system
JPH02125356A (ja) 双方向性バッファ回路
CN117857001A (zh) Mac控制器和数据信号发送方法
KR0145403B1 (ko) 디지탈 시스템의 클럭신호 전송장치
KR101715319B1 (ko) 카운터의 오버플로우 신호를 이용한 차량 통신 송수신기용 딜레이 타이머 회로
JP2504615B2 (ja) 信号伝達タイミング制御方式
JPS61148937A (ja) 半導体集積回路装置