JPH0119397Y2 - - Google Patents
Info
- Publication number
- JPH0119397Y2 JPH0119397Y2 JP1982044487U JP4448782U JPH0119397Y2 JP H0119397 Y2 JPH0119397 Y2 JP H0119397Y2 JP 1982044487 U JP1982044487 U JP 1982044487U JP 4448782 U JP4448782 U JP 4448782U JP H0119397 Y2 JPH0119397 Y2 JP H0119397Y2
- Authority
- JP
- Japan
- Prior art keywords
- pellet
- semiconductor
- pellets
- sheet
- semiconductor pellet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000008188 pellet Substances 0.000 claims description 53
- 239000004065 semiconductor Substances 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 4
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
【考案の詳細な説明】
本考案は半導体装置に関し、特に位置決めを容
易にした半導体ペレツトを有する半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a semiconductor pellet that can be easily positioned.
第1図は樹脂モールド型半導体装置の一例を示
すもので、1は放熱板で、一部に取付け用の穴1
aを穿設し、他部に半導体ペレツト2を半田等に
より固定している。3は3本一組のリードで、中
央のリード3aの一端を半導体ペレツト2近傍の
放熱板1に固定し、他のリード3b,3cを各一
端を半導体ペレツト2の近傍に位置させて、リー
ド3aの両側に平行配列している。4,4はリー
ド3b,3cの各端部と半導体ペレツト2上の電
極とを接続する金属細線、5は半導体ペレツト2
を含む主要部分を被覆した樹脂モールド部であ
る。 Figure 1 shows an example of a resin molded semiconductor device, in which 1 is a heat sink, and a part has holes 1 for mounting.
A is drilled and the semiconductor pellet 2 is fixed to the other part with solder or the like. 3 is a set of three leads, one end of the central lead 3a is fixed to the heat sink 1 near the semiconductor pellet 2, one end of each of the other leads 3b and 3c is positioned near the semiconductor pellet 2, and the leads are connected. They are arranged in parallel on both sides of 3a. 4, 4 are thin metal wires connecting each end of the leads 3b, 3c and the electrodes on the semiconductor pellet 2; 5 is the semiconductor pellet 2;
This is a resin molded part that covers the main parts including.
ここで半導体ペレツト2、例えばサイリスタの
半導体ペレツト2の一例を第2図に示すと、2a
はカソード電極、2bはゲート電極である。そし
て裏面にアノード電極を形成している。 Here, an example of a semiconductor pellet 2, for example a semiconductor pellet 2 of a thyristor, is shown in FIG. 2.
is a cathode electrode, and 2b is a gate electrode. Then, an anode electrode is formed on the back surface.
この半導体ペレツト2は、1枚のウエハ上に複
数個一括して形成され、ペレツト単位に分割され
て製造される。一般に未分割状態のウエハをシー
ト上に貼付し、ダイシング法あるいはスクライブ
法により個々のペレツトに分割し、シートを引き
伸ばすことにより個々のペレツト間に間隙を形成
し取り出しを容易にしている。このようにして個
個に分離された半導体ペレツト2を真空吸着手段
によりシートから引き剥して、一旦整列トレイに
収納したり、シートから引き剥した後、ペレツト
の位置決めをし直ちに放熱板上に供給している。 A plurality of semiconductor pellets 2 are formed on one wafer at once, and then divided into pellet units for manufacture. Generally, an undivided wafer is pasted onto a sheet, divided into individual pellets by dicing or scribing, and the sheet is stretched to form gaps between the individual pellets to facilitate removal. The semiconductor pellets 2 separated into individual semiconductor pellets 2 are peeled off from the sheet by vacuum suction means and temporarily stored in an alignment tray, or after being peeled off from the sheet, the pellets are positioned and immediately supplied onto a heat sink. are doing.
ところで、シートから剥されたペレツトの電極
の位置は一定であるため、整列トレイ内のペレツ
トの方向は一定であり、放熱板上のペレツトの方
向も一定となる。 By the way, since the position of the electrode of the pellet peeled from the sheet is constant, the direction of the pellet in the alignment tray is constant, and the direction of the pellet on the heat sink is also constant.
しかしながら、シートからペレツトを引き剥す
際に、シートが撓み、隣接するペレツトを剥離さ
せ、このペレツトが回転すると、電極の向きが変
ることがあり、これがそのままシート上から取り
出されると、金属細線4によつて半導体ペレツト
2とリード3b又は3cとを接続できないという
問題があつた。 However, when the pellets are peeled off from the sheet, the sheet bends, peeling off adjacent pellets, and when the pellets rotate, the orientation of the electrodes may change. Therefore, there was a problem that the semiconductor pellet 2 and the lead 3b or 3c could not be connected.
また、シートから一旦全てのペレツトを剥離し
て保管する場合にも、放熱板1上に供給する前に
全てのペレツトの電極の方向をそろえなければな
らず、作業が煩雑であつた。 Further, even when all the pellets are once peeled from the sheet and stored, the electrodes of all the pellets must be aligned in the same direction before being supplied onto the heat sink 1, which is a complicated operation.
本考案は上記問題点に鑑み提案されたもので、
電極の方向を考慮することなく位置決めできる半
導体ペレツトを有する半導体装置を提供する。 This invention was proposed in view of the above problems.
Provided is a semiconductor device having a semiconductor pellet that can be positioned without considering the direction of electrodes.
以下、本考案を第3図及び第4図より説明す
る。 The present invention will be explained below with reference to FIGS. 3 and 4.
第3図は本考案を樹脂モールド型半導体装置、
例えば樹脂モールド型サイリスタに適用したもの
で、図において6は半導体ペレツト7を載置する
ペレツト載置部6aを有し、取付用の穴6bを穿
設した基板(放熱板)、8は3本一組のリードで、
平行配置され、中央のリード8aの一端を基板6
のペレツト載置部6a近傍に電気的に接続し、他
のリード8b,8cの一端をペレツト載置部6a
に載置固定した半導体ペレツト7の近傍に位置さ
せている。9,9は半導体ペレツト7の電極とリ
ード8b,8cとを接続した金属細線、10は半
導体ペレツト7を含む主要部分を被覆した樹脂モ
ールド部を示す。 Figure 3 shows the present invention as a resin molded semiconductor device.
For example, it is applied to a resin molded thyristor, and in the figure, 6 has a pellet placement part 6a on which a semiconductor pellet 7 is placed, a substrate (heat sink) with holes 6b for mounting, and 8 indicates three pieces. With a set of leads,
They are arranged in parallel, and one end of the central lead 8a is connected to the substrate 6.
electrically connected to the vicinity of the pellet placing section 6a, and one end of the other leads 8b and 8c to the pellet placing section 6a.
It is located near the semiconductor pellet 7 which is placed and fixed on the substrate. Reference numerals 9 and 9 indicate thin metal wires connecting the electrodes of the semiconductor pellet 7 and leads 8b and 8c, and 10 indicates a resin molded portion covering the main portion including the semiconductor pellet 7.
この半導体装置において、半導体ペレツト7は
第4図に示すような電極を形成している。 In this semiconductor device, the semiconductor pellet 7 forms an electrode as shown in FIG.
即ち、ペレツト中央部にカソード電極7aを形
成しペレツト7の対角線の交点(ペレツトの中
心)より等距離かつ互に等しい角度位置に複数
(図示例では90度位置に4つ)のゲート電極7b
を形成している。 That is, a cathode electrode 7a is formed at the center of the pellet, and a plurality of gate electrodes 7b (four at 90 degree positions in the illustrated example) are formed at equal distances from the intersection of the diagonals of the pellet 7 (the center of the pellet) and at equal angular positions.
is formed.
このペレツト7は図示例ではコーナ部にそれぞ
れゲート電極7bを形成しているから、未分離状
態でシートに貼付されたペレツトをシートから引
き剥す際に、隣接するペレツトが同時に剥離さ
れ、これが回転した状態で取り出されても、ペレ
ツトのコーナ部を基準に位置決めすれば電極の位
置は一定となり、整列トレイ内あるいは基板6上
での半導体ペレツト7の方向を一定にできる。 In the illustrated example, gate electrodes 7b are formed at each corner of the pellets 7, so when the pellets affixed to the sheet in an unseparated state are peeled off from the sheet, adjacent pellets are peeled off at the same time, and the pellets are rotated. Even if the semiconductor pellets 7 are taken out in this state, the position of the electrodes will be constant if the corner portions of the pellets are used as a reference, and the direction of the semiconductor pellets 7 within the alignment tray or on the substrate 6 can be made constant.
また、シートから一旦全てのペレツトを剥離し
保管しておき、これをパーツフイーダ等にて整列
させ、ペレツトのコーナ部を基準に位置決めする
だけで、基板6上に供給できるから製造が容易と
なる。 Further, manufacturing is facilitated because all pellets can be supplied onto the substrate 6 by simply peeling off and storing all the pellets from the sheet, arranging them using a parts feeder, etc., and positioning the pellets based on the corners of the pellets.
尚、本考案は上記実施例にのみ限定されること
なく、例えば樹脂モールド型半導体装置でけでな
く、カン封止形、ガラスモールド型等の半導体装
置にも適用でき、サイリスタだけでなくトランジ
スタにも適用できる。 The present invention is not limited to the above embodiments, and can be applied not only to resin-molded semiconductor devices, but also to can-sealed and glass-molded semiconductor devices, and is applicable not only to thyristors but also to transistors. can also be applied.
第1図は従来の半導体装置の一例を示す部分透
視平面図、第2図は従来の半導体ペレツトの一例
を示す平面図、第3図は本考案による半導体装置
の一例を示す部分透視平面図、第4図は本考案半
導体装置に用いられる半導体ペレツトの一例を示
す平面図である。
6……基板、7……半導体ペレツト、7b……
電極、8,8c……外部リード、9……金属細
線。
FIG. 1 is a partially transparent plan view showing an example of a conventional semiconductor device, FIG. 2 is a plan view showing an example of a conventional semiconductor pellet, and FIG. 3 is a partially transparent plan view showing an example of a semiconductor device according to the present invention. FIG. 4 is a plan view showing an example of a semiconductor pellet used in the semiconductor device of the present invention. 6...Substrate, 7...Semiconductor pellet, 7b...
Electrode, 8, 8c...external lead, 9...metal thin wire.
Claims (1)
リードとを金属細線にて接続したものにおいて、
上記半導体ペレツトの電極をペレツトの中心より
等距離かつ互に等しい角度位置に複数設けたこと
を特徴とする半導体装置。 In the case where the electrode of the semiconductor pellet fixed on the substrate and the external lead are connected with a thin metal wire,
A semiconductor device characterized in that a plurality of electrodes of the semiconductor pellet are provided at equal distances from the center of the pellet and at equal angular positions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982044487U JPS58147248U (en) | 1982-03-29 | 1982-03-29 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982044487U JPS58147248U (en) | 1982-03-29 | 1982-03-29 | semiconductor equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58147248U JPS58147248U (en) | 1983-10-03 |
JPH0119397Y2 true JPH0119397Y2 (en) | 1989-06-05 |
Family
ID=30055543
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1982044487U Granted JPS58147248U (en) | 1982-03-29 | 1982-03-29 | semiconductor equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58147248U (en) |
-
1982
- 1982-03-29 JP JP1982044487U patent/JPS58147248U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS58147248U (en) | 1983-10-03 |
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